JPH0774817B2 - Test method for large scale integrated circuits - Google Patents

Description

DETAILED DESCRIPTION [Overview] A transfer test for transferring data from a memory card to an EEPROM of a system model built as a model on an electronic computer and an operation using a program written in this EEPROM are performed. Regarding the LSI test method for performing the operation test to be confirmed, the LSI under test is manufactured according to the above system model.
For the purpose of shortening the time required for this operation test without increasing the number of pins, the initial value data that specifies the write cycle period is stored at a specific address of the memory card, and this initial value data is also stored. An initial value data buffer is provided in the circuit model of the LSI, and this initial value data is set as the initial value of the cycle counter of the circuit model of the LSI.

[Industrial application field]

At the design stage of a large-scale integrated circuit (hereinafter referred to as LSI), this LSI is built as a model on an electronic computer, and in this model, it is tested whether or not the LSI under design performs the operation as designed. Done.

The present invention relates to a test method for performing a test by this simulation.

[Conventional technology]

FIG. 4 shows an example of a system under test to which the test according to the test method of the present invention is applied. The LSI circuit model 2 and an actual LSI manufactured by this LSI circuit model are shown.
Electrically erasable programmable read only memory (hereinafter referred to as EEPROM) model 16, a buffer model 17 and, for example, static memory (hereinafter referred to as SRAM,
And a control memory model 18 configured by the above), and a program that is to be used after the system under test is actually configured is supplied from the external memory card 1 to execute the simulation operation. To be done.

The above-mentioned EEPROM is a non-volatile memory, and by storing the programs transferred from the memory card 1 in this EEPROM, even if the test is interrupted or the power is cut off, the memory card 1 It is provided to prevent the need for reloading from.

In addition, since all the blocks and circuit elements shown in the drawings of the present application are models built on an electronic computer, in the following description, the description of “model” is omitted to avoid complication. These "models"
When referring to the actual block and circuit element corresponding to, the "actual" is added to the block name or the circuit element name. It should be noted that the same reference numerals are given to the same constituent elements in each conventional example and the embodiment.

The LSI circuit 2 includes a data buffer 6, a data generation circuit 3 having a gate 4 on the input side and a gate 5 on the output side, an EEPROM write address generation circuit 7, an EEPROM read address generation circuit 8, and an SRAM write address generation circuit 9 , SR
At least an AM read address generation circuit 10, gate circuits 11, 12, 13, 14 and a gate control circuit 15 provided on the output side of these address generation circuits are included.

Although processing blocks such as an arithmetic control unit and an input / output control unit are provided according to the functions required for this LSI, the type and number of processing blocks differ depending on the required functions. Since numbers and numbers are not directly related to the present invention, they are not shown or described.

The gate control circuit 15 sequentially outputs the gate signals of G ₁ to G ₈ , the gate signal G ₁ is used as an output enable signal of the external memory card 1, and the gate signal G ₂ is input to the data generation circuit 3. As a conduction control signal for the gate 4, the gate signal G ₃ is sent to the data generating circuit 3 and the output side gate 5
, A gate signal G ₄ is used as a conduction control signal for the output side gate 11 of the EEPROM write address generation circuit 7, and a gate signal G ₅ is used as a conduction control signal for the output side gate 12 of the EEPROM read address generation circuit 8. The gate signal G ₆ is
As the conduction control signal of the output side gate 13 of the SRAM write address generation circuit 9, the gate signal G ₇ is used as the conduction control signal of the output side gate 14 of the SRAM read address generation circuit 7, and
The gate signal G ₈ is applied as the output enable signal of the control memory 18, respectively.

Therefore, the gate signal G ₁ causes the memory card 1
The data from is read out, stored in the data buffer with the gate signal G ₂ , supplied to the EEPROM 16 with the gate signal G ₃ and written to the address supplied from the EEPROM write address generation circuit 7 with the gate signal G _4. This is read by the address from the EEPROM read address generation circuit given by the gate signal G ₅ , and by the write address given to the SRAM 18 by the gate signal G ₆ via the buffer 17.
Written to SRAM 18.

By thus performing data transfer from the memory card 1 to the SRAM 18 via the EEPROM 16 and the buffer 17 for all addresses of the memory card 1, all programs and data on the memory card 1 are transferred to the SRAM 18 via the EEPROM 16. It is desirable that the program and data on the memory card 1 be stored at the same address of the SRAM 18 as the address on the memory card 1.

When the output enable signal of the SRAM 18 is applied by the gate signal G ₈ , the read from the control memory (SRAM) 18 is performed by the gate signal G ₇ from the SRAM read address generation circuit 10 through the gate 14 to the address of this SRAM. It is read from the address given to the terminal.

The system under test operates according to the programs and data sequentially read from the control memory 18, and the system under test including the circuit model of the LSI is evaluated by the electronic computer that executes and monitors the simulation.

Of the various simulations performed on this system under test, the simulations targeted by the present invention are all related to the EEPROM 16, and include a transfer test for testing data transfer from the memory card 1 to the actual EEPROM, This is for an operation test for testing whether or not the expected operation is performed when the system is operated by the program from the memory card stored in this EEPROM.

By the way, one write cycle for an actual EEPROM requires about 10 msec as shown in FIG. This write operation, FIG (a) to indicate the address and Fig (b) together with the data shown in the diagram (a) to the write enable signal is time T ₁ through T ₂ the actual illustrated EEPROM write enable terminal WE Writing is started when given to.

However, in the actual EEPROM, from the start of writing as described above to the end of writing, the actual EE
Depending on the write characteristics of the memory elements that make up the PROM,
Since a long time such as "(can be indefinite)" is required for the actual writing process in the EEPROM in the figure (b), even if the time to start writing is short, once It requires about 10 msec for the write cycle.

When performing the transfer test described above, a write cycle similar to the actual write to the EEPROM is used, and the EEPROM16 of this model is used.
It is necessary to confirm the write operation for.

However, when performing the above-mentioned operation test,
Of course, it is also possible to use the same write cycle as the writing of the EEPROM, but in order to operate the system under test using the program already written in the EEPROM 16 or because the writing operation to the EEPROM 16 is not the test target, The address required to start writing to EEPROM16,
It is sufficient to give the data and the write enable signal.

FIG. 6 shows a main part of a conventional system under test in which the writing cycle to the EEPROM 16 is fixed at 10 msec so that both the transfer test and the operation test can be performed.
EEPROM write address generation circuit 7 provided in circuit 2
3 is a view showing the data generation circuit 3 for supplying the data read from the memory card 1 for writing to the EEPROM 16 and the write enable signal generation circuit 19 together with the EEPROM 16 to be written.

A write cycle of 10 msec to the EEPROM 16 is explained as a cycle counter 71 and a subtraction counter.
EE composed of 72, OR circuit 73, and AND circuit 74
It is generated by the PROM write address generation circuit 7.

That is, the cycle counter 71 is for generating a carry output from the carry terminal CR every 10 msec which is a write cycle of the EEPROM 16, and the memory card 1
Is reset by a reset signal generated at the same time as mounting, the fixed value given to the data terminal D is loaded, and a constant value such as "1" is added every time the clock is applied to the counting terminal CP. By,
Carry terminal when 10msec has passed after reset
Generate carry output from CR.

In other words, the fixed value given to the data terminal D is selected so that the cycle counter 71 overflows every 10 msec, and the fixed value is provided in the LSI circuit 2. It comes from means.

The carry output of the cycle counter 71 is applied to the load terminal L of the cycle counter 71 to reset the count value of the cycle counter 71 to the fixed value, and is also supplied to the input terminal of the OR circuit 73 to be supplied to the AND circuit. 74
It is applied to one input terminal of the AND circuit 74, and is applied to the counting terminal CP of the address counter 72 when a clock following the other input terminal of the AND circuit 74 arrives.

In the address counter 72, the value "3FF" given to the data terminal D is set as an initial value by the reset signal generated at the same time as the mounting of the memory card 1 described above, and thereafter, the counting circuit CP of the AND circuit 74 is set. Every time an output is applied, the count value is decreased from "3FF" by "1" in synchronization with the clock.

That is, the count value of the address counter 72 is kept constant for 10 msec corresponding to one write cycle of the actual EEPROM shown in FIG.
Each time msec elapses, the value decreases from "3FF" by "1", and this count value is supplied to the address terminal AD of the EEPROM 16 as a write address of the EEPROM 16. The initial value "3FF" is the maximum value of the address of the memory card 1 as shown in FIG.

When the write enable signal WE of the EEPROM 16 is supplied with the write enable signal shown in FIG. 5C from the write enable signal generation circuit 19, the data input terminal D
Data such as a program (FIG. 5 (b)) from the memory card 1 supplied via the data generation circuit 3 to the
It is written to the write address of the EEPROM 16.

In this way, “1” is set every 10 msec from the address counter 72.
Since a new address is generated by subtracting, all the data such as the program on the memory card 1 is transferred to the address of the EEPROM 16 which is equal to the address on the memory card 1.

FIG. 7 shows the structure of the write enable signal generating circuit 19 for generating the write enable signal shown in FIG. 5 (c). The cycle counter of the EEPROM write address generating circuit 7 is shown in FIG.
"0" is loaded by the carry generated every 10 msec from 71 and the addition counter 19 ₁ overflowing by the clock generated during 10 msec and the count value from this counter 19 ₁ is applied to one terminal A. Two comparators 19 ₂ and 19 ₃ , an AND circuit 19 ₄ and an inverter 19 ₅
It is composed by.

Figure 5 to the other terminal B of the comparator 19 ₂ time T of the (c)
_Since the numerical value T ₁ corresponding to ₁ and the numerical value T ₂ corresponding to the time T ₂ in FIG. 5C are given to the other terminal B of the comparator 19 ₃ respectively, A ≧ B Comparator 19 for comparing
From ₂ "1" is output at time T ₁ after the Figure 5 (c),
Further, since "1" is output from the comparator 19 _{3 for} comparing A≤B before time T _{2 in} FIG. 5 (c), the outputs from these comparators 19 ₂ and 19 ₃ are AND circuits. By taking the logical product at 19 ₄ , the output of “1” is obtained during the period from T ₁ to T _{2 in} FIG. ₅ , and the output of “1” is inverted by the inverter 19 ₅ according to the enable characteristic of EEPROM 16. After that, the write enable signal is supplied to the write enable terminal of the EEPROM 16.

In this conventional example, one write cycle of the EEPROM 16 takes about 10 msec, which is equal to the write cycle of the actual EEPROM. This time is necessary for the transfer test, but the operation test described above is performed. , The operating clock cycle of the system is on the order of 100 nsec,
Assuming that the number of clocks required to write to the EEPROM16 model is 5 clocks, the time required for writing is
Since it is 500 nsec, this writing time of 10 msec is almost 20,000 times that time, and most of this 10 msec is an unnecessary waiting time.

The conventional example shown in FIG. 8 is designed so that the simulation can be performed by shortening the time corresponding to the time required for the actual storage processing in the EEPROM. In the conventional example shown in FIG. The carry of 71 is configured to be output every 10 msec, whereas the carry of the cycle counter 71 is configured to be output at a shorter time interval.

As is apparent from comparison with the conventional example of FIG. 8, the conventional example of FIG. 8 has a load terminal L of the cycle counter 71.
In addition, the load signal can be applied together with the carry signal via the OR circuit 75, and the external setting value externally set to the data terminal D is applied. The load signal applied to the load terminal L is used when writing to the EEPROM 16 is started.

Here, this external set value is the same as the fixed value supplied to the data terminal D of the cycle counter 71 in FIG. 6 in order to perform the above-mentioned transfer test.
From 10 to every 10 msec, and the initial value used to shorten the writing time to the EEPROM 16 for the above-mentioned operation test must be usable.

If the external setting value is large, the cycle counter 71 shortens the time until the carry is generated, and the time until the writing to the EEPROM 16 is completed is also shortened.

However, in the conventional example shown in FIG. 8, it is necessary to perform the above transfer test, so that 10 msec from the cycle counter 71
Each time, an external setting value is required to generate a carry, but if it is possible to instruct to start writing to the EEPROM 16 in one cycle of the simulation clock, the cycle of this clock will be 10 nsec and the transfer test will be 10 msec. There is a difference of 100,000 times, and since 17 bits are required to transmit this "100,000", there are 17 external setting value input terminals and one input terminal that supplies the load signal. A total of 18 input terminals will be installed in the system under test.

Then, when actually manufacturing an LSI, it is necessary to have exactly the same circuit configuration as the simulated circuit model in order to guarantee the reliability of the operation of the LSI. An additional pin as an input terminal must be added, which greatly increases the price of the LSI.

[Problems to be Solved by the Invention]

The present invention relates to an LSI test method for performing a transfer test for transferring data from a memory card to an EEPROM 16 of a system model and an operation test for confirming an operation using a program written in the EEPROM 16, wherein The purpose is to reduce the time required for this operation test without increasing the number of pins of the LSI manufactured according to the system model.

[Means for Solving the Problems]

By the microprogram transferred from the EEPROM model 16 which stores and holds the microprogram read from the memory card 1 storing the microprogram for operating the system including the LSI created according to the circuit model, to the control memory model 18 , At least above
EEPROM having cycle counter 71 and address counter 72 for generating write address of EEPROM model 16
In a test method of a large scale integrated circuit for operating the circuit model of the LSI including the write address generation circuit 7 and testing the circuit model of the LSI, a write cycle period is designated to a specific address of the memory card 1. In addition to storing the initial value data, the initial value data buffer 20 that stores this initial value data
It is provided in the circuit model of the LSI, and this initial value data is set as the initial value of the cycle counter 72 of the circuit model of the LSI.

[Action]

For the system under test including the LSI circuit model to which the EEPROM model is attached, the actual EEPROM when performing the transfer test.
The time required for writing in is also required for the simulation, but the time required for the actual EEPROM to perform the write processing internally is not required for the simulation when performing the operation test.

Therefore, when performing an operation test, in order to shorten the time corresponding to the time required for the actual EEPROM to perform the write processing internally, the write cycle when transferring the microprogram from the memory card 1 to the EEPROM model Try to shorten.

Therefore, as shown in the principle block diagram of FIG. 1, initial value data designating a write cycle period is stored in a specific address of the memory card, and the initial value data read from this address is stored in the data generating circuit 3. Stored in the initial value data buffer 20 via the EEPRO of the LSI circuit model.
It is supplied to the cycle counter 71 of the M write address generation circuit 7 as an initial value.

By increasing the initial value during the operation test, the time until the cycle counter 71 overflows is shortened according to the initial value, and therefore,
The time required for writing to the EEPROM 16 is also shortened.

Further, in the transfer test, by reducing the initial value so that the cycle counter 71 overflows every 10 msec, for example, the same write cycle as writing to the actual EEPROM can be performed.

Further, according to the present invention, it is not necessary to increase the number of external connection terminals of the LSI just by adding the initial value data buffer 20 and some wirings to the LSI circuit model. Therefore, the price of the LSI manufactured according to this model can be reduced. Never raise.

〔Example〕

FIG. 2 shows an embodiment of the system under test constructed in accordance with the present invention at the time of operation test. In the conventional example shown in FIG. 8, an initial value data buffer 20 and an OR circuit according to the present invention are shown.
24 have the added configuration.

In this initial value data buffer 20, when the same address is applied to the address terminal AD of the EEPROM 16, one input terminal A
Is applied to the other input terminal B, and the address (“3FF” in this embodiment) storing the initial value on the memory card is applied to the other input terminal B, and this comparator 22 matches the above two addresses. The output of the AND circuit 23 in which the coincidence output when it is detected is supplied to one input terminal and the clock is supplied to the other input terminal, and the data generation circuit 3 generating the data read from the memory card. And a data buffer 21 for taking in the output signal from the AND circuit 23.

The OR circuit 24 has one input terminal supplied with the output of the AND circuit 23, and the other input terminal supplied with a carry output when the cycle counter 71 overflows.

The operation of the write address generating circuit for the EEPROM 16 including the cycle counter 71, the OR circuit 73, the AND circuit 74, and the address counter 72 has been described above with reference to FIGS. 6 and 8, and will be briefly described.

When the reset signal is applied to the reset terminal L, the cycle counter 71 sets the count value to the value applied to the data terminal D, increases the count value for each clock applied to the clock terminal CP, and eventually counts. When the numerical value overflows, a carry signal is output from the carry terminal CR. The interval at which this carry is output is equal to the time until the count value of the cycle counter 71 sequentially increases by counting clocks from the initial value and overflows.

The address counter 72 sets the count value to the address (“3FF” in this embodiment) that stores the initial value on the memory card supplied to the data terminal D when the load signal is applied to the load terminal L. Then, the carry signal from the cycle counter 71 is subtracted from the count value by using a signal obtained by synchronizing the carry signal with the clock in the AND circuit 74, and the count value is supplied to the EEPROM 16 as a write address.

Therefore, the address output from the address counter 72 has a constant value during the period when the carry from the cycle counter 71 arrives, and decreases by "1" at each arrival of the carry. From the memory card,
Data is sequentially read from an address equal to this address and output from the data generation circuit 3.

When the address storing the initial value in the memory card set to "3FF" in this embodiment is output from the address counter 72, the comparator 22 sends the output to the AND circuit 23, and the AND circuit 23 outputs the clock. Synchronized coincidence output is sent.

This coincidence output is supplied to the data buffer 21 as a write clock on the one hand, so that the initial value from "3FF" of the memory card is stored in this data buffer 21, and on the other hand, the cycle counter is passed via the OR circuit 24. It is sent to the load terminal L of 71.

At this time, since the initial value from the memory card stored in the data buffer 21 is given to the data terminal D of the cycle counter 71, the count value of the cycle counter 71 is set to this initial value.

As described above, the carry interval output from the cycle counter 71 is determined by the number of times the cycle counter 71 overflows from the initial value and the clock interval. Therefore, the larger the initial value, the shorter the time interval.
The duration of one address output from the address counter 72 is also shortened.

By setting this initial value appropriately, the address duration, that is, the write cycle to this EEPROM16, can be set to the desired time, so the simulation can be performed regardless of the actual write processing time in the EEPROM. Can be executed.

Moreover, as is clear from a comparison between FIG. 2 showing this embodiment and FIG. 6 showing the conventional example, since the number of connecting terminals between the LSI model and peripheral elements has not increased, this LSI model Therefore, since it is not necessary to provide an extra connection terminal in the manufactured LSI, the special effect that the price of the LSI does not become high can be obtained.

〔The invention's effect〕

According to the present invention, the write cycle to the EEPROM model can be changed to the actual EE by simply adding a simple circuit configuration to the LSI model.
Not only can the simulation be executed at high speed by setting it independently of the write processing time inside the PROM, but there is no need to add extra pins to the LSI manufactured according to this LSI model. The special effect is that the price does not become expensive.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is an explanatory diagram of a memory card assumed in a conventional example and an example, and FIG. Shows a system under test targeted by the present invention, FIG. 5 shows a write cycle of an actual EEPROM, FIG. 6 shows a conventional example, and FIG. 7 shows an example of a write enable signal generation circuit. FIG. 8 is a diagram showing another conventional example.

Claims (1)

[Claims] 1. An electrically erasable programmer for storing and holding a microprogram read from a memory card (1) storing a microprogram for operating a system including a large scale integrated circuit created according to a circuit model. For generating at least the write address of the electrically erasable programmable programmable read-only memory model (16) by the microprogram transferred from the model of the programmable read-only memory (16) to the control memory model (18). This large scale integrated circuit model is operated by including the write address generation circuit (7) of the electrically erasable programmable programmable read only memory having a cycle counter (71) and an address counter (72). In a large-scale integrated circuit test method for testing an integrated circuit model, the above memory card (1) Initial value data buffer (20) that stores the initial value data that specifies the write cycle period at a specific address of
Is provided in the large-scale integrated circuit model, and the initial value data is used as the cycle counter (72) of the large-scale integrated circuit model.
A test method for large-scale integrated circuits characterized by being set as an initial value of.