JPH0774818B2 - Timing signal generation circuit for tester - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generation circuit for a tester, and more particularly, to a plurality of IC test pins for generating waveform patterns for IC test, for example. The present invention relates to a timing signal generation circuit in a pattern generation system of a tester that generates a signal.

[Prior Art] In an IC inspection system, a test waveform pattern of a plurality of bits required for performing IC performance and function tests is automatically generated according to a test pattern program or the like.
Therefore, in the conventional pattern generation system, from each of the pattern data obtained from the pattern generator and the phase clock signal having a large number of phases generated by the timing signal generation circuit, it is necessary for each pin of the IC. Each of them is selected and combined to generate a predetermined waveform pattern. The generated test pattern is sent to the drive circuit, and its output is level-converted to a predetermined waveform.
The method of supplying to the IC pin is adopted.

The phase clock signal in this case is usually used to determine the rising and falling timings of the test pattern, and the timing signal generating circuit uses a number of clock signals of different phases (phases) at a cycle corresponding to the test cycle. Clock signal) to each phase clock output terminal.

Generally, such a phase clock signal is generated by counting the reference clock signal by the preset timing data, but the phase clock signal is generated by adding a minute time within the range of the resolution of the reference clock or less. In the case of generating the clock signal and adjusting the timing, by adding the clock signal obtained by counting the reference clock signal to the delay circuit of the delay element matrix and selecting the output of the necessary delay time, You are getting the desired phase clock signal. Further, when the phase clock signal is synchronized with the high-frequency reference clock signal and is output with the resolution, the clock signal delayed to a predetermined phase is output in synchronization with the reference clock signal.

[Problems to be Solved] In the above-described method, the timing accuracy is determined by the accuracy of each delay element of the delay element group, and therefore, there is a drawback that it is necessary to select a highly accurate delay element. is there. In addition, the delay element is affected by the use environment such as temperature and humidity, and a delay error occurs. If the selected delay time is different, the error is also different, which causes the accuracy of the timing generator to deteriorate. ing.

An object of the present invention is to solve the problems of the prior art as described above, and to generate a timing clock signal at an accurate timing by setting a highly accurate delay time without being affected by the use environment. It is an object of the present invention to provide a timing signal generation circuit for a tester that can perform the test.

[Means for Solving the Problems] The features of the timing signal generating circuit of the tester of the present invention for achieving such an object are that a reference clock signal generating circuit and a reference clock signal from the reference clock signal generating circuit are provided. A pulse generation circuit that generates a pulse signal of a clock signal obtained by frequency division through a frequency division circuit or receives a reference clock signal and generates a pulse signal of a predetermined period, and a period from this pulse generation circuit. A first delay circuit for receiving a specific pulse signal and setting a delay time shorter than the period of the pulse signal, and delaying the received pulse signal by a time corresponding to the set value given from the outside, In the usage environment of the selected tester, a conversion procedure for converting the above set value into data on the delay time for performing the time correction corresponding to the usage environment. A second delay circuit having a stage and receiving the set value and delaying the pulse signal obtained from the first delay circuit in accordance with the data by a delay time shorter than the delay time of the first delay circuit. It is provided to obtain the timing lock signal from the second delay circuit.

[Operation] As described above, the first and second delay circuits are provided, and the reference clock signal is adjusted by the first delay circuit to adjust the timing by adding a minute time within the range of the resolution of the reference clock signal or less. The clock signal obtained by counting is delayed corresponding to the setting data, and the delayed clock signal is further added to the second delay circuit, and the first delay time is set according to the delay time set by the second delay circuit according to the usage environment. By delaying the delay circuit so as to correct it within the range of the delay time of the delay circuit, the correction according to the usage environment of the tester can be automatically set at the same time corresponding to the set value of the second delay circuit. Since the delay correction in this case is to generate the correction data from the installation value, different correction data can be generated if the setting values are different. The configuration of the timing signal generating circuit has three stages as described above, and the delay adjustment has two stages, and the delay amount of the final delay circuit is determined according to the allocation of each timing time. The delay time of the second delay circuit cannot be determined simply by increasing or decreasing according to the temperature change. However, if the conversion means is provided as described above, for example, delay data in which the delay amount sequentially decreases in the order of larger set values, conversely delay data in which the delay amount sequentially increases in the order of large set values, and Regardless of the change in the value, the set value and the delay amount can be arbitrarily associated with each other to individually generate data according to the use environment.

That is, by selectively setting the contents of the conversion means provided in the second delay circuit, the delay amount of the second delay circuit is freely combined with the delay amount setting value of the first delay circuit and individually set. And the delay time of the second delay circuit can be determined according to the pulse period of the pulse generating circuit of the preceding stage and the delay time set in the first delay circuit.

Therefore, if the contents of the conversion means are rewritten according to the usage environment of the tester, the overall timing generation time set in accordance with the delay amount setting value of the first delay circuit corresponds to the usage environment. It becomes possible to make it. An accurate timing clock signal can be generated without being affected by the usage environment of the tester.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the timing signal generating circuit of the tester of the present invention.

In FIG. 1, reference numeral 1 is a timing signal generating circuit, which is composed of a count clock generating section 2, a timing clock generating section 3, and a phase correcting section 4.

The count clock generating section 2 is composed of a reference clock signal generating circuit 21 and a frequency dividing circuit 22 which divides the frequency of the reference clock signal output from this circuit.
Receives the reference clock signal from the reference clock signal generation circuit 21 and reduces it to a timing count clock signal having an integral multiple period (frequency of 1 / integer) so that it becomes the period of the reference clock signal for timing count. To do. The clock signal (counter clock signal 22a) reduced by the frequency dividing circuit 22 is then sent to the timing clock generator 3.

The timing clock generation unit 3 includes a timing count circuit 31a that counts a timing count clock signal to generate a rate signal, and timing count circuits 31b, 31c that count the timing count clock signal to generate a phase clock signal. .., and delay circuit matrices 32a, 32b, 32c, provided respectively corresponding to these timing count circuits 31a, 31b, 31c ,.
..And each timing counting circuit 31a, 31b, 31c, ..
.. and data memories 33a, 33b, 33c, ... Provided corresponding to the delay circuit matrices 32a, 32b, 32c, ... And storing timing data set therein.

Here, each timing count circuit 31a, 31b, 31c ...
Respectively receive the start signal from the outside and count the timing count clock signal having the reference cycle for counting the timing, which is sent from the frequency dividing circuit 22, and sets the cycle setting values Na ₁ and Nb for the pulse generation cycle. ₁ , Nc
_1, respectively.. Is be one which generates a pulse signal having a period corresponding to each receive corresponding, for example, and an internal register and preset counter or the like. Then, when the respective cycle set values are set in the respective registers, the set values are set in the preset counter, which is counted by the timing count clock signal from the frequency dividing circuit 22, and the counting is completed. A pulse signal is generated for each period, and the value of the register is reset to generate a periodic pulse signal corresponding to each cycle set value Na ₁ , Nb ₁ , Nc ₁ , ... Are sequentially generated as signals, and are sequentially generated as phase clock signals in the timing count circuits 31b, 31c .... The data memories 33a, 33b, 33c,
Cycle setting values Na ₁ , Nb ₁ , N set to ...
c ₁ , ... Is RT in real time from the pattern generator 7.
It is given as a TC signal (real-time timing control signal). In addition, the signal 2 returned from the data memory 33a
2b is a counter preset signal.

The periodic pulse signal obtained from each timing count circuit is then output to the delay circuit matrix 32a, 32b, 32c, ...
Are input respectively. Each delay circuit matrix 32a, 32
b, 33c, ... are circuits for adjusting the generation timing of the rate pulse signal or the phase clock signal by adding time equal to or less than the resolution of the reference clock.
~ 1 ns for pulse signals generated at a period of several hundred ns
The delay time can be selected within the range of 1 ns to 10 ns, and the time can be adjusted.

The selection of the delay time of each delay circuit matrix is performed by selecting the timing setting values Na ₂ , Nb ₂ , for the delay time given to the data memories 33a, 33b, 33c, ...
It is performed by the value of Nc ₂ , ... Therefore, each delay circuit matrix respectively receives the above-mentioned timing setting values and gives a corresponding delay time to the periodic pulse signal received from the timing count circuit.

The rate pulse signals and the phase clock signals delayed to appropriate values by the delay circuit matrices in this way are then fed to the delay correction circuits 41a, 41b, 41c ,.
・ Sent to Note that the timing setting values Na ₂ , Nb ₂ ,
Nc ₂ , ... Is the pattern generator 7 at the same time as the cycle setting value.
Is set to each data memory in real time.

The phase correction unit 4 includes delay correction circuits 41a, 41b, 41c, ...
Compensation data memory 42a, 42b, 42c, ... provided corresponding to these delay compensation circuits.
Each delay correction circuit receives the correction data obtained from 42a, 42b, 42c, ... And selectively delays the pulse signal received from the delay circuit matrix in the range of 0.1ns to 1ns in 0.2ns units, for example. And output.

Here, each correction data memory 42a, 42b, 42c, ...
From the memory 6 side of the CPU 5 as the controller of the tester
The conversion table selected in advance corresponding to the usage environment is set by the CPU 5 before starting the test. This conversion table is a conversion table for obtaining the correction value data corresponding to the timing setting value from the timing setting value, and a certain timing setting value selected from the range of the delay time of 1 ns to 10 ns in the unit of 1 ns is Correspondingly, when given, it is 0.1 in the above 0.2 ns unit.
The correction value data for selecting a certain delay time selected in the range of ns to 1 ns is generated. The conversion relationship in this case is determined by the use conditions such as the temperature and humidity of the tester.

Therefore, the correction data memories 42a, 42b, 42c, ... Include timing setting values Na ₂ and N ₂ that add delay time given as RTTC signals in real time together with the cycle setting value, respectively.
Receives b ₂ , Nc ₂ , ... From the data memories 33a, 33b, 33c ,.
The delay correction circuit 42 converts the data to the appropriate delay time correction value data according to the usage environment at that time selected within the range of 1 ns.
to a, 42b, 42c, ... As a result, in accordance with the timing setting values Na ₂ , Nb ₂ , Nc ₂ , ... For the given delay time, the correction data is stored in the correction data memory 42a, in real time according to the data memory 33a, 33b, 33c ,.
42b, 42c, ... to delay correction circuits 42a, 42b, 42c ,.
, The delay pulse correction circuits 42a, 42b, 42c, ... Are provided with the rate pulse signals and the respective phase clock signals that are finely time-corrected according to the use environment, and the phase correction unit 4 is provided with accurate timing. Outputs these timing clock signals.

In the above case, the timing clock signal such as the rate pulse signal or each phase clock signal is generated by the timing count circuit and the total delay time of the delay circuit matrix and the delay correction circuit. In order to have a form in which the timing time is added, the immediately preceding circuit, that is, the delay circuit matrix for the delay correction circuit, the timing count circuit for the delay circuit matrix, and these circuits,
The generation timing of the generated pulse signal is set to be earlier than the delay time added in terms of time in order to match the time obtained by subtracting the delay time added in the subsequent stage from the total generation timing.

By adopting the above configuration, it becomes possible to select the time correction data according to the usage environment such as temperature and humidity with the timing setting value, and if this is set as the content of the correction data memory, if that content is changed, the The conversion data with the delay time according to the usage environment can be set in the correction data memory each time. Therefore, the timing clock signals such as the rate pulse signal and each phase clock signal can be generated at accurate timing according to the environment at that time.

The contents of the conversion data set in the correction data memory from the memory on the CPU side can be obtained experimentally by obtaining it for each operating environment, but various timing clocks can be set according to the environment in which the tester is placed. It is possible to measure the delay time of the signal and determine the converted data value together with the setting value on the data memory side so that the delay time is correct. Also, if the usage environment is constant,
Since the content of the correction data memory can be a fixed value, a memory conversion table such as a ROM may be provided. Furthermore, these conversions are not limited to conversions by a table.

In the embodiment, the reference clock signal is divided by the divider circuit to generate the timing count clock signal.
It goes without saying that the reference clock signal may be directly counted by the timing count circuit as the timing count clock signal without being divided by the frequency divider circuit. Therefore, the frequency dividing circuit is not always necessary.

[Effects of the Invention] As can be explained from the above description, in the present invention, the first and second delay circuits are provided, and a minute time is added within the range of the resolution of the reference clock signal or less to adjust the timing. To delay the clock signal obtained by counting the reference clock signal by the first delay circuit in correspondence with the setting data, the delayed clock signal is further added to the second delay circuit and the second delay circuit is added. According to the delay time set according to the usage environment, by delaying the delay time so as to correct it in the range of the delay time of the first delay circuit or less, the correction according to the usage environment of the tester is performed by the second delay circuit. It can be automatically set at the same time according to the set value. Since the delay correction in this case is to generate the correction data from the installation value, different correction data can be generated if the setting values are different. The configuration of the timing signal generating circuit has three stages as described above, and the delay adjustment is 2
Since the delay amount of the final delay circuit is determined according to the allocation of each timing time, the delay time of the second delay circuit cannot be simply increased or decreased depending on the temperature change. However, if the conversion means is provided as described above, the amount of delay of the second delay circuit is set to that of the first delay circuit by selectively setting the contents of the conversion means provided in the second delay circuit. The delay time can be set individually and freely in combination with the delay amount setting value, and the delay time of the second delay circuit is determined according to the pulse period of the pulse generation circuit of the previous stage and the delay time set in the first delay circuit. it can.

Therefore, if the contents of the conversion means are rewritten according to the usage environment of the tester, the overall timing generation time set in accordance with the delay amount setting value of the first delay circuit corresponds to the usage environment. It becomes possible to make it.

As a result, without being affected by the environment in which the tester is used,
An accurate timing clock signal can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the timing signal generating circuit of the tester of the present invention. 1 ... Timing signal generation circuit, 2 ... Count clock generation unit, 3 ... Timing clock generation unit, 4 ... Phase correction unit, 5 ... CPU, 6 ... Memory, 21 ...
Reference clock signal generation circuit, 22 ... Dividing circuit, 31a, 31b,
31c …… Timing count circuit, 32a, 322,32c …… Delay circuit matrix, 33a, 33b, 33c …… Data memory, 41
a, 41b, 41c ... delay correction circuit, 42a, 42b, 42c ... correction data memory.

Claims (2)

[Claims] 1. A reference clock signal generating circuit and a reference clock signal generated by dividing the reference clock signal from the reference clock signal generating circuit through a frequency dividing circuit. A pulse generation circuit that receives a signal and generates a pulse signal with a predetermined period, and a setting given from the outside that receives the periodic pulse signal from the pulse generation circuit and sets a delay time shorter than the period of the pulse signal A first delay circuit for delaying the received pulse signal by a time corresponding to the set value according to a value, and a delay time for performing time correction corresponding to the use environment in the use environment of the selected tester Of the pulse data obtained from the first delay circuit according to the data by receiving the setting value. A second delay circuit for delaying a signal at a delay time shorter than the delay time of the first delay circuit, and a timing lock signal is obtained from the second delay circuit. . 2. A frequency dividing circuit is provided, which divides the reference clock signal to generate a timing clock signal, and the pulse generating circuit is externally supplied.
A set value for counting the timing clock signal up to the cycle set value according to a cycle set value for setting the cycle, the conversion means being a conversion table, and the second delay circuit converting the conversion table into the data. 2. The timing signal generating circuit for a tester according to claim 1, wherein the timing signal generating circuit is accessed according to the above to obtain the data.