JPH0774986B2 - Data bus connection system - Google Patents

Description

Detailed Description [Table of Contents] Outline Industrial Application Field of the Invention Conventional Technology Problems to be Solved by the Invention Means for Solving Problems Problems Working Example First Example (3rd Example) (FIG. 4, FIG. 4) Description of the second embodiment (FIGS. 5, 6) Effect of the invention [Outline] A plurality of types of data having different bit arrangement orders are input / output from the same data input / output terminal. Regarding a data processing system having a device, when connecting a device for inputting and outputting a plurality of types of data having different bit arrangements from the same input / output terminal, the load of software and the increase of hardware due to the connection of the device are increased. And a first device which is connected to a data bus and receives or outputs data from a plurality of predetermined terminals in a bit arrangement order different depending on the type of data. Device of 1 In the first bit arrangement order, data input or output is transferred to and from the first device via the data bus, and via the data bus to the second device. Data input or output in the second bit arrangement order in the first device is transferred to and from the first device, and in the second device to and from the second device. A data processing system comprising: a third device to which data input or output in the first bit arrangement order is transferred; and a data bit between the third device and the data bus. A connection unit is provided, and the data bit connection unit is controlled by a bus master having the right to use the data bus so that the bit arrangement order of the data input or output in the third device is changed. one So that, the data in the device of the third, configured to perform conversion of the bit arrangement order with the data on the data bus.

[Industrial application field]

The present invention relates to a data processing system, and more particularly to a data processing system having a device for inputting and outputting a plurality of types of data having different bit arrangement orders from the same data input / output terminal.

In recent years, semiconductor technology has advanced, and various types of microprocessors and their peripheral LSIs have appeared on the market, and devices are often configured using these. However, although these LSIs are easily interconnected within the same family, interconnects are not easy due to differences in data bit width, data bit order, etc. between different families. In particular, processor LSIs that use the same data bus from the same input / output terminal to input and output multiple types of data with different bit arrangement orders.
In a system that connects such LSIs, it is necessary to adjust the bit arrangement order of data exchanged with the LSIs by software processing, or to provide a special interface circuit for each such LSI. It was being done. Such a conventional system configuration causes complication of software or increase in hardware, and it has been desired to realize a system having a simpler configuration.

[Conventional technology]

FIG. 8 shows a configuration in which LSIs for inputting and outputting a plurality of types of data having different bit arrangement orders are connected from the same input / output terminal.
Image as the first example of the conventional data processing system
LSI that performs data compression / decompression, AM7971 manufactured by AMD
It is a figure which shows schematic structure of the image processing apparatus using (it is hereafter called CEP, Compression Expansion Processor). In this figure, 4 is a 16-bit data bus, 4a is the upper byte of the data bus, 4b is the lower byte, 10 is a 16-bit microprocessor unit (MPU) that controls the entire system, and 20 is the above. CEP, 21 are control signal lines by CEP, 3 is a 16-bit data memory, and 23 is an 8-bit bus transceiver (TRV).

The CEP20 inputs / outputs 8-bit width data, inputs 8-bit control information from the MPU10 via the upper byte 4a of the data bus 4 and sets it in the internal register. The data stored in No. 3 is read out using its own DMA function, compressed or expanded, and the processed data is written into the memory 3 again by the DMA function. Here, in the CEP 20, the input of the control information and the input / output of the processed data are performed through the same 8-bit terminal, but the arrangement order of both bits is opposite. The above control information is the above 16-bit MPU10
Similar to the above, the array is arranged from MSB to LSB as shown in FIG. 7 (2), but the processing data input / output in CEP20 is from LSB for each byte as shown in FIG. 7 (1). MSB
Are arranged in order.

In the configuration shown in FIG. 8, the 8-bit data input / output terminal of the CEP20 is connected to each bit of the upper byte 4a of the data bus 4 with the bit arrangement reversed, and further connected to the upper byte 4a of the data bus 4 and the lower byte. A bus that is connected to or cut off from the byte 4b by the control signal line 21 from the CEP 20.
An 8-bit path is connected through the transceiver 23. That is, with this configuration, when the CEP 20 accesses the upper byte of the memory 3, it performs it through the upper byte 4a of the data bus 4, and when accessing the lower byte of the memory 3, it makes the transceiver 23 conductive so that the CEP 20 outputs from the CEP 20. The upper byte 4a of the data bus 4 is connected to the lower byte 4b of the data bus 4.

However, in the configuration of FIG. 8, the bit arrangement order at the time of data input / output in the MPU10 and the bit arrangement order at the time of control information input in the CEP20 are the same, but as described above, the upper bits 4a and CEP20 of the data bus 4 are the same. When the MPU10 inputs the above control information to the CEP20, it is processed by software on the MPU10 side and processed by the CEP20.
The bit arrangement order of the control information sent to is output in reverse.

FIG. 9 is a diagram showing a second example of the conventional configuration of the image processing apparatus using the above CEP as in FIG. The hardware configuration of this figure is different from that of FIG.
There is only a difference between the CEP 20 and the upper byte 4a of the data bus 4. In Figure 9, CEP20 and data
Between the high-order byte 4a of the bus 4, an 8-bit path 1 which is connected as it is without inverting the bit arrangement order and an 8-bit path 2 which is connected by inverting the bit arrangement order are also provided. The multiplexer 22 provided between these paths and the CEP 20 selects one of the paths and connects it to the data input / output terminal of the CEP 20.
This selection is made by the control signal line 11 from the MPU10.
Controls the path 1 only when the control information is input to the internal register of the CEP 20.

[Problems to be solved by the invention]

Among the above-mentioned conventional data processing systems, in the configuration shown in FIG. 8, regarding a certain kind of data among a plurality of kinds of data which are input / output from the same input / output terminal and have different bit arrangement orders. Must be processed by software in the processor of the data transfer partner to adjust the bit arrangement order inside the processor of the partner, which poses a problem that the software load is heavy.

Further, in the configuration shown in FIG. 9, when a plurality of CEPs are connected to the data bus, there is a problem that the number of circuits for bus connection increases in proportion to the number of CEPs.

The present invention has been made in view of the above problems, and when connecting a device that inputs / outputs a plurality of types of data having different bit arrangements from the same input / output terminal, the load of software increases due to the connection of the device. It is an object of the present invention to provide a data processing system that minimizes an increase in hardware.

[Means for solving problems]

FIG. 1 shows the outline of the configuration at the stage before reaching the present invention. In the figure, 1 is a first device, 2 is a second device, 3 is a third device, 4 is a data bus, and 5 is a data bit connection.

The first device 1 is connected to the data bus 4 and
In the device 1, the data is input or output from a predetermined plurality of terminals in a bit arrangement order different depending on the type of data.

In the second device 2, the data input or output in the first bit arrangement order in the first device 1 is transferred to or from the first device 1 via the data bus 4. It

In the third device 3, the data input or output in the second bit arrangement order in the first device 1 is transferred to and from the first device 1 via the data bus 4. Further, the data input or output in the first bit arrangement order in the second device 2 is transferred to and from the second device 2.

In the configuration of FIG. 1, a data bit connection 5 is provided between the third device 3 and the data bus 4, and the data bit connection 5 uses the data bus 4. The data in the third device 3 and the data in the third device 3 are controlled so that the bit arrangement order of the data input or output in the third device 3 becomes constant under the control of the bus master having the right. Conversion of the bit arrangement order with the data on the bus 4 is performed.

FIG. 2 is a diagram showing a schematic configuration of the present invention. In this figure, the roles of the first and second devices 1 and 2 are the same as those in the above-mentioned configuration of FIG. 1, but in the configuration of FIG. The device 3 is limited to a writable and readable memory 30 and the total bit width of the data transferred with the second device 2 in the third device 3 is such that N is a natural number It is N times the bit width of the data input or output in the device 1. The memory 30 is divided into N sections 30a, 30b having equal bit widths, and the data bus 4 corresponds to each section 30a, 30b of the memory 30. It is divided into sections 4a and 4b having the same bit width as the sections 30a and 30b. Further, the first device 1
The predetermined plurality of terminals of the data bus 4 is the section 4
It is connected to any one bit of a and 4b.

Based on the above premise, in the present invention, a data bit connecting portion 'is provided between the memory 30 and the data bus 4, and the data bit connecting portion 5'is connected to the data bus 4'. When the first device 1 accesses one section of the memory 30 under the control of the bus master having the usage right, the data bus 4 to which the plurality of terminals of the first device 1 are connected. The bits of each section of the memory 30 are rearranged so that the conversion between the first bit arrangement order and the second bit arrangement order is performed, and then each bit of the one section of the memory 30. And when the second device 2 accesses the memory 30,
Each bit of each section of the memory 30 is connected to each bit of each section of the corresponding data bus 4 in the same bit arrangement order.

According to the present invention, more specifically, L is a natural number,
In a data bus connection system 5'connecting between a data bus 4 consisting of upper and lower divisions each consisting of 4L bits and a memory 30 consisting of upper and lower divisions 30a and 30b each consisting of 4L bits, The data bus connection system 5 ', according to a first control signal from the outside, divides the upper and lower sections of the data bus 4 into the upper and lower sections 30a, 30b of the memory 30, respectively.
Alternatively, the upper and lower sides are interchanged and connected to the lower and upper sections 30a and 30b of the memory 30, respectively, and further, in accordance with a second control signal from the outside, the data.
The upper and lower divisions of the bus 4 are connected to the memory 30 with the bit order in each division being forward or reverse, and the data bus connection system 5 ′ is the upper or lower division of the data bus 4. 4a and 4b and first and second logic circuits 52 and 53 between the upper and lower two sections 31a and 31b of the memory 30, and the memory 3
Third and fourth logic circuits 54, 55 between the output terminals of the upper and lower two divisions 31a, 31b of 0 and the upper and lower divisions 4a, 4b of the data bus 4, The first, second, third and fourth logic circuits 52, 53, 54 and 55 have the same configuration, and the first, second, third and fourth logic circuits 52, 53, 54 , 55 has an input terminal of 4L + 2 bits and an output terminal of 4L bits, respectively.
Input data from 4L bits, input first and second control signals from the remaining 2 bits of the input terminal, and input 4L of the input terminal according to the first control signal.
The upper and lower 2L bits of each bit are
The 4L-bit output terminal is output as the upper and lower 2L bits respectively, or the upper and lower sides are interchanged to output as the lower and upper 2L bits of the 4L-bit output terminal, respectively. In accordance with a control signal of 2, the upper and lower 2L bits of the 4L bits of the input terminal for inputting the data are output in the normal or reverse order of the respective 2L bits, and the data of the data bus 4 is output. The lower L bits D0 to D1 of the lower section 4b are to the lower L bits I0 to I1 of the input terminal of the first logic circuit 52, and the next 2L bits D2 to D5 of the lower section 4b of the data bus are the above mentioned. To the lower 2L bits I0 to I3 of the input terminal of the second logic circuit 53, and
The upper L bits D6 to D7 of the lower section 4b of the data bus are connected to the next L bits I2 to I3 of the input terminal of the first logic circuit 52 in the order from the lower to the upper, and The lower L bits D8 to D9 of the upper section 4a are transferred to the next L bits I4 to I5 in order from the lower order of the input terminals of the first logic circuit 52 to the higher order,
The next 2L bits D10-D13 of the upper section 4a of the data bus
Is the upper 2L bits I4 to I7 of the input terminal of the second logic circuit 53.
, The upper L bit D1 of the upper section 4a of the data bus
4 to D15 are upper L bits of the input terminal of the first logic circuit 52
I6 to I7 are connected to the first and second logic circuits 52 and 5
Each of the three output terminals is connected to the first and second logic circuits 52,
The upper and lower divisions 31a, 31 of the memory 30 corresponding to the connection relationship with each bit of the upper and lower divisions 4a, 4b of the data bus 4 as seen from each of the 53 input terminals.
Each of the output terminals of the upper and lower divisions 31a and 31b of the memory 30 and the input terminals of the third and fourth logic circuits 54 and 55 are connected to the respective input terminals of the memory b. The data bus 4 is connected in correspondence with each bit of the upper and lower divisions 4a and 4b and the input terminals of the first and second logic circuits 52 and 53, and is connected to the third and fourth portions. Of the output terminals of the logic circuits 54 and 55 and the bits of the upper and lower divisions 4a and 4b of the data bus 4 are connected to the output terminals of the first and second logic circuits 52 and 53, respectively. The memory 30 is connected in a manner corresponding to the connection relationship with the input terminals of the upper and lower sections 4a and 4b.
And the second logic circuits 52, 53 are always set to output enable, and the third and fourth logic circuits 54,5
The data bus connection system 5 is controlled by the bus master so that the output is enabled only when data is read from the memory 30.

[Work]

In the configuration shown in FIG. 1, the first device 1 and the second device 1
Data is exchanged with the device in the first bit arrangement order.

When exchanging data between the second device 2 and the third device 3, the bus master, which recognizes this, controls the data bus 4 and the third device 3. The data bit connection unit 5 provided in the above section connects the data on the data bus 4 or the data input / output in the third device to the other party without change. Therefore, the data in the form of the first bit arrangement order is exchanged between the second device 2 and the third device 3.

When exchanging data between the first device 1 and the third device 3, the data exists in the form of the second bit arrangement order from the first device 1 to the data bus 4. However, if the data bit connection 5 provided between the third device 3 and the data bus 4 is a data transfer with the first device 1, the fact is recognized. Under the control of the bus master, the data of the second bit arrangement order on the data bus is converted into the data of the first bit arrangement order and output to the third device 3, and vice versa. The data output from the device 3 of No. 3 in the first bit arrangement order is converted into the second bit arrangement order and output to the data bus 4.

When the right to use the data bus 4 is acquired, the bus master that transfers data via the data bus is
Usually, it is often one of the devices for exchanging data, but in view of the configuration of the present invention, another device not shown in FIG. 1 may be used.

As described above, the configuration of FIG. 1 does not require special processing in software, and even when a large number of first devices 1 are connected, the hardware required for the connection is the third one. Data bit connection section 5 attached to the device 3
There is no need to add hardware.

In the schematic configuration of the present invention shown in FIG. 2, the difference from the situation of the above-described first configuration is that the bit width of the data input / output in the first device 1 is such that N is a natural number.
In the memory 30 corresponding to the third device 3, the second device 2
It is 1 / N of the bit width of the data when the data transfer between and is performed. Therefore, in the schematic configuration of the present invention, the memory 30 can be divided into N sections having a bit width equal to the bit width of the data in the first device, and can be accessed for each individual section. That is, writing or reading of data can be controlled. With respect to the data bus 4, this is not actually changed in the structure, but in order to show the correspondence relationship between the respective sections 30a, 30b of the memory 30 or the first device 1 described below. , Each section of the above memory 30
It is shown divided into sections 4a and 4b having the same bit width as a and 30b. Note that in FIG. 2, the memory 30 and the data bus 4 are divided into two sections because they are shown as N = 2.

Now, the first device 1 is connected to one section of the data bus 4, for example 4a. Thus, each section 30 of the memory 30
Access to a, 30b is made via the section 4a of the data bus 4.

In addition to the conversion operation of the bit arrangement order in the configuration of FIG. 1 described above, the data / bit connection unit 5'in the schematic configuration of the present invention transfers data from a device having a narrow bit width such as the first device 1 to the memory 30. At the time of access, the section 4a of the data bus 4 and the section of the designated memory 30 are connected so that only the section of the designated memory 30 can be accessed under the control of the bus master. Alternatively, it is said that all the sections 30a, 30b of the memory 30 are connected to the corresponding sections 4a, 4b of the data bus 4 for access from a device that transfers data with a width equal to the total bit width of the memory 30. As described above, depending on from which device the memory 30 is accessed, the control corresponding to the bit width is also performed. Thus, even when the bit width at the time of inputting / outputting data of the first device 1 is 1 / N of the bit width of the memory 30, the data bit connecting section 5 provided between the memory 30 and the data bus 4 is provided. By ', the bit arrangement order is matched and each section on the memory can be accessed.

〔Example〕

[Explanation of First Embodiment] (FIGS. 3 and 4) FIG. 3 is an overall configuration diagram of a first embodiment of the present invention. In this figure, 4 is a 16-bit data bus, 4a and 4b are the upper byte (8 bits) and lower byte (8 bits) of the data bus 4, 6a and 6b are 8-bit paths, and 7a,
7b is a path that reverses the order of 8-bit bit arrangement, 10 is
16-bit microprocessor unit (MPU), 1
1 is a control signal line by the MPU 10, 20 is the above-mentioned CEP, 21 is a control signal line by the CEP, 50 and 51 are multiplexers, 30 is a memory, and 30a and 30b are the upper and lower 8 bits of the memory 30, respectively. Area.

FIG. 3 corresponds to the second embodiment of the present invention shown in FIG. 2, and the inside of the broken line 5'is the data bit connecting portion 5'of FIG.
FIG. When each of the MPU 10 and the CEP 20 accesses the memory 30, the MPU 10 and the CEP 20 serve as a bus master and control the data bit connection unit 5 ′, specifically, the multiplexers 50 and 51 via the respective control signals 11 and 21. To do. On one side of the multiplexer 50, the bit arrangement order from the upper byte 4a of the data bus 4 is kept unchanged.
A bit path 6a and an 8-bit path 7a in which the bit arrangement order is reversed at the position of R in FIG. 3 from the upper byte 4a of the data bus 4 are connected, and the upper part of the memory 30 is connected. The 8-bit path on the other side of the multiplexer 50 connected to the 8-bit area 30a is connected to either of the two 8-bit paths 6a and 7a by the above control. Similarly, on one side of the multiplexer 51, an 8-bit path 7b in which the bit arrangement order is reversed at the position of R from the upper byte 4a of the data bus 4 and the lower byte 4b of the data bus 4 this time. Is connected to the 8-bit path 6b which does not change the bit arrangement order from the multiplexer 51 connected to the lower 8-bit area 30b of the memory 30.
The 8-bit path on the other side of
It is connected to either of these two paths 6b and 7b.

When the MPU 10 accesses the memory 30, the MPU 10 controls the multiplexers 50 and 51 so that they are connected to the path 6a side and the path 6b side, respectively, so that the MPU 10 can connect the data bus 4 to the path 6a and the path 6b. Memory through
A route for data transfer to each of the upper 8-bit area 30a and the lower 8-bit area 30b is established.

When any of the CEPs 20 that are complicatedly connected to the data bus 4 accesses the upper 8-bit area 30a of the memory 30, the CEP 20 controls the multiplexer 50 to set the bit arrangement order from the upper byte 4a of the data bus 4. A route for data transfer to the upper 8-bit area 30a of the memory 30 is established through the reverse path 7a.

When the CEP 20 accesses the lower 8-bit area 30b of the memory 30, it controls the multiplexer 51 to start the lower 8 bits of the memory 30 from the upper byte 4a of the data bus 4 through the path 7b which reverses the bit arrangement order. A route for data transfer to the bit area 30b is established.

FIG. 4 shows a more specific structural example of the memory 30 and the data / bit connecting section 5'of FIG. memory
The upper and lower 8-bit memory chips 30a and 30b for realizing 30 are 8-bit RAMs, respectively. The multiplexer 50 reverses the bus transceiver 50a for connecting or disconnecting the 8-bit path 6a and the upper 8-bit area 30a of the memory 30 and the bit arrangement order. 8-bit path 7a
And the upper 8-bit area 30a of the memory 30 are connected or not connected to each other by a bus transceiver 50b. The bus transceivers 50a and 50b may be those having a bidirectional tristate buffer for each bit, such as a commercially available 74245 type IC. DIR and in the figure are the control input terminals,
When is at "H" level, both directions are OFF (cut off), but when is at "L" level, the reading direction from the memory 30a depends on "L" or "H" of DIR, Alternatively, it is turned on (conducted) only in the writing direction to the memory 30a. The structure of the multiplexer 51 is made up of bus transceivers 51a and 51b which connect either the path 6b or the path 7b to the lower 8-bit area 30b of the memory 30, just like the structure of the multiplexer 50.
As described above, since the paths 6a and 6b are connected to the 16-bit microprocessor, MPU10, via the data bus 4, the MPU10 can access the memory 30 to the terminals that enable the bus transceivers 50a and 51a. When the CEP 20 accesses the upper 8-bit area 30a or the lower 8-bit area 30b of the memory 30, the MPU access signal that becomes "L" is applied to the terminals of the bus transceivers 50b and 51b, respectively. A CEP access signal of L "is applied. In addition, each bus transceiver 50a, 50
The 8-bit memory chips 30a, 30a,
The memory read signal to the output enable signal input terminal ▲ ▼ of 30b is connected in common, and when reading from either memory 8-bit area 30a or 30b, all bus
In the transceivers 50a, 50b, 51a, 51b, the reading direction from the memory is set. Each memory chip 30a,
For writing to 30b, the write signal from the MPU 10 or CEP 20 is applied to the write enable terminal ▲ ▼ of each memory chip 30a, 30b.

By the way, in the configuration of FIG. 3, when the MPU 10 is an 8-bit microprocessor unit and the memory 30 is also 8-bit, there is no path from the MPU 10 to the lower byte 4b of the data bus 4, Therefore the data
The lower byte 4b of the bus 4 is unnecessary, and the multiplexer 51 and the paths 6b and 7b are also unnecessary. At this time, the multiplexer 50 connects the path 6a or the path 7a to the memory 30a depending on whether the MPU 10 or the CEP 20 accesses the 8-bit memory 30a. This function is the fourth
In the figure, memory chip 30a, bus transceiver 5
It is obvious that this can be realized by the configuration including only 0a, 50b and paths 6a, 7a. The configuration at this time corresponds to the first aspect of the present invention.

[Explanation of the Second Embodiment] (FIGS. 5 and 6) FIG. 5 is a block diagram of the data / bit connection section 5'and the memory 30 in the second embodiment of the present invention. In the figure, 4a and 4b are the upper 8 bits and the lower 8 bits of the 16-bit data bus 4, 31a and 31b, respectively.
Is 8-bit RAM, 52,53,54,55 is 8-bit ×
It is a 1K ROM.

The 8-bit RAMs 31a and 31b each have an 8-bit data input terminal and a data output terminal, and a high-order byte access signal or a low-order byte access signal is applied to the chip enable terminal CE, respectively. As a result, writing or reading is performed.
Also, the signal applied to each WE pin is "H" or "L".
Data is written or data is read depending on whether or not.

The ROMs 52, 53, 54, 55 are provided for writing data to and reading data from the RAMs 31a, 31b, and one for each of the upper byte side and the lower byte side in each. These may be PROMs or logic circuits such as PALs as long as they output 8-bit data in response to input of 10-bit data. In the example of FIG. 5, I0 to I7 and
An 8-bit × 1K PROM (programmable ROM) that outputs 8-bit data of 0 to 7 in response to the input of 10-bit data of X and Y is used, and 4 of 52, 53, 54, 55 are used. Both are exactly the same. These proms
The relationship between the input data and the output data in is as shown in the table below, considering the X terminal and the Y terminal as control input terminals. In the table below, EN is the output enable pin, any
Can be 1 or 0, and Z represents a high impedance state.

The connections between the chips in FIG. 5 are as follows. First, the lower 2 bits D0 to D1 of the lower byte 4b of the data bus 4 are set to the lower 2 bits I0 to I1 of the input terminal of the writing upper byte ROM 52, and the next 4 bits D2 of the lower byte 4b of the data bus 4 are set. .About.D5 are in the lower 4 bits I0 to I3 of the input terminal of the write lower byte side ROM 53, and the upper 2 bits D6 to D7 of the lower byte 4b of the data bus 4 are the next 2 bits I2 of the input terminal of the ROM 52. ~ Connected to I3. Further, the lower 2 bits D8 to D9 of the upper byte 4a of the data bus 4 are
In the next two bits I4 to I5 of the input terminal of the ROM52, the next four bits D10 to D13 of the upper byte 4a of the data bus 4 are the ROM5.
To the next bit I4 to I7 of the input terminal of 3, and the data
The upper two bits D14 to D15 of the upper byte 4a of the bus 4 are the ROM5
It is connected to the upper 2 bits I6 to I7 of the 2nd input terminal.

Lower two bits I0 to I0 of the input terminal of the lower byte side RAM31b
The lower 2 bits 0 to 1 of the output terminal of the ROM 52 are included in I1.
However, the lower 4 bits 0 to 3 of the output terminal of the ROM 53 are in the next 4 bits I2 to I5 of the input terminal of the RAM 31b, and the upper 2 bits I6 to I7 of the input terminal of the RAM 31b are
The next 2 bits 2 to 3 of the output terminal of the ROM 52 are connected. Further, in the lower 2 bits I0 to I1 of the input terminal of the upper byte side RAM31a, the next 2 bits O4 to O5 of the output terminal of the ROM 52 are set, and in the lower 4 bits I2 to I5 of the input terminal of the RAM 31a.
Are the upper 4 bits 4 to 7 of the output terminal of the ROM 53.
, And the upper 2 bits I6 to I7 of the input terminal of the RAM 31a
The upper 2 bits 6 to 7 of the output terminal of the ROM 52 are connected to.

Next, regarding the connection on the output side of the RAMs 31a and 31b, the correspondence between the output terminals of the RAMs 31a and 31b and the input terminals of the read upper byte side ROM 54 and the read lower byte side ROM 55 corresponds to the data bus 4. Of the upper byte 4a and the lower byte 4b, and the input terminals of the ROMs 52 and 53 are connected so as to have the same correspondence.
And 55 output terminals and upper byte of data bus 4
4a and lower bits 4b correspond to the ROM5
The output terminals of 2 and 53 and the input terminals of the RAMs 31a and 31b are connected so as to have the same correspondence.

As can be seen from FIG. 5 and the above description, the RAM 31a, 3
On both the input side and the output side of 1b, the connection with each terminal of the data bus 4 as seen from the input terminals of the ROM52, 53 or the output terminals of the ROM54, 55, and the output terminals of the ROM52, 53,
Alternatively, the connection with the input terminals or output terminals of the RAMs 31a and 31b viewed from the input terminals of the ROMs 54 and 55 is symmetrical. That is, for example, the connection (correspondence) relationship between each bit of the upper and lower bytes 4a, 4b of the data bus 4 and each of the input terminals of the ROMs 52, 53 is as follows. Is equivalent to the connection (correspondence) relationship with each of the output terminals.

In the above configuration, the write ROMs 52 and 53 are always enabled, and the read ROMs 54 and 55 set the read (read) signal from the bus master (MPU10 or CEP20) to "0" only when reading data. The output is enabled by.

The X terminal has a bit inversion control signal of "0" or "1" common to the four ROMs 52, 53, 54, 55 depending on the bit arrangement sequence of data at the time of input / output in the device that accesses the memory. Is applied, and the Y terminal, which is also common to the four ROMs, has an 8-bit bus master, that is, as shown in FIG.
When the CEP 20 accesses the lower byte side 31b of the memory, "1" is applied to this Y terminal. As the signal applied to the Y terminal, for example, the least significant bit of the address, which is not normally used in a 16-bit microprocessor, is used.

When the 16-bit MPU10 accesses the memory, (X,
Y) = (0,0). At this time, each of the 16 bits D0 to D15 of the data bus 4 is directly input terminal I on the RAM 31a, 31b.
Applied on 0 to I15. And RAM31a, 31b from MPU10
By applying the access signal to the CE terminal, the address signal to the address terminal, and the write signal to the WE terminal, the 16-bit data on the data bus 4 is stored in the memory in the same bit arrangement order. Written in.
Also, at the time of reading, by applying a read signal from the MPU 10 to the EN terminals of the ROMs 54 and 55, the data from the output terminals 0 to 15 of the RAMs 31a and 31b are taken out to the data bus 4 as they are. That is, in this case, the configuration of FIG. 5 is equivalently as shown in FIG. 6 (1).

Next, when the CEP 20 accesses the upper byte side 31a of the memory, (X, Y) = (1,0). At this time, the bit arrangement order of the data D8 to D15 on the upper byte 4a of the data bus 4 is reversed and becomes D15 to D8, which is the input terminal I of the RAM 31a.
Applied to 0 to I7. And from CE P20, CE with RAM 31a only
By applying the upper byte access signal to the terminal and further applying the address signal and the write signal, the above-mentioned D15 to D8 are written in the memory chip 31a. here,
The data D8 to D15 sent from the CEP20 onto the upper byte 4a of the data bus 4 originally had the bit arrangement order to be recorded in the memory reversed, so as described above.
Since the order is D15 to D8, it is written in the memory in the correct bit arrangement order. Even at the time of reading, the data outputted from the output terminals 0 to 7 of the RAM 31a are reversed in the bit arrangement order and outputted to the upper byte 4a of the data bus 4. That is, in this case, the configuration of FIG. 5 is equivalently as shown in FIG. 6 (4).

When the CEP 20 accesses the lower byte side 31b of the memory, (X, Y) = (1,1). At this time, the bit arrangement order of the data D8 to D15 on the upper byte 4a of the data bus 4 is reversed to become D15 to D8.
Applied to the input terminals I0 to I7 of 31b. This time, it is controlled so that only RAM31b is enabled.
8 is R by the address signal and the write signal as above.
Written to AM31b. At the time of reading, the data whose bit arrangement order is reversed is read from the RAM 31b onto the upper byte 4a of the data bus 4. That is, in this case, the configuration of FIG. 5 is equivalently as shown in FIG. 6 (5).

Further, although not shown in FIG. 2, the system of FIG.
When connecting the device shown in FIG. 1, the first device (1) shown in FIG.
Connect to upper byte 4a of data bus 4 as is. In this case, when the fourth device accesses the RAM 31a on the upper byte side of the memory, if (X, Y) = (0,0) in the configuration of FIG. 5, the upper byte of the data bus 4 is The data on 4a is applied to the input terminal of the RAM 31a without changing the bit arrangement order as it is, and is written to the RAM 31a by applying the upper byte access signal, the address signal and the write signal as described above. Get caught. The same applies when reading. That is, the configuration in this case is equivalently as shown in FIG. 6 (2).

When the fourth device accesses the RAM 31b on the lower byte side of the memory, the data on the upper byte 4a of the data bus 4 remains unchanged by setting (X, Y) = (0,1). It is applied to the input terminal of the RAM 31b and written in the RAM 31b in the same manner as above. The same applies when reading.

It should be noted that the CEP 20 is connected to the lower byte 4b of the data bus, as is apparent from the fact that the wiring in the configuration of FIG. 5 is symmetrical with respect to the RAMs 31a and 31b, and is also symmetrical with respect to the upper and lower sides. Even in such a case, the upper byte side 31a of the memory can be accessed by setting (X, Y) = (0,1).

That is, in the configuration of FIG. 5, generally, by setting Y = 1, the upper byte 4a of the data bus 4 is placed on the lower byte side 31b of the memory and the lower byte 4 of the data bus 4 is set.
b is connected to the upper byte side 31a of the memory. If Y = 0, the upper byte 4a of the data bus 4 is connected to the upper byte side 31a of the memory and the lower byte 4b of the data bus 4 is connected to the lower byte side 31b of the memory.

Further, as described above, by setting X = 1, each of the upper byte 4a and the lower byte 4b of the data bus 4 becomes
One of the high-order byte side 31a and the low-order byte side 31b of the memory (the one designated by Y above) is connected in reverse bit order. If the bit order is X = 0,
It will be in a normal order. In this case, it is equivalently as shown in FIG.

As described above, according to the configuration of FIG. 5, the bit arrangement order is reversed and the upper byte of the memory, or The lower byte can be easily accessed.

It should be noted that in the description of the above embodiment, the section 31a of the memory 30,
The width of 31b and the logic circuits 52, 53, 54, 55 is set to 8 bits, but the connection relation of bits in FIG. 5 is generally established even if 8 bits → 4L bits, where L is a natural number in FIG. .

〔The invention's effect〕

According to the present invention, when connecting a device for inputting and outputting a plurality of types of data having different bit arrays from the same input / output terminal,
A data processing system that minimizes an increase in software load and an increase in hardware due to the connection of the devices is realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration at a stage before reaching the present invention, FIG. 2 is a schematic configuration diagram of the present invention, FIG. 3 is an overall configuration diagram of a first embodiment of the present invention, and FIG. FIG. 3 is a diagram showing a configuration example of the data / bit connection unit 5'and the memory 30, FIG. 5 is a configuration diagram of the data / bit connection unit 5'and the memory 30 in the second embodiment of the present invention, and FIG. 5 is an explanatory view of the configuration of FIG. 5, FIG. 7 is a diagram showing the difference in the bit arrangement order of input / output data in CEP and MPU, and FIG. 8 is a configuration diagram of the first example of the conventional data processing system, and FIG. 9 is a block diagram of a second example of the conventional data processing system. (Explanation of symbols) 1 ... First device, 2 ... Second device, 3 ... Third device, 4 ... Data bus, 4a ... High byte of data bus, 4b ... Data・ Lower byte of bus, 5,5 '... Data bit connection, 6a, 6b, 7a, 7b ... 8 bit path, 10 ... MPU, 11 ... MPU control signal line, 20 ... CEP , 21 …… CEP control signal line, 22 …… multiplexer, 23 …… bus transceiver, 30 …… memory, 30a …… higher byte area of memory, 30b …… lower byte area of memory, 31a, 31b …… RAM, 50,51 …… Multiplexer, 50a, 50b, 51a, 51b …… Bus transceiver, 52,53,54,55 …… ROM.

Claims (1)

[Claims] 1. A data bus (4) consisting of upper and lower divisions, each consisting of 4L bits, where L is a natural number.
Upper and lower divisions (30a, 30
In a data bus connection system (5 ') for connecting to a memory (30) consisting of b), the data bus connection system (5') is responsive to a first control signal from the outside, The upper and lower divisions of the data bus (4) are respectively replaced by the upper and lower divisions (30a, 30b) of the memory (30), or the upper and lower divisions of the memory (30) are interchanged. And the data bus (4) according to a second control signal from the outside.
The data bus connection system (5 ') is connected to the memory (30) by setting the bit order in each of the upper and lower partitions of the data bus (4) to the normal or reverse order. And subdivisions (4a, 4
b) and first and second logic circuits (52, 53) between the upper and lower two (31a, 31b) input terminals of the memory (30), and the memory (30 Third and fourth logic circuits between the output terminals of the upper and lower two sections (31a, 31b) of 30) and the upper and lower sections (4a, 4b) of the data bus (4). (54, 55), and the first, second, third and fourth logic circuits (52, 53, 54,5
5) has the same configuration, and the first, second, third and fourth logic circuits (52, 53, 5)
4,55) and 4L + 2 bit input terminals respectively
It has a 4L bit output terminal, inputs data from the 4L bit of the input terminal, and outputs the first from the remaining 2 bits of the input terminal.
And a second control signal, and in accordance with the first control signal, the upper and lower 2L bits of the 4L bits of the input terminal for inputting the data are respectively set to the upper of the 4L bit output terminal. And output as lower 2L bits respectively, or by switching the upper and lower sides and outputting as the lower and upper 2L bits of the 4L-bit output terminal respectively, and further according to the second control signal. , The upper and lower 2L bits of the 4L bits of the input terminal for inputting the data are output in the normal order or the reverse order of the respective 2L bits, and the lower order (4b) of the data bus (4) is output. ) Lower L bits (D0 to D1) of the first logical circuit (52) are input to the lower L bits (I0 to I1) of the second 2L bits of the lower section (4b) of the data bus. (D2 to D5) are the second logic circuits (53) The lower 2L bits (I0 to I3) of the input terminal and the upper L bits (D6 to D7) of the lower section (4b) of the data bus are lower than the input terminal of the first logic circuit (52). Are connected to the next L bits (I2 to I3) in the order from the upper to lower, and the lower L bits (D8 to D9) of the upper section (4a) of the data bus are input to the first logic circuit (52). The data is transferred to the next L bits (I4 to I5) in order from the lower order of the terminal to the higher order.
The next 2L bits (D10 to D13) of the upper section (4a) of the bus are the upper 2L bits (I4) of the input terminal of the second logic circuit (53).
To I7), the upper L bits (D14 to D15) of the upper section (4a) of the data bus are connected to the upper L bits (I6 to I7) of the input terminal of the first logic circuit (52). , Each of the output terminals of the first and second logic circuits (52, 53) has the data bus (4) seen from each of the input terminals of the first and second logic circuits (52, 53). ) Is connected to each of the input terminals of the upper and lower divisions (31a, 31b) of the memory (30) in a correspondence equal to the connection relationship with each bit of the upper and lower divisions (4a, 4b), Upper and lower division of memory (30) (31a, 31b)
Of the output terminals of each of the third and fourth logic circuits (5
4, 55) each of the input terminals means the respective bits of the upper and lower divisions (4a, 4b) of the data bus (4) and the inputs of the first and second logic circuits (52, 53). Are connected in a manner equivalent to the connection relationship with the terminals, and each of the output terminals of the third and fourth logic circuits (54, 55) and the upper and lower sections (4a, 4a) of the data bus (4). Each bit of 4b) is a connection between each of the output terminals of the first and second logic circuits (52, 53) and the input terminals of the upper and lower sections (4a, 4b) of the memory (30). The first and second logic circuits (52, 53) are set to always enable output, and the third and fourth logic circuits (54, 55) are Controlled by the bus master so that output is enabled only when data is read from the memory (30) Data bus connection system, wherein the door.