JPH0775003B2 - Program content analyzer - Google Patents

Description

[Detailed Description of the Invention] In general, comparing a program written in an assembler language with its specifications and analyzing the basic structure and operation thereof has conventionally been performed with a great deal of manual labor, and is also erroneous. Was difficult to avoid. In the present invention, the basic operation and structure of such a program to be analyzed is determined by the input / output state by the load instruction or the store instruction and the branch state by the branch instruction that makes the execution order different from the array order. I focused on that. Therefore, the path data for identifying the execution path defined by the branch instruction and the position data of the branch destination instruction and the branch source instruction in relation to the branch instruction are set for each instruction.

A program is read upside down from a store instruction or a branch instruction, and the output contents such as flow charts and PAD diagrams are output as a combined logical expression whose execution contents and branch conditions represent the execution contents of each instruction. obtain. At this time, the longer the program is, the larger the output amount becomes. Therefore, a logical operation is performed on the combined logical expression of the logical expressions, and the output is simplified. As a result, the output can be obtained in a simplified format that can be easily compared with the program specifications, and the efficiency of analysis processing and the occurrence of errors can be prevented.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for analyzing the contents of a program used to operate a microprocessor or the like.

2. Description of the Related Art The assembler language is used to describe a program as a language that is the closest to the machine language that is actually read when the microprocessor operates. Unlike a high-level language, this assembler language has a one-to-one correspondence with each machine language instruction, so the operation contents of various input / output devices based on this program and the outline of the program execution contents are It is difficult to understand, and it is necessary to manually perform each command in order to check the contents described in the specifications. Moreover, the technique of checking the operating state of the program by performing simulation or emulation, etc. is adopted, but these must set numerical values and data corresponding to various input commands required in the program.

Therefore, by reading each instruction of the program and recognizing the process and flow structure of the entire program, the execution contents of the program can be roughly described, or described as the operation of the input / output device. It is envisioned that the technology will try to obtain an output in a format that is easy to understand. In this case, the final output to the I / O device based on the program is a store instruction in which the microprocessor writes some data to a predetermined address of the memory. Therefore, if the contents of the variable of the operand appearing in the store instruction are finally determined, for example, the load instruction, if the instruction is read upside down and the instruction is read, the content of the variable is assumed to be data input by the load instruction. Will be confirmed. In this way, the execution contents of the program can be roughly described by the variables of the operands used in the load instruction.

Problems to be Solved by the Invention In such a conventional example, a case where a program to be analyzed has a structure shown in FIG. 19 will be described. This program is composed of the instructions of steps a1 to a10, and call instructions "CALL A" and "CALL B" for calling a subroutine program are arranged in steps a2 and a4. Here, when going up the program from step a5, there are two types of reverse going paths: a5 → a8 → a7 → a6 → ... and a5 → a8 → a7 → a10 → a9 → ... Considering the order of execution, the latter is a path that cannot actually be executed.

In other words, when analyzing the contents of a program, only the technique of reading the program in reverse order and sequentially based on the execution contents of the instruction makes the path that is impossible from the actual execution path of the program subject to analysis. However, the analysis time becomes long, and an analysis result different from the actual program execution content is derived, which is a serious problem.

An object of the present invention is to provide a program content analysis device capable of displaying a complicated expression in an easily understandable manner in displaying a condition for executing a predetermined execution content of a program. is there.

Means for Solving the Problems The present invention reads each instruction of a program consisting of a plurality of instructions in reverse order of the arrangement order, analyzes the content, and analyzes each execution content and a condition under which the execution content is performed. In a device for outputting, a reading means for reading the execution contents of each instruction by reversing a program, and a first logical expression corresponding to a condition for passing a path leading to an instruction related to the execution contents among the read instructions. Execution content for obtaining information, synthesizing first logical expression information for all paths related to the execution content as total logical expression information in a logical sum form, and storing the total logical expression information in association with the execution content Storage means, decomposing means for transforming and outputting the given logical expression information into a logical sum form of logical products, and for the logical expression information given from the decomposing means, parenthesized terms related to the same term In a tough form A first identical term organizing means for outputting in a form, and a second identical term organizing means for transforming the given logical expression information into terms related to the same term in parenthesized form, and outputting 1 Of the formula information given from the same term arrangement means,
Pattern transformation means for transforming and outputting a term corresponding to a predetermined transformation pattern according to the predetermined transformation pattern, and execution contents for displaying logical expression information given by the pattern transformation means and its execution contents in association with each other. It is provided between the output means and the first identical term organizing means and the pattern transforming means, and detects whether or not the predetermined pattern is included in the logical expression information given from the first identical term organizing means, If the predetermined pattern is included, logical formula information is output to the pattern synthesizing unit; if not, the first selecting unit that outputs logical formula information to the decomposing unit; the pattern transforming unit and execution content output. Means for determining whether or not the same term is included in the logical expression information provided from the pattern transforming means, and if the same term is included, the second same term organizing means. Program content analysis, characterized by further comprising: second selection means for giving logical expression information to the first selecting means via the above, and for giving logical expression information to the execution content output means if the same term is not included. It is a device.

Operation According to the present invention, the program is read upside down, the first logical expression information is obtained by this, and the decomposing means has a function of transforming into a form of the logical sum of logical products and outputting it. It is possible to identify terms related to the same term in parentheses with respect to the logical expression information from the disassembling means, that is, to identify terms including the same term. Output from the means, a second same term arrangement means is also provided, and the predetermined execution content is executed by including the pattern transformation means, the execution content output means, the first selection means, and the second selection means. In displaying the conditions for performing, it is possible to easily display the complicated display by transforming it.

First Embodiment FIG. 1 is a block diagram showing a configuration example of a program content analysis device (hereinafter abbreviated as an analysis device) 1 according to an embodiment of the present invention. An external storage device 2 is connected to the analysis device 1 and stores a program written in a high-level language or an assembler language to be analyzed. The analysis apparatus 1 includes an assembler 3 that changes the program from the external storage device 2 into a machine language, and the assemble list from the assembler 3 is stored in the assemble list file storage unit 4. Below "memory section"
Indicates a predetermined area of an internal storage device such as a RAM (random access memory) or a fixed disk device provided in the analysis device 1.

The assemble program to be analyzed from the assemble list file storage means 4 is given to the analysis preparation processing means 5, and the data of the program to be analyzed is classified according to the contents prior to the program analysis described later. A plurality of storage units are connected to the analysis preparation processing means 5. The list file storage unit 6 stores an instruction sequence including a machine language of a program to be analyzed and a mnemonic of an assembler language. RA
Various variables used in the analyzed program are stored in the M file storage unit 7. The map data storage unit 8 stores fixed data in a map format or the like used in the analyzed program. In addition, the storage unit 9 is connected to store the vector address of the interrupt vector used in the analyzed program, the label related to the mnemonic program stored in the list file storage unit 6, and the like. The analysis device 1 is also provided with an instruction data file storage unit 10 in which instructions used in the analyzed program are stored in advance.

The program in the mnemonic format from the list file storage unit 6 is given to the flow structure analysis unit 11 as a branch data creation unit, and the structure of the processing flow in the analyzed program, that is, the presence or absence of a branch and the branch instruction are assumed. In this case, the position variation of the branch destination instruction and the stack nesting degree are analyzed. Here, a flow control file, which is the basic data for all subsequent analysis processes, is created and stored in the flow control file storage unit 12. Based on the respective data from the list file storage unit 6, the instruction file storage unit 20 and the flow control file storage unit 12, the branch condition analysis unit 13, the store content analysis unit 14, and the complete branch condition analysis unit 15 perform respective analyzes described later. The processing is performed, and each obtained data is stored in the branch condition file storage unit 16 including the route data storage unit and the position data storage unit, the execution content file storage unit 17, and the complete branch condition file storage unit 18.

The flow chart creating unit 19 creates and outputs a flow chart of the analyzed program from the flow control file, the branch condition file, and the execution content file. Further, the execution content analysis result output unit 20 prints out the execution content of the analyzed program from the execution content file and the complete branch condition file, for example.

FIG. 2 is a flow chart for explaining the operation of the analysis preparation processing means 5. In step a1, the analysis device 1 reads the source program from the external storage device 2, and the assembler 3
Assemble at. To the assemble program stored in the assemble list file 4, the analysis preparation processing means 5 gives a series of numbers (hereinafter referred to as line numbers) to each instruction in step a2. At this time, each instruction is classified according to its type, such as a store instruction, an input / output instruction, a branch instruction, or an arithmetic instruction, as will be described later. This is performed by referring to the instructions stored in the instruction data file storage unit 10. At step a3, the above-mentioned various data files are created based on the classification of such instructions.

Next, the analysis apparatus 1 performs the flow structure analysis processing on the program file composed of the machine language and the mnemonic stored in the list file storage unit 6 by the flow structure analysis means 11. This analysis process is the process of analyzing the flow structure of the analyzed program (whether there is a branch, specification of branch destination, stack nesting degree, etc.), and the various files described above that are the basic data of all subsequent analysis programs are analyzed. create. In particular, in addition to extracting the line number of the branch destination instruction based on the existence of a branch instruction, "backward going"
Create data representing concepts and "attribute" concepts.

(1) Reverse going up concept When analyzing the execution contents of a program in order to read and analyze the instructions according to the execution order, the change of the condition code such as various flags and the correlation between a plurality of instructions It is necessary to store all the data expected to be associated with the command, such as relationships. Even if such data contains unnecessary data depending on the type of instruction, it is not possible to determine which data will be needed in the subsequent analysis processing, so all data will be deleted. Need to collect.

The "reverse uphill" concept according to the present invention is a measure for solving such a problem.

The present invention is intended to describe a program written in a machine language or an assembler program by a logical expression in a format that is easy to understand by synthesizing branch conditions and store contents of a branch instruction and a store instruction. Therefore, starting from the branch instruction or the store instruction, the program goes back up to a point where the content of the branch condition or the store instruction is determined, and only necessary information is collected.

Here, a program example will be described according to the program shown in Table 1 below.

In the above program example, the execution order is line number 1 → 2 → 3 → 4
→ 5 → 6 or line numbers 1 → 2 → 3 → 4 → 5 → 7.
The branch instruction is "BCC", and the condition is line number 4 (A
-# 8) is determined to be 0 or more or negative. For that purpose, the value of the accumulator A must be determined. For that purpose, it is necessary to determine the values of both accumulators A and B at line number 3, and the values are determined only after reading line numbers 2 and 1.

In the flow structure analysis means 11, the information required for the reverse processing,
That is, a certain instruction and its preceding line are data for judging whether or not there is a continuous instruction according to the execution order of the program,
When these commands are discontinuous, attribute data, which will be described later, such as data regarding to which line number the command is continuous, is created.

(2) Attribute concept The program is composed of a main routine and a subroutine whose processing branches from a predetermined part of the main routine. Even the same subroutine may be called from a plurality of locations, and the position of the branch destination by the return instruction RET that returns processing to the main routine changes corresponding to the calling instruction of the main routine. Therefore, it is considered that a plurality of execution paths are set even by one subroutine, and the attribute concept is set as information for dividing the processing paths. Hereinafter, description will be given along the program example shown in Table 2.

The flow chart of the above program example is shown in FIG.

The execution order of this program example is line number 1 → 2 → 3 → 9 →
10 → 11 → 4 → 5 → 6 → 8 → 9 → 10 → 11 → 7 → ....
On the other hand, when going up the program from line number 7, the first route is line numbers 7 → 11 → 10 → 9 → 8 → 6 → 5 → 4 → 11 →
There are 10 → 9 → 3 → 2 → 1 →…, but in addition, line number 7 →
It means that there are reverse going routes such as 11 → 10 → 9 → 3 → 2 →. Such a latter reverse uplink route is a route that is impossible in the order of execution, and the attribute concept is used to prevent the selection of such an undesired route.

In the program example of Table 2, the branch destination column, the branch source column,
The contents of the flow flag column and the attribute column are determined as follows.

(A) Attributes Line numbers 1 to 7 are all given the same attribute symbol M because their processing branches by the CALL instruction of line numbers 3 and 6 and does not include a subroutine program. Line number 9-
Reference numeral 11 is a subroutine program whose processing is moved by the CALL instruction at line number 3 and is given the attribute symbol A. Line numbers 8 to 11 are subroutine programs whose processing is transferred by the CALL instruction of line number 6, and attribute symbols B different from the attribute symbol A are given respectively.

(B) Branch destination column The branch instructions of the above program are arranged in line numbers 3, 6, 7, and 11, and the destinations to which these processes move correspond to the line numbers 9, 8, 1 respectively. In the branch instruction RET, the line number 4 or line number 7 immediately after the corresponding CALL instruction is used. In the branch destination column, data in which the line number of the branch destination and the attribute of the instruction of the line number are paired is set.

(C) Branch source column From the branch destination instruction to which the processing is shifted by each of the branch instructions, the branch source instruction from which the processing shifts to the branch destination instruction is associated. Therefore, in the branch source column, when the branch source instruction is associated with each instruction, data in which the line number of the branch source instruction and the attribute symbol to which the branch instruction belongs are paired is set. It

(D) Flow flag column The flow flag "1" indicates that the instruction is an instruction continuous from the instruction in the preceding line. The flow flag “0” indicates that the instruction is a branch destination instruction from which the process branches from an instruction other than the instruction in the preceding line. That is, the line numbers 1 to 3 are a series of commands, and the command of line number 4 is executed by the subroutine program A by the CALL command of line number 3 and the command of line number 11 is executed.
This is an instruction whose processing has branched by the RET instruction. Therefore, the flow flag “0” is attached. Similarly, line numbers 5,6
Is assigned a flow flag “1”, and row number 7 is assigned a flow flag “0”.

Line number 8 is an instruction whose processing is branched by the CALL instruction of line number 6, and a flow flag "0" is added. Line number 9
Is an instruction whose processing is branched by the CALL instruction of line number 3 and is an instruction to which a flow flag "0" is added. However, since the CALL instruction of line number 6 is performed after the CLL for the line number 3 , Line number 9 is an instruction continuous to line number 8, and the flow flag "1" is given as shown in Table 2. Line number 10,11
Is given the flow flag "1".

In the program examples in Table 2 above, the instructions such as the CALL instruction in which the processing branches from the instruction and the processing branches to the instruction are explained. Generally, the execution of the program of the microcomputer is performed by the program counter (PC). The instruction of the address output by is read and executed, and the address of the instruction to be executed next by the execution of the instruction is stored in the program counter.

On the other hand, if the program includes a subroutine program, the process branches, but at this time, the stack is used. As is well known, the stack is a first-in / first-out (first-in-last-out, FILO method) memory and stores the next address of the main routine to which the process returns when the subroutine is called.
After the processing of the subroutine is completed, the data stored in the stack is transferred to the program counter by the return instruction RET, and the program is executed from that address. Therefore, if the instruction to change the stored contents of the stack is included, the return destination from the subroutine program can be changed. An example of such a program is shown in Table 3 below.

In the program example of Table 3, line numbers 4 to 8 of the program example of Table 2 are changed. The method of determining the data in the branch destination column, the branch source column and the flow flag column in the program example of Table 3 is the same as in the program example of Table 2. Hereinafter, a method of determining attributes will be described.

Line numbers 1 to 3 are a series of instructions and give attribute data M. Since the process branches to the line number 9 by the CALL instruction of the line number 3, another attribute symbol A is given to the line numbers 9 to 11. The RET instruction at line number 11 returns the process to line number 4. The attribute symbol M is given to this command.

The latest address data of the stack described above is rewritten to the contents of the X register by the PSH instruction in line number 5. At this time, the attribute data is changed to B, and the same attribute data B is given up to line number 11 below. In this way, the attributes relating to the program including the instruction to change the data stored in the stack are determined.

The attribute data of the flow control data relating to the program examples in Tables 2 and 3 above are, for each execution path of the program, for a branch instruction including an instruction for changing the contents of the stack,
Different symbols are given as described above. In the case of such a method, when the number of attributes in the analyzed program increases, when analyzing the program in the reverse way as described later, the attribute data in all the attribute columns are searched for each instruction and the same attributes are obtained. Since a process that goes up along with it is performed, a faster process can be realized if the number of the attribute data can be reduced.

The following Table 4 has the same program content as the program content of Table 3, but the flow control data different from those in Tables 2 and 3 are stored in the branch columns 1, 2, ... And the attribute columns 1, 2 ,. It is set as ... Hereinafter, these determination methods will be described.

(E) Attribute column i (i = 1, 2) ... The line number data NO in the attribute column is set for each branch instruction, and the line number of the branch destination instruction is described. The attribute data to indicates to which attribute column the process has branched by the branch instruction. In the ascending flag column, flag = “0” indicates that the corresponding instruction is a branch target instruction, and the instruction on the immediately preceding line is an instruction whose processing is not continuous, and flag = “j” (j = 1, j = 1,
2, ...) indicates the number in the attribute column. Line number 1 may be a branch target instruction having line number 11 as the branch instruction, and accordingly, the flag = "0" is set. Further, in the forward flag column, a flag = “0” indicates that the corresponding instruction is an instruction whose processing is not continuous with the instruction immediately after it and is a branch instruction.

In line number 2, the number in the attribute column 1 that was set first is flag =
It is set as "1". Line number 3 is a branch instruction,
The branch destination line number data NO = “9” is set. To = “1” is set for the attribute data to. After this, the process branches to the line number 9, and accordingly, the reverse flag = “0”.
Is set. The reverse flag = “1” is set in the line number 10. Line number "11" is the branch source instruction, and line number data NO = "4" is set. The instruction of line number 4 is currently in the range of attribute column 1, and therefore the attribute data
to = “1” is set.

After this, the process moves to line number 4. Therefore, the reverse ascending flag and the forward descending flag are "0" and "1". After this, the reverse flag = “0” or “1” is set in the row numbers 5 to 10. After this, the process is line number
To reach 11. The branch destination is changed to the line number 1 by the RSH instruction of the line number 5, and accordingly, the attribute column 2 is added and the reverse ascending flag = “2” is set. Line number data NO = "1" and attribute data to = "1" are set.

(F) Branch source column i (i = 1, 2, ...) The data of this branch source column is set for the branch destination instruction, and the line number data NO of the branch destination and the instruction immediately preceding the branch instruction belong. The column number fr and the attribute column number to to which the branch destination instruction belongs are set.

Hereinafter, it will be explained that reverse program analysis is possible with the program example of Table 4 using the data in the branch source column and the data in the attribute column. If the user reverses the reverse flag = “1”, the reverse flag = “0” at line number 9, so the branch source column is referred to, and it is understood that the branch is made from the attribute column 1 at line number 3. . Further, in the reverse direction, line number 1 fixes all the information. Therefore, the route relating to the reverse ascending flag = "1" is the line number 10 → 9 → 3 → 2 → 1.

The contents of each execution are 10th line A → [X + 0]… Undefined variable A, X 09th line A ← A + 1… Undefined variable A, X 03th line Undefined A, X No change 02 line A ← [ X + 0]… Undefined variable X 01th line X ← PORT1… Since there are no undefined variables, A → [X + 1] obtained on the 10th line instead of A → [X + 0] 'A' obtained on the 10th line. Replace'A + 1 → [X + 0] Instead of'A ', get at line 02 and replace'X + 0' [X + 0] + 1 → [X + 0] Get at line 01 instead of'X 'Replacing'PORT1'yields [PORT1 + 0] + 1 → [PORT1 + 0].

It is understood that the processing content is [PORT1 + 0] + 1 → [PORT1 + 0] (1).

On the contrary, if the user goes up for the reverse flag = “2”, the attribute column 2 is first referenced, but the reverse flag =
Since it is changed to "1", the attribute column 1 for the line number 8
Is referred to. From this point onward, as in the case described above, reading is performed in reverse, and all the information is determined at line number 6. According to this, the processing contents are line numbers 10 → 9 → 8 → 7 →
It can be understood that by following 6 it becomes [PORT2 + 0] + 1 + 1 → [PORT2 + 0] (2).

FIG. 4 is a flow chart for explaining the operation of the flow structure analysis means 11. The outline of the operation of the flow structure analyzing means 11 has been described with reference to Tables 2 to 4 above, and the operation will be described in detail below. In step c1 in FIG. 4, the line number ln for starting the analysis is set to a predetermined value, and various data are initialized to predetermined values. At step c2, it is determined whether the processing has reached the last line. If not, processing is step
Move to c3, the line number ln of the instruction currently being analyzed
It is determined whether or not the array CZ [ln] representing the number of attribute fields set for is 0. If the number array CZ is 0,
This means that this is the first instruction to be analyzed.

If the determination in step c3 is negative, the process proceeds to step c4 and the number of attribute fields is increased by one. Fourth in step c5
Set the attribute data described with reference to the table. Step
At c6, it is determined whether the instruction at line number ln is a branch preceding. If it is a branch preceding, the branch source column such as the branch source column 1 in the instruction of the fourth table row number 4 is set at step c7, and the process proceeds to step c8. If the judgment at step c6 is negative, step c6
Moving to c9, the reverse uplink flag and the forward downlink flag are set.

Hereinafter, the reverse uplink flag and the forward downlink flag will be described. FIG. 5 is a diagram for explaining the structure of the flow control file storage unit 12. The flow control file storage unit 12 includes a branch source file unit 21 and an attribute file unit 22. Sixth
The figure illustrates the structure of the branch source file portion 21. The branch source file unit 21 is provided for each line number, and the branch source number storage unit 23 that stores the number of branch source instructions whose branch destination is the line number and the branch source column described with reference to Table 4 are provided. For example, 80 areas are set in the corresponding branch source column storage unit 24. The branch source column storage unit 24 includes a line number storage unit 25, a branch source attribute storage unit 26,
It is configured to include a branch destination attribute storage unit 27.

FIG. 7 is a diagram for explaining the structure of the attribute file unit 22.
The attribute file unit 22 is provided for each line number, and the attribute number storage unit 2 stores the number of attribute columns set for the line number.
8, "1" if the attribute data of the command line is confirmed, "0" if indefinite, an indefinite flag storage unit 29 for storing an indefinite flag, corresponding to the attribute data to in the attribute column of Table 4 The attribute value storage unit 30 for storing the attribute value, and the branch condition storage unit 3 for storing the address storing the branch condition of the instruction of the line number in the branch condition file storage unit 16 shown in FIG.
1, a branch leading number storage unit 32 that stores the line number data NO and the attribute data to in the attribute column of Table 4, a branch destination attribute column number 33, and a reverse up flag corresponding to the flag of the attribute column of Table 4 And a forward-downward flag storage unit 35 for storing a forward-downward flag.

The forward flag is set as shown in the forward flag column of the attribute column 1 of Table 4, for example. That is, "1" is given if the instruction of a certain line number is an instruction continuous with the instruction of the immediately following line number, and "0" is given if it is a discontinuous instruction. Line number 2 in Table 4 is an instruction that is continuous with line number 3 and is given the data "1". However, the line number 3 is not continuous with the command of the line number 4, and therefore data "0" is given.

In the fourth illustrated steps c7 and c9, the reverse ascending attribute, the forward descending attribute, and the branch source column having the above-described contents are set.

First, in step c8, it is judged whether or not the instruction is a branch instruction. If it is a branch instruction, the process proceeds to step c10, and it is determined whether or not the branch instruction is an instruction such as the fourth table line number 11RET instruction which terminates the interrupt processing. If this judgment is negative, the process proceeds to step c11 to obtain the branch leading number. This is obtained by referring to the list file storage unit 6 in FIG. In step c12, the branch number data bi representing the number of branches is incremented by +1. In step c13, the branch number data bi and the row number are associated with the array m, m (bi) = ln ... (3).

At step c14, the stack changes are checked as described later. At step c15, the attribute data is calculated, and at step c16, the next line number is set in the variable ln, and the process is returned to step c2. If the determination in step c8 is negative, the process proceeds to step c14.

If the determination in step c3 is affirmative, the instruction is not the instruction line to be analyzed for the first time, and it is determined in step c17 whether or not there is an attribute column having the same attribute.
If this judgment is negative, the process moves to step c4 and the attribute column is increased. If the determination in step c17 is affirmative, step c
Moving to 18, it is determined whether or not the branch instruction is a branch preceding. If it is a branch preceding, the branch source column of Table 4 is set in step c19, and the process proceeds to step c20. If the determination at step c18 is negative, at step c21 the above step c
The reverse uplink flag and forward downlink flag described in 9 are set. Here, after steps c19 and c21, since the determination in step c17 is affirmative, it means that the same attribute column already exists, and the analysis has been completed for this attribute, and the analysis is not performed again. The analysis process is completed, and the process is moved to step c20.

At step c20, it is judged whether or not the branch number data bi is zero. If so, the process ends. If the answer is negative, it means that the analysis process has not been completed, and step c2
At 0, the line number ln of the branch instruction stored in step c13 is read in the array m (bi), the branch number data bi is decremented by 1 in step c23, and the process returns to step c2. That is, the analysis process is performed again from the line number ln read in step c22.

FIG. 8 is a flow chart for explaining the operation of the branch condition analyzing means 13. The branch condition analysis processing will be described according to the program contents shown in Table 4 above. In step d1, the line number sln is set to 0, and in step d2 the line number sln is incremented by +1. At step d3, it is determined whether the line number ln exceeds the last line number of the program, that is, the line number 11 in the program example of Table 4. If so, the process ends, and if not, the process moves to step d4. At step d4, it is determined whether the instruction at line number ln is a branch instruction. In the above program example, line number 1 is not a branch instruction, and the process returns to step b2 to proceed to the instruction of the next line number. It is determined that the instruction is a branch instruction at line number 3, and the process proceeds to step d5.

At step d5, the variable k representing the attribute column number is set to 0, and at step d6 the variable k is incremented by +1.
At step d7, k≤CZ (ln) (4) is judged with respect to the array CZ (ln) representing the number of attribute fields related to the instruction of the line number ln. If this judgment is negative, it means that the number of attribute columns for each instruction in the flow structure analysis processing shown in FIG. 4 has been exceeded, that is, branch condition analysis has been completed for all attributes in the branch instruction. Then, the processing shifts to step d2 to proceed to the instruction of the next line number.

If the determination in step d7 is affirmative, the process proceeds to step d8, and the reverse ascending process described later is started along the attribute column number k in the instruction of the line number ln to obtain the reverse ascending route. As described above, a participation flag, which will be described later, is set to the instruction necessary to determine the branch condition of the branch instruction. At step d9, the execution content of each instruction read backward is constructed as a branch condition as described later. At step d10, the branch condition thus obtained is stored in the branch condition file storage unit 16 shown in FIG.

FIG. 9 is a flow chart for explaining the details of the reverse ascending process of step d8 of FIG. Fig. 9 At step e1,
A control variable SW described later is initialized to 0. At step e2, it is judged whether or not the control variable SW is 0, and if affirmative, the process goes to step e3 to check the reverse ascending flag shown in the attribute column of Table 4 so that the reverse ascending flag becomes 0. Control variable SW = 2 when, and SW = 1 when reverse going flag is within 0
And set. After this, the processing returns to step e2.

FIG. 10 is a flow chart for explaining the details of the reverse ascending determination processing of the step e3. Figure 10 At step f1,
The attribute column number indicated by the attribute data to in the attribute column 1 of the fourth table row number 3 is read. In the above example, to = “1”, and the attribute column 1 is read. At step f2, the value of the reverse ascending flag in the attribute column 1 is set to the value of the attribute data to. At step f3, it is determined whether or not the attribute data to is 0.
If it is 0, it means that the instruction in the preceding line has lost the continuity in the execution order, and the control variable SW = 2 in step f4
And the process ends.

If the determination in step f3 is negative, the processing is continuous with the instruction in the preceding line, and the control variable SW = 1 is set in step f5. At step f6, the variable ln representing the line number is decremented by -1, and the processing is terminated. In the program of Table 4 and the line number 3 in the example, the attribute data to = “1”, and in this case, the control variable SW = 1.

Referring again to FIG. 9, if the determination at step e2 is negative, the process proceeds to step e4 to determine whether the control variable SW = 1. If affirmative, the process moves to step e5, and when all the information necessary to determine the branch condition of the above branch instruction is obtained, the corresponding reverse uplink flag is cleared and the newly necessary information is set to the corresponding flag. To do. When all the flags are cleared, the control variable SW = 4 is set, and otherwise, the control variable SW = 0 is set. After this,
The process returns to step e2.

FIG. 11 is a flow chart for explaining the details of the reverse uplink information setting process of the step e5. In step g1 in FIG. 11, the reverse ascending row counter rc is incremented by +1 every time the program to be analyzed is moved up one line at a time. In step g2, the counter cn for reverse going is used as a variable, and the line number ln, the attribute data to, the branch column number nd, the branch condition of the branch instruction or the store instruction, or the line number rn0 of the instruction necessary to determine the store condition is set. In the work memory m which is temporarily stored, the row number ln which is inverted is stored first.

At step g3, similarly, the attribute data to of the inverted command is stored in the work memory m. In step g4, the number of branch source instructions branching to the same attribute as the attribute data to of the instruction is counted in the branch source column 21 of the branch source file unit 21 shown in FIG. 6 corresponding to the inverted line number. ,Remember. Further, the branch source column number nt is stored in the work memory m for each branch source instruction stored in the work memory m.

At step g5, it is judged whether or not the various data obtained at steps g2 to g4 are necessary. Line number 3 in Table 4
CALL instruction is an unconditional branch instruction. Therefore, the above-mentioned various data of line number 2 are unnecessary, and the determination is negative. On the other hand, the fourth table row number 3 is the BBC of the first table row number 5
If the instruction is a conditional branch instruction and the line number 2 is involved in the branch condition, the process moves to step g7, and the number given to each such instruction is stored in the work memory. In step g8, the information flags other than the work memory are cleared, and the process proceeds to step g9.

In step g9, it is judged whether or not there is new necessary information, and if there is new information, a new information flag is set in step g10,
Move to step g11. If the determination in step g5 is negative, data "0" is set in the work memory m (rcrn0), and the process proceeds to step g11. The same applies when the judgment in step g9 is negative.

At step g11, it is judged whether or not a necessary information flag indicating whether or not new information is necessary to determine the branch condition or the contents of the store instruction is "0". That is,
When the necessary information flag is "1", it means that the execution contents of the branch instruction or the store instruction from which the reverse ascending analysis processing has started are fixed, and the processing moves to step g12, and the control variable SW
= "4". This is because, as will be described later, a process of writing the data stored in the work memory m into the branch condition file storage unit 16 of FIG. 1 is performed. If the determination in step g11 is negative, the process proceeds to step g13 and the control variable SW = "0" is set. This is because, as will be described later, when the process returns to step e2 in FIG. 9, the process moves to step e3 to continue the reverse ascending process.

In this way, step e5 in FIG. 9 is executed, and the process returns to step e2. If the determination in step e4 is negative, the process proceeds to step e6, and it is determined whether the control variable SW = “2”. In this case, as described in step e3, the case where the backward flag is "0" and the processing order is not continuous with the instruction immediately before the line number is shown. In such a case, since it is necessary to branch the reverse uplink analysis process, the process moves to step e7. Step e7
Then, as will be described later, the line number of the branch destination of the reverse ascending analysis processing is obtained, the control variable SW is set to "1", and the processing is returned to step e2.

FIG. 12 is a flow chart showing the details of the reverse ascending branch process of step e7 in FIG. Fig. 12 In step h1,
In step g4 of FIG. 11, the branch source column number is read from the work memory m [rc, nd (cn)] in which the branch source column number is stored, and the fourth
In the branch source column 1 or the like as shown in the table, the corresponding branch source line number data NO or the branch source attribute data, that is, the branch source attribute column number fr is obtained, and the branch source line number data NO is assigned to the line number ln. The branch source attribute data is set in the attribute data to in step h2.

At step h3, the branch number data m [rc], cn set at step g4 in FIG. 11 is decremented by -1. After that, in step h4, the control variable SW is set to "1", and the process is terminated.

Thus, the processing of step e7 in FIG.
Return to e2. If the judgment in step e6 is negative, step e8
Then, it is determined whether or not the control variable SW = “3”.
If this judgment is affirmative, the process moves to step e9 to find the start line number of the analysis route that holds the reverse ascending analysis, and
Set SW = "2" and return the process to step e2.

FIG. 13 is a flow chart showing the details of the unanalyzed data processing of FIG. 9 step e9. In step p1 of FIG. 13, it is judged whether or not the reverse path counter rc is "0".
That is, it is determined whether or not there are unanalyzed reverse uplink analysis routes. If such an unanalyzed reverse ascending route does not exist, the process proceeds to step p2, the control variable SW is set to "5", and the process ends. If the determination in step p1 is negative, the process moves to step p3, the reverse route counter rc is decremented by -1, and the branch number work data m (rc), cn explained in step g4 in FIG. 11 is 0 in step p4. Determine if there is. If it is 0, the process returns to step p1 and the same process is performed for other unanalyzed routes.

If the determination in step p4 is negative, the process proceeds to step p5, the control variable SW is set to "2", and the process is terminated.

Referring again to FIG. 9, the unanalyzed route analysis processing of step e9 is completed in this way, and the processing returns to step e2. If the determination in step e8 is negative, the process proceeds to step e10 to determine whether the control variable SW = "4". If the result is affirmative, it means that the reverse-link analysis processing has been completed for all the possible reverse-link analysis paths, and step e11
The branch condition file of FIG. 1 is used as the analysis path obtained in step 1, that is, the line number data of each instruction forming the reverse analysis path.
Write to 16. When the unanalyzed route remains, the control variable SW is set to "3".

FIG. 14 is a flow chart detailing the processing of step e11 in FIG. In step q1 in FIG. 14, it is judged whether or not the reverse uplink route counter rc is zero. If 0,
Since the analysis has been completed over the previous reverse uphill route, the above-mentioned route data storage processing is performed, and the processing is terminated. If the determination at step q1 is negative, the process proceeds to step q3 and the control variable SW = “ "3" is set and the processing ends.

Referring to FIG. 9 again, the data writing process is thus completed at step e11, and the process returns to step e2. If the judgment in step e10 is negative, step p in FIG.
As described in 2, the analysis has been completed over the entire analysis path, and the processing for obtaining the path going up the program described in step d8 in FIG. 8 ends.

In step d9 of FIG. 8, processing for synthesizing branch conditions is performed for each reverse ascending analysis path obtained in step d8. The branch instructions in Tables 2 to 3 above are unconditional branch instructions,
The program example in Table 1 will be described. The branch instruction of this program example is the BCC instruction of line number 5, and according to the above-described process for obtaining the reverse route, line number 5 → 4 → 3 → 2 → 1 is set as the reverse ascending analysis route starting from line number 5. Is obtained.

That is, the branch condition of the branch instruction at line number 5 is A- # 8 ≧ 0 (5) obtained at line number 4, and the variable A is undetermined. The calculation of A ← (A−B) (6) is performed on the variable A in the line number 3, and the undetermined variables are A and B. Line numbers 2 to
With the instruction of 1, A = # 3 (7) B = # 5 (8) is obtained, and the variables A and B are determined. Therefore, when these are combined, 3 * 5-8 ≧ 8 (9) is obtained as the branching condition.

In step d10 in FIG. 8, in this way, step d9
The branch condition obtained in step 1 is shown in FIG.
Remember. In this way, the program to be analyzed is moved backward from the branch instruction, and the processing for obtaining the branch condition is completed.

Further, in the program example of Table 4, the process for obtaining the execution content is obtained by starting the reverse ascending analysis path obtained at step d8 in FIG. 8 from the ST instruction at line number 10, for example. The first analysis path obtained is the line number 10 → 9 → 3 → 2 → 1 as described above. When the execution contents are combined by a technique similar to the method of combining the branch conditions along this path, [PORT1 + 0] + 1 → [PORT1 + 0] (10) [PORT1] indicates the data stored in the address PORT1. .

Is obtained. For example, [PORT1 + 0] +1 → [PORT1 +
0] is executed (a condition in which the programs are executed in such an order that such execution contents are combined, that is, a condition that appears when the program is traced in such an order that such execution contents are combined). When the composition condition of the branch condition of the branch instruction is branched at branch A, branched at branch B, and not branched at branch C, or if branched at branch A and not at branch B, then at branch C. If it is, then if branching with branch X is represented by X and branching with branch X is not represented, then the above condition becomes A and B and / or A and and.・ Simplified proposition that [PORT1 + 0] + 1 → [PORT1 + 0] is executed when "branch A and not branch C" can be simplified as + A ... = A. Can be obtained.

That is, a process of storing again the contents of the address obtained by adding the preset data 0 to the address PORT1 and the data 1 at the same address, that is, a process of incrementing the data of the address PORT1 by +1.

The other analysis routes are line numbers 10 → 9 → 8 → 7 → 6. When the execution contents are combined along this path, [PORT2 + 0] + 1 + 1 → [PORT2 + 0] (11) as in the previous case, and it is understood that this is a process of incrementing the data of the address PORT2 by two. Such execution content data is stored in the execution content file storage unit 17 shown in FIG.

According to the present embodiment as described above, Tables 2 to 4 above
Since each data in the branch source column and each data constituting the attribute column shown in FIG. 5 to FIG. 7 is set prior to the reverse uplink analysis processing, the program is executed during the reverse uplink analysis. It is possible to prevent a situation in which useless processing is performed by selecting an undesired reverse uplink analysis path inconsistent with the order.

Further, in this embodiment, like the subroutine program A of the line numbers 9 to 11 in the program example shown in Table 2, the CALL instruction of the line number 3 is called and the CA of the line number 6 is called.
In the instruction sequence that is executed again by calling the subroutine program B called by the LL instruction,
Attribute data for identifying an analysis path is set for each of a plurality of branch instructions.

Therefore, when performing reverse ascending analysis processing from such a subroutine program, it is possible to set the analysis path according to the call location of the CALL instruction, etc., and prevent the situation where an incorrect analysis path is set. You can

The forward drop flag in the attribute column of Table 4 will be described below.

FIG. 15 is a flow chart showing a program example for explaining the reason why the forward-downward flag is used, and FIG.
It is a figure explaining the memory content of the stack 36 used at the time of execution of the illustrated program. If the subroutine program is called during execution of the main routine program, the 16th
As shown in FIG. 1A, the stack 36 stores the return address and the stack pointer is incremented by +1.
The processing shifts to, for example, the subroutine program shown in FIG.

In the subroutine program of FIG. 15, step r1
When the push instruction PSH for writing new address data to the stack 36 is executed, the stack 36 is loaded into the stack 36 as shown in FIG. 16 (2).
As shown, address data is written and the stack pointer is incremented by +1. After that, when the processing proceeds to steps r2, r3, r4, r5, the stack 36 is read by the pull instruction PULL that reads out the latest written address data from the stack 36 and decrements the stack pointer by -1. As shown in FIG. 3C, the address data is erased and only the return address remains.

It is assumed that the subroutine program as shown in the fifteenth example is intended to check whether or not the stack operation instruction PSH and the stack operation instruction PULL are paired one by one in a single subroutine program. At this time, in the reverse uplink processing, there are the following three types of routes.

Line numbers R7, R6 (12) Line numbers R7, R6, R2, R1 (13) Line numbers R7, R5, R4, R3, R2, R1 (14) Therefore, when the inspection is performed, the route of the twelfth formula is also inspected, and a useless inspection having no relation to the stack operation command is performed. Therefore, in the case of performing the inspection as described above, the method of reading the instruction in the order of execution of the program and performing the inspection is advantageous in that unnecessary processing is omitted.

Therefore, in this embodiment, the forward-downward flag is set in the attribute column of Table 4. As described above, the forward drop flag is a flag for identifying whether or not a certain instruction is a sequential instruction in the execution order with the instruction of the next line number. By using this forward-downward flag in the same manner as the reverse-upward flag described in the above embodiment, it is possible to read and analyze the program to be analyzed along the forward-downward path. As a result, wasteful processing is omitted, and the processing speed and efficiency can be increased.

In the program example of Table 4 above, when a plurality of CALL instructions are arranged for the subroutine program A,
The branch source column and the attribute column in the table are set as many as the number of CALL instructions. If such a subroutine program does not change the contents of the stack in it, the execution contents are the same even if called by different CALL instructions. In such a case, the branch source column and attribute column It is possible to reduce the amount of memory allocated to.

An operation example of this embodiment will be described along with a program example shown in Table 5 below.

The data in the branch source column and the attribute column in Table 5 above are set based on the data setting method described with reference to Table 4 above. As described above, in order to reduce the memory capacity allocated to the branch source column and the attribute column, the branch source column and the attribute column as shown in Table 6 below are created based on the program example of Table 5. To do.

In Tables 5 and 6 above, the underlined data has been changed. That is, the CALL instruction at line number 3, the instruction sequence at line numbers 8 to 10 branched from this, and the return instruction RE
The determination of the branch source column and the attribute column for the line number 4 further branched by T is set in the same manner as in Table 5 above. When the line number 6 is continuously read, the process branches to the line number 8.

In the example of Table 4, new branch source column 2 and attribute column 2 are set, but since this embodiment analyzes the same subroutine program, such branch source column and attribute column are not increased, In line number 8 of branch source column 1, line number data NO = “0” is set, and line number 4 attribute data fr =
Set it to "0". Furthermore, the attribute column of line number to =
Set it to "0". By using such data “0”,
It indicates that the analysis of the subroutine program of line numbers 8 to 10 based on the CALL instruction of line number 6 has been completed.

At this time, similarly in the attribute column, the line numbers 1 → 2 → 3 → 8 → 9
At the stage when the analysis of → 10 → 4 → 5 is completed, the data like the attribute column 1 in Table 5 is set, but the attribute column 2 is expanded by the processing as described above after the line number 6. No, No. 6
Data such as the attribute column 1 in the table is set.

When the line number data NO in the branch source column 1 of the line number 8 is referred to during the reverse processing, since this is "0", the branch source line number becomes unknown. Therefore, in the process of creating the branch source column and the attribute column described above, the next line number when the line number of the branch source instruction branching to the line number 8 is reversed, that is, the line number 5 in the example of Table 5 is used. , 2 are stored in the memory of the first in last out (FILO) type. Therefore, when the data of the line number data “0” is referred to in the branch source column during the reverse ascending analysis, the data is read from the FILO type memory storing the line number and the branch preceding in the reverse ascending process is performed. Number.

By doing so, the flow control file storage
In 12, the capacity of the memory allocated to the branch source column and the attribute column can be reduced.

The execution contents in the program example of Table 4 above are line numbers.
It is known that the memory contents of the stack, which are changed by a branch instruction such as 3, 5, 11 or an instruction for manipulating the contents of the stack, are greatly affected. It is convenient to analyze the program if the contents of such a stack are collected in advance as data in the attribute column. In particular, row number 5 in table 4 above
If an instruction that changes the contents of the stack is included, such as the PSH instruction and the PULL instruction that forms a pair with it, the change in the execution state of the program becomes clear and the program analysis path can be easily specified. .

In the same program example as in Table 4 above, description will be given assuming that an address as shown in Table 7 below is set for each instruction of the program.

In the present embodiment, the data in the branch source column and the attribute column use the data in Table 4, but in addition to this, when there is an instruction that changes the contents of the stack, the contents of the stack changed by the instruction are treated as data. A column for stack data VAL is provided. According to this, the line is branched to the line number 9 at the line number 3, but at this time, the data # F007 is stored in the stack.
Therefore, in the VAL column of line numbers 9 to 11, data obtained by converting the upper byte and the lower byte of the address # F007 is converted.
VAL = "07F0" is set respectively.

The process returns from the line number 11 to the line number 4, and then at line number 5, the contents of the stack are changed to the address # F000 of the line number 1. Therefore, stack data VAL = "00F0" is set in the attribute column 1 of the line numbers 4 to 8 thereafter. At line number 8, a new attribute column 2 is set,
Subsequently, stack data VAL = "00F0" is set.

As described above, according to the present embodiment, since the stack data is set in the attribute column, for example, when performing the reverse processing from the return instruction RET of the subroutine instruction to the main routine, The return destination is known by referring to the stack data VAL, and it is possible to eliminate the need to sequentially analyze and detect each instruction in reverse order. This speeds up the processing. Further, the use of the stack data VAL makes it much easier to identify the attributes such as the type of attribute and the processing route set for each instruction.

In step d9 in FIG. 8, the branch condition is synthesized and the obtained result is converted from the flow chart creating means 19 and the execution content analysis result output means 20 shown in FIG. When outputting in the form of PAD diagram or printing out the execution contents, the longer the analyzed program becomes, the larger the output amount becomes. Therefore, it is necessary to have a technique for organizing the outputs described by these logical expressions into a simple form using Boolean algebra.

FIG. 17 is a flow chart for explaining such an embodiment. The output from the flow chart creating means 19 and the execution content analysis result output means 20 is, for example, the following formula: F = C · (+ (A · B)) + (· (+ AB) + A ·
) Is given as a logical expression in which logical symbols are combined, the following processing is performed to reduce it. The basic policy of this reduction processing is the following 16th and 17th equations.

A + = U (16) A + · g = A + g (17) U; Overall set A; Subset of U; Complement of A g; Unary ・; Logical AND operation +; Logical OR operation Fig. 18 above FIG. 16 is a Venn diagram for explaining the contents of Expression 16 and Expression 17. The above 16th expression means that in the universal set U, the union of the subset A and its complement is always the universal set. Further, the above 17th expression means that if the subset A and the unary g are disjoint, the intersection of the complement and the unary g and the set A are the union of the set A and the unary g. .

Based on the basic schemes of the 16th and 17th equations, the procedure for simplifying the 15th equation will be described with reference to the flow chart of FIG. In FIG. 17, step s1, each term is decomposed. As a result, Equation 15 above becomes
It is changed to 18 formulas.

F = C ・ + C ・ A ・ B + ・ + ・ A ・ B + A ・
(18) Next, it is determined in step s2 whether there is a common term.
First, it is judged that there is a common term C for the first term and the second term of the 18th equation, and the equation (19) below is obtained by being bracketed by () in step s3.

C · (+ A · B) (19) Next, in step s4, it is judged whether or not there is a combined pattern based on the 16th and 17th equations. Formula 19 ()
In the above, the composition based on the expression (17) is possible, the judgment is affirmative, the process proceeds to step s5, and the composition is made as the following expression (20). If it is determined in step s4 that there is no composite pattern, the process proceeds to step s6, and it is determined whether there is another identical term that is enclosed in (). If not, the process proceeds to step s3. In the example of the following expression 20, there is no more combined pattern in (), the process is returned to step s1, and () is decomposed to obtain the following expression 21.

C · (+ B) (20) C · + CB (21) Next, regarding the first term of the 21st equation and the third term of the 18th equation, the processing of the steps s2 and s3 is applied, and the following equation 22 is applied. Is obtained.

C • + • = • (C +) (22) In the next steps s4 and s5, the basic policy of the above-mentioned expression 16 is applied, and the following expression 23 is obtained.

(C +) = ... (23) Next, similar processing is performed on the second term of the 21st equation and the fourth term of the 18th equation, and the result of the following 24th equation is obtained.

C ・ B + ・ A ・ B = B ・ (+ C ・ A) = BC + BA ...
(24) Next, similar processing is performed between the second term on the rightmost side of the 24th equation and the 5th term of the 18th equation, and the following 25th equation is obtained.

B · A + A · = A · (B +) = A (25) Accordingly, the following formula 26 is obtained from formula 23, formula 24, the first term on the rightmost side, and formula 25.

+ B · C + A = B · C + U = U (26) In this way, based on the basic method shown in the 16th and 17th equations, the logic shown in the 15th equation based on the processing procedure shown in FIG. It was confirmed that the formula was reduced to the universal set U. In this way, in performing the processing of synthesizing the branch condition in step d9 in FIG. 8, the logical expression is simplified by the logical operation using the Boolean algebra as described above. Thereby, the flow chart creating means 19 creates and outputs the flow chart, or the execution content analysis result outputting means.
When the execution contents are printed out as a logical expression in 20, the execution contents can be expressed in a format that makes it easier to grasp the contents, and the program content analysis device of this case is used for debugging the program. Very efficient in case.

EFFECTS OF THE INVENTION As described above, according to the present invention, in displaying the condition for executing the predetermined execution content, a complicated display can be easily transformed and displayed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the analysis apparatus 1, and FIG. 2 is a flow chart for explaining the operation of the analysis preparation processing means 5.
3 is a flow chart showing the flow of the operation of the analyzed program example, FIG. 4 is a flow chart explaining the operation of the flow structure analysis means 11, and FIG. 5 is a flow control file storage unit 12.
6 shows the structure of the branch source file storage unit 21, FIG. 7 shows the structure of the attribute file storage unit 22, and FIG. 8 shows the operation of the branch condition analysis means 13. FIG. 9 is a flow chart for explaining the reverse flow flag of this embodiment, FIG. 10 is a flow chart for explaining the reverse flow determination in the reverse flow processing, and FIG. 11 is a data setting process for the reverse flow processing. Float Chart, No. 12
FIG. 13 is a flow chart for explaining the reverse uplink branch processing of the reverse uplink processing, FIG. 13 is a flow chart for explaining the operation of the unanalyzed route processing of the reverse uplink processing, and FIG. 14 is a flow chart for explaining the data write processing. FIG. 15 is a flow chart for explaining the operation flow of the analyzed program example, FIG. 16 is a diagram for explaining the state of the stack, FIG. 17 is a flow chart for explaining the simplification process using the Boolean algebra of the logical expression, and FIG. FIG. 18 is a Venn diagram for explaining the present embodiment, and FIG. 19 is a flow chart showing the flow of a program example. 1 ... Analysis device, 3 ... Assembler, 4 ... Assemble list file storage unit, 5 ... Analysis preparation processing means, 6 ...
… List file storage unit, 10 …… Instruction data file storage unit, 11 …… Flow structure analysis means, 12 …… Flow control file storage unit, 13 …… Branch condition analysis unit, 16 …… Branch condition file storage unit, 21 ...... Branch source file part, 22 ...... Attribute file part, 23 ...... Attribute source number storage part, 24 ...... Branch source column storage part, 25 ...... Line number storage part, 26 ...... Branch source attribute storage part,
27 ... Branch destination attribute storage unit, 28 ... Attribute number storage unit, 29 ...
… Indeterminate flag memory, 30 …… Attribute value memory

Claims (1)

[Claims] 1. An instruction of a program consisting of a plurality of instructions is read in the reverse order of the arrangement order, and the contents are analyzed,
In an apparatus that outputs each execution content and a condition under which the execution content is performed, a reading unit that reverses a program to read the execution content of each instruction, and a path to an instruction related to the execution content among the read instructions. The first logical expression information corresponding to the condition for passing is obtained, and the first logical expression information for all the paths related to the execution content is combined as comprehensive logical expression information in a logical sum form, and the comprehensive logical expression information is obtained. Execution content storage means for storing in relation to the execution content, decomposing means for transforming given logical expression information into a form of logical sum of logical products and outputting, logical expression information given by the decomposing means , The first same-arrangement means for transforming and outputting the terms related to the same term in parentheses, and for the given logical expression information, the terms related to the same term are parenthesized. It is transformed into an output format and output. A second same term organizing means, among the logical expression information given from the first same paragraph arranging unit,
Pattern transformation means for transforming and outputting a term corresponding to a predetermined transformation pattern according to the predetermined transformation pattern, and execution contents for displaying logical expression information given by the pattern transformation means and its execution contents in association with each other. It is provided between the output means and the first identical term organizing means and the pattern transforming means, and detects whether or not the predetermined pattern is included in the logical expression information given from the first identical term organizing means, If the predetermined pattern is included, logical formula information is output to the pattern synthesizing unit; if not, the first selecting unit that outputs logical formula information to the decomposing unit; the pattern transforming unit and execution content output. Means for determining whether or not the same term is included in the logical expression information provided from the pattern transforming means, and if the same term is included, the second same term organizing means. Program content analysis, characterized by further comprising: second selection means for giving logical expression information to the first selecting means via the above, and for giving logical expression information to the execution content output means if the same term is not included. apparatus.