JPH0775008B2 - Cache memory - Google Patents

Description

TECHNICAL FIELD The present invention relates to a cache memory.

[Conventional technology]

The operation speed of the main memory is slower than the operation speed of the CPU. In order to improve the operation efficiency of the CPU, a method of storing data read from the main memory in a cache memory that can operate at high speed and reading the data from the cache memory when rereading the data is generally used.

Figure 8 shows the magazine "Interface" published by CQ Publisher 19
FIG. 9 is a block configuration diagram of a cache memory taken out for explanation of only one way of a 4-way set associative cache memory described on page 250 of the September 1987 issue.

In the figure, 1 is an address signal for accessing the cache memory, 2 is a tag address which is a part of the address signal 1, 3 is an entry address which is a part of 1 of the address signal, 4 is the address signal 1 Part of the word address, 5 is a tag address memory that holds the tag address in the cache memory, and 6 is a valid bit memory that indicates whether the data held in the data memory 7 is valid or invalid. Is. When the valid bit is H, the data is valid, and when the valid bit is L, the valid bit is invalid.
Reference numeral 7 is a data memory for holding the data in the cache memory, 8 is a comparator for comparing the tag address 2 and the tag address held in the tag address memory 5 and checking whether or not they match, 9 is a The word address 4
A word selector for selecting one word from the data memory, 10 a control circuit controlled by a valid bit and the word address 4, 11 a HIT signal output from the control circuit 10, 12 an output from the word selector 11. Data signal, 13 is a decoder for the entry address 3, 14 is a decode signal output from the decoder 13, 15
Is a MISS signal.

Next, the read operation of the conventional cache memory will be described. In this example, the word address is set to 1 for convenience of explanation.
It is assumed that the bits, the end address are 2 bits, and the tag address is 3 bits. When the address signal 1 is given from the outside, the contents of the tag address memory 5 selected by the entry address 3 and the decoder 13 are sent to the comparator 8 and the contents of the data memory 7 are also sent to the word selector 9, and the word data is sent at the word address 4. Choose. In this example, two word data correspond to one entry address.
Then, the comparator 8 checks whether or not the content of the selected tag address memory 5 matches the tag address 2,
The result is sent to the control circuit 10. In this example, each of two word data corresponding to one entry address is valid,
It has 2 valid bits to indicate invalidity.

In the control circuit 10, when the value of the valid bit corresponding to the word data selected by the word address 4 is H and the data specified by the external address is in the cache memory, the HIT signal 11 is sent at a predetermined timing. Occur. The HIT signal 11 is sent to the outside of the cache memory and the word selector 9, and when the HIT signal 11 is H, the data is output to the data signal 12. When a cache miss occurs, the MISS signal 15 is set to H, the main memory outside the cache memory is activated to read the data, the data is sent to the MPU, and the data is stored in the data memory 7 in the cache memory.

Next, the write operation of the conventional cache memory will be described. When the address signal 1 is externally applied, the address hit judgment is performed as in the read operation, and the HIT signal 11
Is H, the value of the data signal 12 is written in the data memory 7. When the HIT signal 11 is L, nothing is done.

[Problems to be Solved by the Invention]

In the conventional cache memory, since the timing of the HIT signal 11 that is output at the time of a read hit is fixed, the hit determination time increases when the cache memory is used at a low power supply voltage or high temperature, and the HIT signal 11 that has an incorrect determination result is generated. There was a problem that was output to the CPU.

Further, in the conventional cache memory, if the operating frequency of the cache memory is increased, the time that can be used for hit determination in the cache memory decreases, so the HIT signal 11 with an incorrect determination result is output to the CPU. There was a problem.

The present invention has been made to solve the above problems, and an object thereof is to obtain a general-purpose cache memory that can be used in a wider environment.

[Means for Solving the Problems]

The cache memory according to the present invention includes a circuit for delaying the activation signal of the cache memory and a circuit for changing the output timing of the signal indicating the cache hit.

Further, the cache memory according to the present invention includes a circuit for delaying the activation signal of the cache memory and a circuit for changing the timing of accessing the external memory in the case of a cache miss.

[Action]

The cache memory according to the present invention delays the hit determination so that the correct HIT signal can be output to C without a wait cycle.
If it cannot be output to PU, it automatically inserts a wait cycle and then outputs the HIT signal.

Further, in the cache memory according to the present invention, when the hit determination is delayed, a read miss occurs, and when the external memory cannot be accessed without the wait cycle, the wait cycle is automatically inserted and then the access to the external memory is activated.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cache memory according to a first embodiment of the present invention, which is obtained by adding a timing changing circuit 20 to the circuit of the conventional example shown in FIG. 8, and the other parts have the same structure. . The timing change circuit 20 uses the HIT signal 11 and MISS
It is a circuit that changes the output timing of a signal. HIT signal 1
1 is output to the word selector 9 and the outside of the cache memory. Reference numeral 21 is a CLK1 signal which is supplied from the outside of the cache memory and indicates a clock, 22 is a CLK2 signal, 23 is a TAGHIT signal which is output from the control circuit 10 and indicates an address match, and 24 is a bus cycle which is supplied from the outside of the cache memory. The BS signal indicating the start and 25 is the READ signal indicating the read cycle given from the outside of the cache memory.

Next, the operation of the cache memory of this embodiment will be described. The write operation of the cache memory of this embodiment is similar to that of the conventional cache memory, and only the read operation is different. Therefore, the read operation will be described below. In this example, for convenience of explanation, it is assumed that the word address is 1 bit, the entry address is 2 bits, and the tag address is 3 bits.

When the address signal 1 is given from the outside, the contents of the tag address memory 5 selected by the entry address 3 and the decoder 13 are sent to the comparator 8 and the contents of the data memory 7 are also sent to the word selector 9, and the word data is sent at the word address 4. Choose. In this example, two word data correspond to one entry address. Then, the comparator 8 checks whether or not the content of the selected tag address memory 5 matches the tag address 2, and the result is checked by the control circuit 10
Send to. In this example, 2 corresponding to one entry address
It has two valid bits to indicate the validity or invalidity of each word data. In the control circuit 10,
When the value of the valid bit corresponding to the word data selected by word address 4 is H, and the data specified by the external address is in the cache memory, the TAGHIT signal 23 is generated at the predetermined timing and the timing is changed. Sent to circuit 20. The timing changing circuit 20 creates a BS delay signal 34 from the BS signal 24, determines whether or not to insert a wait cycle based on the delay state of the BS delay signal 34, and considers the wait cycle.
And MISS signal 15 are output.

The HIT signal 11 is sent to the outside of the cache memory and the word selector 9, and when the HIT signal 11 is H, it outputs the data to the data signal 12. When a cache miss occurs, the MISS signal 15 is set to H, the main memory outside the cache memory is activated to read the data, the data is sent to the MPU, and the data is stored in the data memory 7 in the cache memory.

Next, a configuration example of the timing changing circuit will be described with reference to FIG. In the figure, 21 is a CLK1 signal, 22 is a CLK2 signal, 23 is a TAGHIT signal, 24 is a BS signal, 25 is a READ signal, 30 is a delay circuit, 31 is a 3-input AND gate, and 32 and 33 are D latches. D-latch 32 and D-latch 33 are composed of N-channel transmission gates 40 and 41 and inverter gates 42 and 43. The N channel transmission gate 40 of the D latch 32 is controlled by the CLK2 signal 22,
The N-channel transmission gate 41 is controlled by the CLK1 signal 21. The N-channel transmission gate 40 of the D latch 33 is controlled by the CLK1 signal 21, and the N-channel transmission gate 41 of the D latch 33 is controlled by the CLK2 signal 22. Reference numeral 35 is an inverter gate.

FIG. 3 is a circuit example of the delay circuit 30 shown in FIG. In the figure, 50 is an inverter gate, 51 is a load capacitance, and 52 is
It is GND. In this circuit example, four inverter gates 50
Then, the BS signal 24 is delayed by the four load capacitors 51 to create a BS delay signal 34. The delay obtained with this circuit is
The capacity value of the load capacity 51 is set so as to be a value slightly larger than the time required for hit determination in the cache memory. The delay circuit shown here is an example, and there is no problem even if the circuit configuration is different as long as the delay obtained is a value slightly larger than the time required for hit determination in the cache memory.

Next, the operation of the timing changing circuit of FIG. 2 will be described with reference to FIGS. 4 to 7 which are timing charts of the timing changing circuit.

First, FIG. 4, which is a timing chart of the 0-wait read bit, will be described. In the figure, 21 is CLK1 signal, 22 is CLK2
In terms of signals, these signals are two-phase clocks with key overlap. In this example, one clock cycle is called one machine cycle. The state of the cache memory is described every machine cycle.

Figure 4 consists of SCMP and SHIT states. SCMP
Is a state for comparing addresses, and is a state for setting the HIT signal 11 to H level by SHIT. The read signal 25 is a signal which becomes H level during read access and becomes L level during write access. The BS signal 24 is a signal indicating the start of a bus cycle, and is at H level during SCMP. In order to clearly show the operation, the states of points A to D in FIG. 2 are also shown. Fourth
In the read hit state in the figure, both the TAGHIT signal 23 and the BS delay signal 34 change from the L level to the H level by the end of the SCMP cycle. Therefore, by the end of the SCMP cycle, point A becomes H level, point B becomes L level, and HIT signal 11 becomes H level in SHIT cycle. At this time, point C is at L level, point D is at H level, and MISS signal 15 is at L level.

Next, FIG. 5, which is a timing chart of 0-wait read miss, will be described. Figure 5 consists of SCMP and SMISS states. SCMP is a state for comparing addresses, and SMISS is a state for setting the MISS signal 15 to H level.

In the read miss state of FIG. 5, the TAGHIT signal 23 is at L level, the A point is at L level, the B point is at H level, and the HIT signal 11 is at L level.
Keep the level. By the end of the SCMP cycle, the BS delay signal 34 changes from the L level to the H level. Therefore, C point becomes H level by the end of SCMP cycle and MI
The SS signal 15 becomes H level in the SMISS cycle, the point D becomes L level, and the MISS signal 15 becomes H level in the SMISS cycle. The external memory is accessed by setting the MISS signal 15 to H level. There are many kinds of methods for accessing the external memory, and since they are not related to the present invention, they will not be described.

Next, refer to FIG. 6, which is a timing chart of 1-wait read hit. Figure 6 shows SCMP, SWAIT and SHIT
It consists of states. SCMP is a state to compare addresses, SWAIT is a wait state, SHIT is HIT
This is a state in which the signal 11 is set to the H level. In the read hit state of FIG. 6, both the TAGHIT signal 23 and the BS delay signal 34 change from the L level to the H level after the end of the SCMP cycle. Therefore, in the next cycle of the SCMP cycle, point A becomes H level, point B becomes L level, and HIT signal 11
Goes high in the SHIT cycle. At this time, point C is L
Level, D point is H level, MISS signal 15 is L level.

In this way, when the TAGHIT signal 23 and the BS delay signal 34 are delayed, a wait cycle is automatically inserted, and then the HIT signal 11 becomes H level.

Next, FIG. 7 which is a timing chart of 1-wait read miss will be described. Figure 7 shows SCMP and SWAIT
And SMISS states. SCMP is a state for comparing addresses, SWAIT is a wait state, S
MISS is a state in which the MISS signal 15 is set to H level. In the read miss state of FIG. 7, the TAGHIT signal 23 is at L level,
The A point is at the L level, the B point is at the H level, and the HIT signal 11 is at the L level. BS delay signal 34 after completion of SCMP cycle
Changes from L level to H level. Therefore, in the next cycle of the SCMP cycle, point C becomes H level, point D becomes L level, and MISS signal 15 becomes H level in SMISS cycle. In this way, when the TAGHIT signal 23 and the BS delay signal 34 are delayed, after automatically inserting the wait cycle, the MI
The external memory is accessed by setting the SS signal 15 to the H level.

In the above embodiment, 0 wait and 1 wait access have been described, but when the BS delay signal 34 is further delayed or the clock frequency is increased, 2 wait cycles or more are automatically inserted. That is clear.

As described above, according to the present invention, when the hit determination is delayed and the correct HIT signal 11 cannot be output to the CPU without a wait cycle, the HIT is automatically inserted after the wait cycle is inserted. It outputs a signal 11 and when the hit judgment is delayed, a read miss occurs and the external memory cannot be accessed without a wait cycle, the wait cycle is automatically inserted and the external memory access is activated. It is possible to obtain a general-purpose cache memory that normally operates in a wide operating environment such as power supply voltage, high temperature, and high operating frequency.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache memory according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of the timing changing circuit shown in FIG. 1, and FIG. 3 is a delay shown in FIG. FIG. 4 is a diagram showing one configuration example of the circuit, FIGS. 4 to 7 are diagrams showing a timing chart of the timing changing circuit shown in FIG. 2, and FIG. 8 is a block configuration diagram of a conventional cache memory system. In the figure, 1 is an address, 2 is a tag address, 3 is an entry address, 4 is a word address, 5 is a tag address memory, 6 is a valid bit memory, 7 is a data memory, 8 is a comparator, 9 is a word selector, 10 Is the control circuit,
11 is a HIT signal, 12 is a data signal, 13 is a decoder, 14 is a decode signal, 15 is a MISS signal, 20 is a timing change circuit,
Reference numeral 24 is a BS signal, 30 is a delay circuit for a cache memory activation signal, and 34 is a BS delay signal. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A circuit for delaying a start signal of a cache memory, and a circuit for changing an output timing of a signal indicating a cache hit according to a delay of a cache hit determination detected by using the delay signal. A cache memory characterized by that. 2. A circuit for delaying a start signal of a cache memory, and a circuit for changing a timing of accessing an external memory at a cache miss according to a delay of a cache hit determination detected by using the delay signal. A cache memory characterized by that.