JPH0775300B2 - Delay circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a delay circuit suitable for IC implementation.

(Prior Art) FIG. 6 is a block diagram of a conventional delay circuit suitable for use as an IC, and FIG. 7 is a circuit diagram showing a specific example of the delay circuit.

The delay circuit having the biquad configuration shown in FIGS. 6 and 7.
100 is a differential amplifier circuit 101 in the first stage, a differential amplifier circuit 10 in the latter stage
2, an inverting amplifier circuit 103, buffer circuits 104 and 105, and capacitors 106 and 107 connected to the output terminals of the differential amplifier circuits 101 and 102, respectively.

The input signal applied to the input terminal IN passes through the non-inverting input terminal 101a of the differential amplifier circuit 101 at the first stage, the input terminal 103a of the inverting amplifier circuit 103, and the capacitor 107, and the differential amplifier circuit 102 at the subsequent stage.
Is applied to the output terminal 102c of. First stage differential amplifier circuit 101
The output terminal 101c of is connected to the output terminal 103b of the inverting amplifier circuit 103 via the capacitor 106, and the differential amplifier circuit of the first stage is connected.
The output signal of 101 is applied to the non-inverting input terminal 102a of the differential amplifier circuit 102 at the subsequent stage via the buffer circuit 104. The output of the differential amplifier circuit 102 at the subsequent stage is applied to the inverting input terminal 101b of the differential amplifier circuit 101 at the initial stage and the inverting input terminal 102b of the differential amplifier circuit 102 at the subsequent stage via the buffer circuit 105. .

In the above configuration, the input signal applied to the input terminal IN
VI, output signal of output terminal OUT is V0, first stage differential amplifier circuit 1
The transconductance of 01 is 1 / r1, the differential amplifier circuit of the latter stage 10
The conductance of 2 is 1 / r2 and the gain of the inverting amplifier circuit is −
A, and the capacitance values of the capacitors 106 and 107 are C1 and C2, respectively,
The output signal V0 of this delay circuit 100 is And the transfer function V0 / VI is Therefore, when the gain of the inverting amplifier circuit 103 is 1 (OdB), it becomes a secondary phase shift circuit. Then, the mutual conductance of each differential amplifier circuit 101, 102 is set to 1 / r1, 1 / r2, and the capacitance value C1,
The desired characteristics can be obtained by selecting C2.

As shown in FIG. 7, each of the differential amplifier circuits 101 and 102 and the inverting amplifier circuit 103 is connected between the emitters of a pair of transistors Q1, Q2, Q3, Q4, Q5, Q6 to which a predetermined bias current is supplied. This is a configuration in which the emitters are connected by resistors.

Here, each NPN transistor Q that constitutes the inverting amplifier circuit 103
If the emitter resistances of 1 and Q2 are re1 and re2, the collector load resistance of the transistor Q1 is RC, and the resistance between the emitters of the transistor Q1 is RE, the gain −A of the inverting amplifier circuit 103 is expressed by the following equation.

-A = -RC / (re1 + re2 + RE) Similarly, for the first-stage differential amplifier circuit 102, if the emitter resistance of each NPN transistor Q3, Q4 is re3, re4 and the emitter resistance is R1, the first-stage differential amplifier The transconductance 1 / r1 of the amplifier circuit 102 is Becomes

Also in the differential amplifier circuit 102 in the subsequent stage, if the emitter resistances of the NPN transistors Q5 and Q6 are re5 and re6 and the resistance between the emitters is R2, the mutual conductance 1 / r2 of the differential amplifier circuit 103 in the first stage is 1 / r2. Is Becomes

The emitter resistance re of each transistor Q1 to Q6 is Given in. Here, k is the Boltzmann constant, q is the elementary charge, T is the absolute temperature, and Ie is the emitter current of the transistors Q1 to Q6.

(Problems to be Solved by the Invention) As described above, the delay circuit 100 according to the related art includes the inverting amplifier circuit 1
It is necessary to set the gain A of 03 to OdB. In the process of manufacturing the IC, the ratio of the collector load resistance RC and the emitter resistance RE can be accurately realized, but since the emitter resistances re1 and re2 of the transistors Q1 and Q2 are involved in the gain A, the inverting amplifier circuit 103 It is difficult to accurately adjust the gain A of O to OdB.

In addition, a slight phase delay occurs between the input and output of the inverting amplifier circuit 103.

Therefore, the desired amplitude characteristic and phase characteristic may not be obtained.

The present invention has been made to solve such a problem, and an object thereof is to provide a delay circuit which has a simple circuit configuration without providing an inverting amplifier circuit and has excellent transfer characteristics.

(Means for Solving the Problems) In order to solve the above problems, a delay circuit according to the present invention includes a differential amplifier circuit at a first stage, a differential amplifier circuit at a rear stage having two inverting inputs, and each differential amplifier circuit. And a load capacitance connected to the output terminal of the input signal, the input signal to the non-inverting input terminal of the differential amplifier circuit of the first stage, one inverting input terminal of the differential amplifier circuit of the latter stage, the load capacitance of the differential amplifier circuit of the latter stage Applied to one end of the differential amplifier circuit, and the signal based on the output signal of the differential amplifier circuit in the first stage is input to the non-inverting input terminal of the differential amplifier circuit in the subsequent stage.
It is characterized in that the output of the differential amplifier circuit at the subsequent stage is applied to the inverting input terminal of the differential amplifier circuit at the first stage and the other inverting input terminal of the differential amplifier circuit at the subsequent stage, respectively.

(Operation) An output signal delayed with respect to the input signal is output from the output terminal of the operation amplification circuit in the subsequent stage.

(Embodiment) An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a delay circuit according to the present invention.

The delay circuit 1 includes a first stage differential amplifier circuit 2, a load capacitor 3 of the first stage differential amplifier circuit 2, a buffer circuit 4, a rear stage differential amplifier circuit 5, a capacitor 6, and a buffer circuit 7. The differential amplifier circuit 5 in the subsequent stage includes one non-inverting input terminal 5a and two inverting input terminals 5b and 5c.

The input signal VI input to the input terminal IN is applied to the non-inverting input terminal 2a of the differential amplifier circuit 2 in the first stage and one inverting input terminal 5b of the differential amplifier circuit 5 in the subsequent stage, and the capacitance 6 Is connected to the output terminal 5d of the differential amplifier circuit 5 in the subsequent stage via. The output 2c of the differential amplifier circuit 2 in the first stage is applied to the input terminal 4a of the buffer circuit 4 having a high input impedance, and the output 4b of the buffer circuit 4 is applied to the non-inverting input terminal 5a of the differential amplifier circuit 5 in the subsequent stage. It If the input impedance of the differential amplifier circuit 5 in the subsequent stage is sufficiently high, the buffer circuit 4 can be omitted. The output 5d of the differential amplifier circuit 5 at the subsequent stage is applied to the input terminal 7a of the buffer circuit 7 having a high input impedance, the output 7b of the buffer circuit 7 is connected to the output terminal OUT, and this output signal V0 is applied to the differential signal at the first stage. It is applied to the inverting input terminal 2b of the dynamic amplifier circuit 2 and the other inverting input terminal 5c of the differential amplifier circuit 5 at the subsequent stage. If the load connected to the output terminal OUT has a sufficiently high impedance, the buffer circuit 7 can be omitted.

In the above configuration, the mutual conductance of the first stage differential amplifier circuit 2 is 1 / r1, the mutual conductance of the second stage differential amplifier circuit 5 is 1 / r2, and the capacitance values of the capacitors 3 and 6 are C1 and C2, respectively. For example, the output signal V0 is The transfer function of the delay circuit 1 can be expressed by the following equation.

FIG. 2 is a block diagram showing another embodiment of the delay circuit.

This delay circuit 11 outputs the output of the buffer circuit 4 of the delay circuit 1 shown in FIG. 1 through an amplifier circuit 12 having a voltage gain of 6 dB,
The configuration is such that the voltage is applied to the non-inverting input terminal 5a of the differential amplifier circuit 5 in the subsequent stage.

The output signal V0 of this delay circuit 11 is And the transfer function can be expressed by the following equation.

FIG. 3 is a circuit configuration diagram showing a specific example of the delay circuit shown in FIG.

Here, each transistor that constitutes the first stage differential amplifier circuit 2
The emitter resistances of Q1 and Q2 are re1 and re2, the resistance between the emitters of the transistors Q1 and Q2 is R1, and the emitter resistances of the transistors Q3, Q4, and Q5 that make up the differential amplifier circuit 5 in the subsequent stage are re3 and re3, respectively. , re4, re5, the resistance R2 between the emitters of the transistors Q3 and Q4, and the resistance R3 between the emitters of the transistors Q3 and Q5, the transfer function of the delay circuit 11 shown in FIG. It can be represented by 1).

If this delay circuit 11 is realized by an IC, the resistance values R2, R3
The relative accuracy of is high, so R2 = R3. Further, since the currents supplied from the respective current sources can be made equal, the emitter resistances of the respective transistors Q1 and Q2 forming the differential amplifier circuit 2 in the first stage are re1 = re2, and similarly, the differential amplifier circuit in the latter stage is similar. The emitter resistance of each of the transistors Q3, Q4, and Q5 constituting the circuit 5 is re3 = re4 = re5. Therefore, the equation (1) can be expressed as the equation (2).

Therefore, the differential amplifier circuit 5 in the subsequent stage shown in FIG.
It has a configuration including an amplifier circuit 12 having a voltage gain of 6 dB shown in FIG.

As described above, the delay circuits 1 and 11 according to the present invention are
Since it is composed of two differential amplifier circuits 2 and 5 and two capacitors 3 and 6, the inverting amplifier circuit that was required in the conventional delay circuit is unnecessary, the circuit configuration is simple, and the chip when integrated into an IC The area becomes smaller. Furthermore, by just adjusting the relative accuracy of the two emitter resistors R2 and R3 that determine the transconductance 1 / r2 of the differential amplifier circuit 5 in the subsequent stage of the three inputs, the gain and the phase shift of the inverting amplifier circuit described above can be obtained. It is possible to prevent the deterioration of the delay characteristics that accompanies this.

FIG. 4 is a circuit configuration diagram showing an application example of the present invention.

The delay circuit 20 shown in FIG. 4 corresponds to the delay circuit 11 shown in FIG.
Are connected in cascade to obtain a large delay time. Each of the delay circuits 21, 22, 2 in the first stage, the middle stage, and the latter stage
3 and a bias circuit 24 that regulates the bias currents of the delay circuits 21, 22, and 23. In this application example, the total delay time is 500 nanoseconds (nsec)
It realizes the characteristics of.

FIG. 5 is a graph showing frequency characteristics of delay time of the delay circuit shown in FIG.

In FIG. 5, (a), (b), and (c) show the individual characteristics of the delay circuits 21, 22, and 23 of the first, middle, and second stages, respectively, and FIG. 5 (d) shows the overall characteristics.

(Effects of the Invention) As described above, the delay circuit according to the present invention serves as a load for two differential amplifier circuits and each differential amplifier circuit.
Since it is configured with two capacitors, especially the differential amplifier circuit in the subsequent stage is configured to have two inverting input terminals and one non-inverting input terminal, the inverting amplifier circuit itself required for the conventional delay circuit is unnecessary. Further, there is an effect that the phase amplitude characteristic, which has been caused by the variation in the gain of the inverting amplifier circuit, can be improved with a simple configuration.

[Brief description of drawings]

1 is a block diagram of a delay circuit according to the present invention, FIG. 2 is a block diagram of a delay circuit showing another embodiment, FIG. 3 is a circuit diagram of the delay circuit shown in FIG. FIG. 4 is a circuit diagram of a delay circuit showing an application example of the present invention, FIG. 5 is a graph showing delay time-frequency characteristics of the delay circuit shown in FIG. 4, and FIG. 6 is a block diagram of a conventional delay circuit. , 7th
The figure is a circuit diagram of a conventional delay circuit. 1,11,20,21,22,23 ... Delay circuit, 2 ... First stage differential amplifier circuit, 3,6 ... Capacitance, 5 ... Later stage differential amplifier circuit, VI ... Input signal, V0 ... Output signal.

Claims (1)

[Claims] 1. A first stage differential amplifier circuit having an inverting input terminal and a non-inverting input terminal and having a load capacitor connected to an output terminal, and two inverting input terminals and one non-inverting input terminal. And an output terminal and one of the inverting input terminals through a capacitor, and a differential amplifier circuit in the subsequent stage, and the input signal is applied to the non-inverting input terminal of the differential amplifier circuit in the first stage and one of the differential amplifier circuits in the subsequent stages. To the inverting input terminal of the first-stage differential amplifier circuit and the other inverting input terminal of the latter-stage differential amplifier circuit to apply the output of the latter-stage differential amplifier circuit to the first-stage differential amplifier. The output signal of the circuit or a signal based on this output signal is applied to the non-inverting input terminal of the differential amplifier circuit in the subsequent stage, and the output signal delayed with respect to the input signal is output from the output terminal of the differential amplifier circuit in the subsequent stage. Configured to Delay circuit, characterized in that.