JPH0775340B2 - Digital signal multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in a digital communication device. The present invention is
The present invention relates to a digital signal multiplexer for multiplexing incoming n × m (n and m are natural numbers of 2 or more) low order group signal inputs into m high order group signals asynchronous with the inputs.

〔Overview〕

The present invention is a digital signal multiplexer for multiplexing low-order group signals of n × m (n and m are natural numbers) into m high-order group signals asynchronous with the input side. The frame signals necessary for multiplexing are supplied from the one frame signal source to the m multiplex converters provided in, and the phases of the frame signals do not match each other for the m multiplex converters. , A separate delay device is provided in each of the frame signal supply paths to simplify the configuration of the frame signal source and prevent intelligible crosstalk between m high-order group signals to be output. .

[Conventional technology]

The asynchronous multiplexer shown in FIG. 3 will be described as an example. The four separated DS1 signals 4-1 to 4- which are low-order group signals.
4 is two DS1C signals 7-1 and 7 which are high order group signals.
2 independent frame signals 9 when multiplexed to -2
-1 and 9-2 are asynchronously multiplexed into these DS1C signals 7-1 and 7-2. In FIG. 3, 1a and 1b are transmission-side counters that output frame signals 9-1 and 9-2, respectively, and 3a and 3b are drive circuits thereof.
-1 to 5-4 are read clocks, and 6-1 to 6-4
Is a stuff pulse.

[Problems to be solved by the invention]

In the above-described conventional asynchronous multiplexer, when the m × n low-order group signal inputs are multiplexed into the m high-order group signals, independent frame signals are supplied to the respective counter circuits (1a, 1a, Supplied from 1b). The frame signals are asynchronous with each other. Therefore, there is a drawback that the circuit scale becomes large.

It is conceivable to supply this in common from one counter circuit, and in that case the circuit scale can be made small, but if this is done, the frame phases of the m high-order group signals on the output side will be the same. If an integrated circuit is constructed with a high density, crosstalk will occur between the high-order group signals. Moreover, the crosstalk is likely to be decoded as intelligible crosstalk when it is decoded.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a digital signal multiplexing apparatus which reduces the circuit scale and simplifies the circuit configuration and prevents the crosstalk caused thereby.

[Means for solving problems]

According to the present invention, n × m (n and m are natural numbers) low-order group signals are represented by m.
In a digital signal multiplexing apparatus for multiplexing into multiple higher-order group signals, m number of frame signals branched from one main frame signal are subjected to necessary bit adjustment and then multiplexed into the respective higher-order group signals above. And

That is, in the present invention, n × m (n and m are natural numbers of 2 or more)
Low order group signal input, m multiplex converters (2), and a counter circuit (1) for supplying the multiplex converter with a frame signal (9) asynchronous with the low order group signal input. , The low-order group signals are distributed to the m multiplex converters n by n together with the stuff pulse, and a digital signal is multiplexed from each of the multiplex converters to obtain a high-order group signal asynchronous with the low-order group signal. In the multiplexer, one counter circuit is commonly provided for the m multiplex converters, and the counter circuit and the frame signal paths of the multiplex converters do not coincide in phase with each other for the m multiplex converters. It is characterized in that a delay device (8) having a different delay amount is inserted in the.

[Action]

In the device of the present invention, the frame signal (9) supplied to the plurality of multiplexers is commonly supplied from one counter circuit (15). Moreover, the frame signals are inserted into the delay devices (8) so that the phases of the respective frame signals do not coincide with each other.

Therefore, the common counter circuit simplifies the circuit, and even if crosstalk occurs, it may cause noise due to different frame phases, but it does not cause intelligible crosstalk. .

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a digital multiplex conversion apparatus as a first embodiment of the present invention. In this embodiment, n = 2 and m = 2. That is, in this embodiment, four (2 × 2) DS1 signals 4 as low-order group signals are used.
-1 to 4-4 are input. And, it is provided with two multiplexing devices 2a and 2b. Signal 4-of low order group signal input
1 and 4-2 are input to the multiplexer 2a, and the signal 4-3 is input.
And 4-4 are input to the multiplex converter 2b. Stuff pulses 6-1 to 6-4 are input to each of the multiplexers 2a and 2b together with the input of the low-order group signals. Higher-order group signals 7-1 and 7-2 are output from each of the multiplex converters 2a and 2b. The high order group signals 7-1 and 7-2 are signals asynchronous with the low order group signal input.

Here, the feature of the present invention is that each multiplexer 2a
The frame signal necessary for assembling the multiplex signals in 2 and 2b is commonly supplied from one counter circuit 1 and is also supplied to the two multiplex converters 2a and 2b in the supply path of the frame signal 9. The delay device 8 is inserted in the multiplex conversion device 2b so that the phases of the signals are different from each other. As the simplest example, the delay amount of the delay device 8 is a time corresponding to 1 bit of the high-order group signal.

In such a device, the read clocks 5-1 to 5-4 are sent to the memories on the left side of FIG. The next group signal is read out and input to the multiplex converters 2a and 2b together with the stuff pulse. In each of the multiplex converters 2a and 2b, the multiplex signal is assembled according to the frame signal input from the counter circuit 1, and the high-order group signal 7-
It is sent as 1 or 7-2.

Here, in the device of the present invention, since only one counter circuit 1 is provided for the plurality of multiplexers 2a and 2b,
The circuit configuration is simplified. Moreover, the delay device 8 causes the phase of the frame signal to be transmitted to a plurality of multiplexers 2a and
2b is different, so the output higher order group signal 7
Even if crosstalk occurs between -1 and 7-2, it is not intelligible when the crosstalk is decoded.

FIG. 2 is a block diagram showing the apparatus of the second embodiment of the present invention, which is a generalization of the first embodiment of FIG. In this example, the incoming low-order group signals 4-1 to 4-m are n signals each. The n low order group signals 4-1 to 4-m, each of which is n, are stuff pulses 6-1 to 6 respectively.
-M together with m multiplex converters 2-1 and 2-1
Given to -m. Then, each of the multiplex conversion devices 2-1 to 2
Higher-order group signals 7-1 to 7-m are sent to the output of -m, respectively.

Here, even if there are m multiplex converters 2 as in this embodiment, the frame signal 9 is commonly supplied from one counter circuit 1 to each multiplex converter 2-1 to 2-m. Then, this frame signal is transmitted to each of the multiplex conversion devices 2-1 to 2-m.
The delay signals 8-2 to 8-- having different values in the supply path of the frame signal 9 so that their phases do not match.
m is inserted. Since the delay amount is zero in the multiplex conversion device 2-1, it is not necessary to insert a delay device. And
The delay units 8-2 to 8-m are set so that the delay amount increases in order of 1 bit. That is, the delay device 8-2
The delay amount is set to 1 bit, the delay amount to 8-3 is set to 2 bits, and the delay amount to 8-m is set to m-1 bits.

In this way, 1 is set for a plurality of m multiplex converters.
It is sufficient to provide one counter circuit 1, and the phases of the output frames do not match in each of the multiplex converters 2-1 to 2-m. Therefore, even if crosstalk occurs, when the multiplexed signal is decoded. There is no intelligible crosstalk.

In the above-mentioned embodiment, an example in which a delay is used to give a delay bit by bit is shown. However, if the phase of the frame signal is set to be different for each multiplex conversion device, the delay device may be configured by other methods. You can

〔The invention's effect〕

As described above, according to the present invention, since each frame signal of m high-order group signals is commonly supplied from one main frame signal, the circuit scale can be reduced and simplified. Moreover, the phase of the frame signal is different for each high-order group signal, so that even if crosstalk occurs, the crosstalk is not intelligible when the high-order group signal is decoded and its influence can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a digital multiplex conversion apparatus as a first embodiment of the present invention. FIG. 2 is a block diagram showing a main part of a digital multiplex conversion apparatus as a second embodiment of the present invention. FIG. 3 is a block diagram showing a main part of a conventional digital multiplex conversion device. 1, 1a, 1b ... Counter circuit, 2, 2a, 2b, 2-1 to 2
-M ... Multiplex converter, 3, 3a, 3b ... Drive circuit, 4-
1 to 4-m ... Low-order group signal (DSI signal), 5-1 to 5-5
m: read clock, 6-1 to 6-m ... stuff pulse, 7-1 to 7-m ... high-order group signal (DS1C signal),
8, 8-1 to 8-m ... Delay device, 9 ... Frame signal,
9-1 to 9-m ... Distributed frame signals.

Claims (1)

[Claims] 1. A low order group signal input of n × m (n and m are natural numbers of 2 or more), m multiplex converters, and a frame asynchronous with the low order group signal input to the multiplex converter. A counter circuit for supplying a signal, and distributes the low-order group signals to the m multiplex converters n by n together with the stuff pulse, and asynchronously with one low-order group signal from each multiplex converter. In the digital signal multiplexer for obtaining the higher-order group signal, one counter circuit is provided in common for the m multiplex converters, and the m number of the multiplexer circuits are provided in the frame signal path between the counter circuit and each multiplex converter. In the multiplex converter, delay devices having different delay amounts are inserted so that the phases do not match each other. A digital signal multiplexing device characterized by the above.