JPH077600B2 - Memory circuit device - Google Patents

Description

The present invention relates to a memory device, and more particularly to a technique for facilitating a test such as failure analysis of a memory circuit device.

[Conventional technology]

FIG. 2 shows an example of a conventional memory circuit device of this type. Here, a writable and readable storage circuit device (RAM for short) that uses a MOS field effect transistor (abbreviated as MOS transistor) will be described as an example, but the same applies to a circuit that uses a bipolar transistor. .

A large number of memory elements (hereinafter, referred to as cells) 400 in the row direction and the column direction, signal lines (hereinafter, referred to as word lines) WL1, WL2, ..., WL2 ⁿ for selecting the cells in the row direction, and cells in the column direction are selected. Signal lines (hereinafter referred to as bit lines) 801 and 802, and address A
1, A2, A3, ..., An decoder 100, a read circuit (hereinafter referred to as a sense circuit) 700 that outputs stored information to R1 to R4,
Circuit 600 for writing information input terminals W1-W4 to cell 400
And the signal ▲ ▼ that controls the circuit and the bit line 80
It consisted of 1,802 load transistors 300.

Here, examples of circuits used in the cell 400 are shown in FIGS.

FIG. 3 shows an example of a static type cell using nMOS type transistors Q ₁ and Q ₂ and resistors R ₁ and R ₂ . Figure 4
It is an example of a complementary MOS transistor cell composed of nMOS type transistors Q ₁ and Q ₂ and PMOS type transistors Q ₃ and Q ₄ . Both examples are connected to the bit lines 801 and 802 via nMOS type transistors called transfer gates.

[Problems to be solved by the invention]

Since the conventional memory circuit device described above has various circuits, when a defect is found in the operation test of the circuit, it is necessary to spend a great deal of time to identify the defective part. there were. For example, in the circuit of FIG. 2, a cell 400 selected by certain addresses A1, A2, A3, ..., An
Write the input information W1 to W4 to the control signal ▲ ▼,
Even if the operation of reading from the sense circuit 700 to the outputs R _{1 to} R ₄ is taken as an example, when the desired output information is not output, where the defective portion is located is determined by the decoder 10.
Input circuit such as 0 or write circuit 600, sense circuit 70
It often took an enormous amount of time and labor to know whether the output system such as 0 or the cell 400 itself was bad. In some cases, it was not possible to know the defective part at all.

[Means for solving problems]

The present invention provides a row decoder driver, a storage element matrix connected to its output signal line (word line) and a bit line in the column direction, a circuit (sense circuit) for reading the storage information of this storage element, and a storage element. A memory circuit device including a circuit for writing information has a test read-only cell connected to a bit line and a test signal line for selecting the dedicated cell.

〔Example〕

 FIG. 1 shows an embodiment of the present invention.

In this embodiment, word lines WL1, WL2, ..., WL2 ⁿ and bit lines 801,
A number of cells 400 connected to 802 and addresses A1, A2, A3,
…, An decoder 100, sense circuit 700, and terminals W1 to W4
The circuit 600 that writes the information input by the cell 400 by the control signal ▲ ▼ and the load transistor 3 of the bit line.
00, read-only cells for testing 501 and 502 which are connected to bit lines, test signal lines 901 and 902 for selecting the cells, test terminals T1 and T2, and output of this terminal and the decoder 100 described above. 101 and input, word lines WL1, WL2,
..., a gate 202 for controlling WL2 ⁿ .

Here, in the cell 501, as shown in FIG. 5, the drain of the nMOS type transistor Q ₁ is the bit line 801, and the test signal line 9 is
01 is connected to the gate and the source is connected to the ground line 503.
Similarly, in the cell 502, the drain of the nMOS type transistor Q ₂ is connected to the bit line 802, the test signal line 902 is connected to the gate, and the source is connected to the ground 503. This cell is used in a read-only memory circuit called a ROM.

FIG. 6 shows an example in which cells 501 and 502 are formed on a P-type silicon semiconductor substrate 500. FIG. 6 assumes a Group 2 metal wiring process. The test signal lines 901 and 902 are polysilicon wiring, the ground line 503 is the first layer wiring, the bit lines 801 and 802 are the second layer wiring,
Reference numeral 504 is an n ⁺ type diffusion layer, 505 is a contact hole between the diffusion layer 504 and the first layer wiring, 506 is a through hole between the first layer wiring and the second layer wiring, and 507 is a first layer wiring covered with the contact hole 505. Is.

The operation of the embodiment shown in FIG. 1 is as follows. First, the test terminals T1 and T2 are set to a high level. Address decoder 1
Regular write to cell column 400 selected by 00,
Perform a read operation test. If this test fails, the test terminals T1 or T2 are set to low level. By doing this, the word lines WL1, WL2, ..., Due to the NAND gate of 202,
None of WL2 ⁿ is selected, and the information of the cell of either 501 or 502 is output. When T1 is low level and T2 is high level, the output R1 to R4 is low level, and conversely, when T1 is high level and T2 is low level, if the output R1 to R4 is high level, the sense circuit 700 is normal. In other cases, it can be determined that the sense circuit or the load transistor 300 of the bit line is defective. That is, it is possible to distinguish whether the defective portion is in the input circuit system or the output circuit system.

〔The invention's effect〕

As described above, according to the present invention, a read-only cell for testing, which is different from a memory cell that normally writes and reads information, is connected to a bit line, and a test signal line for selecting the cell is provided. As a result, if there is a defect in the memory circuit device, there is an effect that the time required for the analysis can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a circuit example using a MOS transistor of a memory circuit device of the present invention, FIG. 2 is a circuit example of a conventional memory circuit device, FIG. 3 is a static memory cell using an nMOS transistor and a resistor, 4 is a static memory cell using complementary MOS transistors, FIG. 5 is a read-only memory cell circuit using nMOS transistors, and FIG. 6 is a circuit of FIG. 5 fabricated on a semiconductor substrate. It is a top view of a case. A1, A2, A3, ..., An …… Address, W1 to W4 …… Information input terminal, R1 to R4 …… Information output terminal, ▲ ▼ …… Write control signal, T1, T2 …… Test signal terminal, WL1 , WL2, ..., WL2 ⁿ
...... Word line, 801,802 ... Bit line, 100 ... Address decoder, 101 ... Address decoder output, 202 ... 3-input NAND gate, 300 ... Bit line load transistor, 400
...... Write / read memory cells, 501,502 …… Test read-only memory cells, 600 …… Write circuit, 700…
… Sense circuits, 901,902 …… Test signal lines.

Claims (1)

[Claims] 1. A storage element matrix having a plurality of word lines, a plurality of bit lines, and storage cells respectively arranged at intersections of the word lines and the bit lines, and one of the plurality of word lines in response to an address signal. And a read / write means for writing and reading data to and from the memory cell connected to the selected word line, and a memory circuit capable of repeatedly writing and reading data to and from the memory cell In the device, a plurality of test read-only cells respectively connected to the plurality of bit lines, a test signal line for selecting these read-only cells, and the plurality of test read-only cells by the test signal line. Means for making all of the plurality of word lines in a non-selected state when selected, Memory circuit device information out dedicated cell, wherein the read out via the read / write unit.