JPH077751B2 - Charge-up detection method in MOS manufacturing process - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for detecting charge-up in a MOS manufacturing process, and more particularly, a method for detecting charge-up in an ion implantation process for forming source / drain regions of a MOS manufacturing process. Regarding

[Prior Art] A three-layer structure of metal-oxide insulator-semiconductor, in which a magnitude of an electron flow flowing from a source to a drain is applied to a gate provided through the insulator, Controlled MOS (metal oxide semiconductor) is widely used in integrated circuits. In particular, integrated circuits using CMOS have excellent characteristics such as low power consumption and large circuit operating margin, and are used in various applications. Is used for.

Conventionally, this MOS and CMOS are manufactured through the following processes (see FIG. 2).

(1) P well (P-
well) 12 is formed. The depth of this well is usually 4-5μ
It is about m.

(2) Oxidize the substrate surface with LOCOS (selective oxidation) technology,
An element isolation region 14 is formed.

(3) The MOS gate oxide film 16 is grown to 20 to 50 nm.

(4) Deposit polycrystalline silicon 18.

(5) The gate electrode is processed, and ions such as P (phosphorus) are implanted using a mask to form the source / drain regions 20.

(6) An insulating film is deposited and flattened to form contact holes and metal electrode wiring.

FIG. 2 (A) shows a plan view of the MOS thus manufactured after the polycrystalline silicon deposition process, and FIG. 2 (B) shows a sectional view thereof.

[Problems to be Solved by the Invention] However, some problems occur in the conventional MOS manufacturing process.

As described above, when the source / drain regions 20 of the MOS are formed, ions are implanted. At this time, the ions are not only the source / drain regions 20 but also the polycrystalline silicon 18 deposited on the gate oxide film 16. Is also injected. Then, the charges of the ions injected into the polycrystalline silicon 18 are concentrated near the thin gate oxide film 16.

Generally, the gate oxide film 16 is as extremely thin as 20 to 50 nm as described above, and therefore, defects are likely to occur and dielectric breakdown often occurs. However, in this conventional manufacturing process, the amount of electric charges concentrated in the vicinity of the gate oxide film 16 is a certain value, and it is not possible to determine to what level the electric charges are concentrated at an allowable level. Therefore, it is difficult to determine whether the oxide film is destroyed due to charge-up or the oxide film is destroyed due to a defect in the gate oxide film itself, and it is difficult to improve the manufacturing yield. .

The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a charge-up detection method capable of surely detecting the presence or absence of charge-up, thereby improving the yield of a MOS manufacturing process.

[Means for Solving the Problems] In order to achieve the above object, the charge-up detection method in the MOS manufacturing process of the present invention connects an integrated region for accumulating charges of implanted ions to a gate oxide film. The feature is that the charge-up is detected by changing the area of the integrated region to change the amount of charge accumulated in the vicinity of the gate oxide film.

[Operation] In the MOS manufacturing process, after the gate oxide film is formed as described above, polycrystalline silicon is deposited and ions are further implanted to form the source / drain regions, but the integrated regions having various areas are formed. Is connected to the gate oxide film, ions are injected into the integrated region according to the area thereof during ion injection, and the electric charges are concentrated on the gate oxide film.

Then, the amount of charges accumulated in the gate oxide film changes stepwise according to the area of the integrated region, and the charge-up level can be grasped and reliably detected.

[Embodiment] A preferred embodiment of a charge-up detection method in a MOS manufacturing process according to the present invention will be described below with reference to the drawings.

In the MOS manufacturing process of this embodiment, first, the P-well 12 is ion-implanted into the n-silicon substrate 10 as in the conventional case. Then, the surface is oxidized by the LOCOS technique to form an element isolation region. Further, a gate oxide film 16 having a film thickness of 20 to 50 nm is formed, and polycrystalline silicon 18 is deposited on the gate oxide film 16.

What is characteristic of the present embodiment is that the polycrystalline silicon 18 is deposited in this polycrystalline silicon 18 deposition process.
An integrated region 18a for efficiently accumulating the charges of ions to be implanted in the ion implantation process for forming the source / drain regions is formed in a part of the above, and the integrated region 18a and the gate oxide film 16 are formed. I have connected.

FIG. 1 shows a plan view of the CMOS immediately after depositing the polycrystalline silicon 18. Large area integrated area in a part of polycrystalline silicon 18
18a is formed and connected to the gate oxide film 16 formed on the P-well 12.

Then, the integrated region 18a is formed by appropriately changing the area for each manufactured CMOS.

After forming the integrated region 18a in this way, the process proceeds to an ion implantation process of implanting ions such as P and B to form the source / drain regions 20 of the MOS, but the implanted ions are only the source / drain regions. Without polycrystalline silicon
18 and the integrated region 18a are also driven.

Since the integrated region 18a has a large area, a larger number of ions are implanted and a large amount of charges are accumulated in the gate oxide film 16 as compared with the conventional MOS manufacturing process. And
The area of the integrated region 18a is formed so as to be changed for each MOS, and the amount of charges accumulated in the gate oxide film 16 is
It will change stepwise according to the area of 18a.

That is, in this embodiment, the amount of charge accumulated in the gate oxide film 16 can be controlled stepwise by changing the area of the integrated region 18a, and various accumulated charge amounts can be obtained in one ion implantation process. Will be realized. Therefore, after the ion implantation process is completed, the breakdown voltage of the gate oxide film 16 having these various levels of accumulated charge amount is inspected to grasp how much the accumulated charge amount is in comparison with the charge-up level. be able to. For example, when the area ratio between the gate oxide film 16 and the integrated region 18a is about 1: 500, the withstand voltage is 40 V when the film thickness of the gate oxide film is 25 nm, and the withstand voltage is 60 V when the film thickness is 45 nm. Therefore, if dielectric breakdown occurs after this ion implantation process, it is easy to determine whether this is caused by a defect such as a crack in the gate oxide film itself or as a result of charge-up. be able to.

Thus, in the MOS manufacturing process of this embodiment,
The amount of charges accumulated in the gate oxide film 16 is controlled by changing the area of the integrated region, and the charge-up of the gate oxide film 16 can be detected and reliably prevented.

Since the amount of accumulated charge varies not only with the area of the integrated region but also with the film thickness of the gate oxide film, charge-up evaluation of various devices is performed by appropriately combining the gate oxide film thickness and the area of the integrated region. It can also be used to obtain useful information in device design.

[Effect of the Invention] As described above, according to the charge-up detection method in the MOS manufacturing process of the present invention, in the ion implantation process for forming the source / drain regions of the MOS,
The level of the amount of charge accumulated in the gate oxide film can be grasped in stages, the presence or absence of charge-up can be reliably detected, the charge-up can be prevented, and the yield can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of a charge-up detecting method in a MOS manufacturing process according to the present invention, and FIG. 2 is an explanatory diagram of a conventional MOS manufacturing process. 10 ... n Silicon substrate 12 ... P-well 14 ... LOCOS element isolation region 16 ... Gate oxide film 18 ... Polycrystalline silicon 18a ... Integrated region 20 ... Source / drain region

Claims (1)

[Claims] 1. A CMOS in which a gate oxide film is formed on a semiconductor substrate and source and drain regions are formed by ion implantation.
In the manufacturing process, an integrated region for integrating implanted ions is connected to the gate oxide film, and the area of this integrated region is changed to change the amount of accumulated ions in the vicinity of the gate oxide film and detect charge-up. A method for detecting a charge-up in a MOS manufacturing process, which comprises: