JPH0778700B2 - Signal distribution method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] For example, in a digital multiplex transmission device or the like, a method for distributing the same signal such as a high-speed clock to a large number of locations in the device via a buffer circuit is described. A method of distributing signals to more than N distribution destinations by using M ICs having N buffer elements for the purpose of correcting variations in delay time and distributing signals in phase. , The buffer element of each IC is divided into a passing buffer element and a distributing buffer element, and a signal that has passed through the passing buffer elements of all ICs except the own IC once is distributed through the distributing buffer element of the own IC. To configure.

[Industrial application field]

The present invention relates to a method for distributing the same signal such as a high-speed clock to a large number of locations in a device such as a digital multiplex transmission device via a buffer element.

In the above device, in order to synchronize the data pulse train, it is necessary to distribute the same clocks having the same phase to a plurality of packages in the device, but the clock generating unit and the clock are required due to the limitation of the driving capability of the clock generating unit. It is distributed to the portion via a distribution circuit including a buffer circuit. However, since the distribution circuits individually have variations in propagation delay time, there is a phase difference between the clocks that reach the required parts, and especially in the recent devices that require high-speed clocks, the distributed clocks It is difficult to keep the phase difference of 1 within the allowable range.

As measures against this, various attempts have been made such that the wiring path lengths after distribution are made equal, the propagation delay characteristics of the elements constituting the distribution circuit are made uniform, and a delay time variable circuit is inserted and adjusted. The present invention relates to a clock pulse distribution method for gradually reducing a phase difference of clocks caused by a buffer circuit used in many distribution circuits.

[Conventional technology]

In a digital multiplex transmission device or the like, it is necessary to distribute a high-speed clock signal created at one place in the device to a plurality of places in the device. For this reason, in the distribution unit, the same signal is divided into a plurality of pieces and transmitted via the buffer gate formed of a semiconductor element.

A semiconductor high-speed logic element used as a buffer circuit is integrated and a plurality of elements are formed on one chip. However, when there are many distribution destinations, a plurality of chips are used for distribution as shown in FIG. is doing.

For example, when a semiconductor integrated circuit (hereinafter referred to as an IC) having a buffer gate of 6 elements per chip is used and distributed to 10 locations, two ICs 1 and 2 are used and each of the first gate elements 11 and 21 is used. Clock signal C as an input buffer circuit
LK was divided into two and received, and each signal was distributed by sending it out through the remaining 5 elements 11 to 16 and 22 to 26 used as output buffers. That is, all clock signals are distributed through two buffer elements in the same IC.

[Problems to be Solved by the Invention]

Generally, in a semiconductor integrated circuit in which a plurality of the same elements are formed, variations in the characteristics of the elements are far larger between chips than in the same chip due to the nature of the manufacturing process. Therefore, the propagation delay time of the buffer circuit also varies greatly from IC to IC, and even in the distributed high-speed clock, # 1
There is a non-negligible phase difference between the two groups # 5 to # 6 and # 6 to # 10. Therefore, there is a problem that the signal phase margin cannot be secured and it is difficult to increase the transmission speed.

The present invention has been made in view of the above problems, and an object of the present invention is to correct variations in the propagation delay time of ICs in a buffer circuit and distribute signals in phase.

[Means for Solving the Problems]

 FIG. 1 is a principle diagram of the signal distribution system of the present invention.

The above-mentioned problem is, as shown in FIG. 1, a method of distributing signals to more than N distribution destinations by using M ICs 1 to M having N buffer elements 11 to 1N,
The buffer element of each IC is divided into the passing buffer elements 11 to M1 and the distributing buffer elements 12 to 1N, M1 to MN, and the signals passed through the passing buffer elements of all the ICs except the own IC at least once are analyzed. This is solved by the signal distribution method of the present invention, which is characterized in that distribution is performed through the distribution buffer element of the own IC.

[Action]

Each distribution signal passes through the same number of passing buffer elements of all ICs except the own IC, and finally passes through the buffer elements of the own IC to be distributed. That is, since all distributed signals are distributed by passing through the buffer elements of all ICs once, even if there is a difference in propagation delay time between ICs due to variations in characteristics, each signal when reaching the final distribution destination The propagation delay time is the sum of the delay times of the buffer elements of all ICs and is equalized to reduce variations.

In this way, variations in the propagation delay time between ICs can be corrected, and the phase correction circuit can be simplified.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a block diagram showing an embodiment of a high-speed signal distribution system according to the present invention, and shows a case where the same clock signal is distributed to 10 locations by the same 6-gate IC as in the conventional example.

In the figure, the high-speed clock signal CLK sent from the clock generator is input to the first buffer gates 11 and 21 of the two ICs 1 and 2 in which six buffer gates are formed on one chip, for example. . The clock signal CLK1 that has passed through one buffer gate 21 of the second IC2 is divided into five via the remaining buffer gates 12 to 16 of the first IC1 and is output as the first group of # 1 to # 5. One
Clock signal CLK2 received by buffer gate 11 of IC1
Is output as the second group of # 6 to # 10 via the remaining buffer gates 22 to 26 of the second IC2, and the clock signal is sent to the distribution destinations of the previous 10 locations.

According to the above distribution method, all of the clock signals of the 10 systems after distribution pass through the buffer elements of the two ICs once, so there is a difference in the propagation delay time characteristics between the two ICs due to the difference in the semiconductor chips. Even if there is a difference, it will be delayed by the sum of both delay times at the end, and the difference between the ICs will be canceled out and will not cause the phase difference between the clock systems.

If the number of signal distribution destinations further increases, increase the number of ICs correspondingly, and after passing through the buffer elements of all but one IC, make the final distribution via the remaining elements of the one IC. Of course, it can be realized by the same principle.

In this way, variations between chips with relatively large deviations are canceled out, and variations in phase delay time are greatly reduced.
Adjustment of the delay time becomes easier. After that, if the data is transmitted to the final distribution position through almost the same wiring distance length, the phase adjustment between the groups becomes unnecessary, and the high-speed clock signal of the same phase can be distributed to a plurality of places, eliminating troublesome phase adjustment. It is possible to simplify the configuration.

〔The invention's effect〕

As described above, according to the present invention, it is possible to distribute a high-speed signal with a small phase difference to multiple points by canceling out variations in the characteristics of the IC in the distribution circuit for high-speed signals such as clocks. Since the phase margin is increased, it significantly contributes to the improvement of stability and reliability of the digital transmission device and the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle diagram of a signal distribution system of the present invention, FIG. 2 is a block diagram showing an embodiment of the signal distribution system of the present invention, and FIG. 3 is a conventional signal distribution system. It is a block diagram showing the method. In the figure, 1,2 to M ... ICs having a plurality of buffer elements, 11 to 1N, 21 to 26, M1 to MN ... Buffer elements formed on an IC chip.

Claims (1)

[Claims] 1. A method for distributing a signal to more than N distribution destinations by using M ICs (1 to M) having N buffer elements (11 to 1N, M1 to MN). The buffer element of is divided into a passing buffer element (11, M1) and a distribution buffer element (12 ~ 1N, M2 ~ MN)
The signal distribution method is characterized in that a signal which has passed through the passing buffer elements of all ICs except for at least once is distributed through the distributing buffer element of the own IC.