JPH0778761B2 - Memory read processing time reduction circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a circuit in the field of digital signal processing in which control of a control unit for a memory is performed by a serial command, and more specifically, a memory in the circuit. The present invention relates to a circuit that shortens the read processing time.

(Prior Art) In the field of processing a digital signal, processing of transmitting / receiving a reply command to / from each memory circuit in serial is performed.

In such a process, even if the memory contents are the same, the contents are read individually from the respective memory circuits. Therefore, if there are n memory circuits, it is necessary to execute the reading process n times.

The memory circuit is used, for example, as a time switch (a switch that arbitrarily exchanges input data in the time axis direction). The time switch is stored in RAM once and is realized by designating the reading order from another RAM. . This another RA
M is called a control memory and is provided with a plurality of control memories. It is necessary to shorten the control of this control memory.

(Problems to be solved by the invention) In the conventional processing method, regardless of the memory contents,
If there are n memory circuits, the read process is performed n times. Therefore, it is conceivable to perform the same writing in order to shorten the processing time, but the return is performed for each memory. In this case, a plurality of reply commands will be returned for one transmission command, and the processing of the control unit will be complicated, and the effect of time reduction will not be significant.

An object of the present invention is to provide a processing time shortening circuit that shortens the processing time for reading the memory circuit by assembling a plurality of reply commands from each memory circuit into one reply command.

(Means for Solving the Problem) In order to achieve the above-mentioned object, a memory read processing time shortening circuit according to the present invention is a circuit in which a control unit controls writing and reading with respect to a plurality of memory circuits by serial commands. Command comparison unit that compares the contents of each input command including the data read respectively from the
A command assembling unit for assembling an unmatched command and sending one reply command to the control unit, a signal indicating a data bit portion to be compared to the command comparing unit, and a command to the command assembling unit are assembled. It comprises a counter section for transmitting a signal indicating the bit portion to be powered.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a processing time shortening circuit according to the present invention.

Input commands 1, 2 ... N (serial commands) sent from a plurality of memory circuits (not shown) are input to the command comparison unit 1.

Each input command includes the data read from each memory circuit.

When the input command is serially sent as 1, 2, 3 for example, the command comparison unit 1 inputs the input commands 1, 2, 1, 3
The comparison is performed by such a method.

The input command comprises, for example, 64 bits to form one frame, and the effective data portions 5 to 10 bits are compared.

The comparison contents are, for example, 101 pieces of data stored at addresses 0 to 100 of the memory circuit.

The counter section 3 outputs to the command comparing section 1 a signal for comparing the bit part to be compared, that is, the 5th to 10th bits in the above example.

The command assembling section 2 sets a match / mismatch bit flag on the command according to the comparison result of the command comparing section 1. Then, in the case of coincidence, the coincident data is set, and in the case of disagreement, all "0" is set in the data bit and sent to the control unit (not shown) as one reply command.

It should be noted that in a mismatched state, a flag is returned to the request source. In case of a match, the data will be returned to the requester including the data.

When comparing the 5th to 10th bits in the above example, the counter section 3 sets, for example, the 11th bit as a flag,
A signal is output to the data bit to set matching data.

The input command is 64 bits per frame, and 5 to 10
Although the embodiment has been described in which the bits are compared and the coincidence / non-coincidence flag is set to 11 bits, the present invention can also be applied to the comparison portion other than the input command.

The same applies to the part where a flag is set.

(Effects of the Invention) As described above, according to the present invention, data on commands from a plurality of memory circuits are compared, and the result is assembled and sent out as a single command to a plurality of memory circuits having the same content. This has the effect of shortening the read processing time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory read processing time reduction circuit according to the present invention. 1 ... Command comparison unit 2 ... Command assembly unit 3 ... Counter unit

Claims (1)

[Claims] 1. A command comparison unit for comparing the contents of input commands including data read from the plurality of memories in a circuit in which the control unit controls writing and reading with respect to a plurality of memory circuits by serial commands. , A command assembling unit for assembling a match / mismatch command based on the result of the command comparing unit and sending one reply command to the control unit, and a signal indicating a data bit portion to be compared to the command comparing unit, A memory read processing time shortening circuit comprising: a counter unit which sends a signal indicating a bit portion where a command should be assembled to the command assembling unit.