JPH077889B2 - Operational amplifier circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit, and more particularly to a circuit for preventing abnormal oscillation when the output is saturated by connecting a plurality of amplifier stages in order to obtain a high gain. .

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventional operational amplifier circuit, FIG. 3 is a block diagram of the operational amplifier circuit, FIG. 4 is its block diagram, and FIG. 5 shows frequency characteristics of the circuit of FIG. 2 when saturated. It is a characteristic view to show.

As shown in FIG. 2, the conventional operational amplifier circuit includes a NPN transistor (hereinafter abbreviated as Tr) 6,7 forming a differential pair, resistors 8 and 9 serving as its load, and input Tr protection diodes 10 and 11. , A first current differential amplification stage composed of a constant current source Tr12, resistors 13 and 14 and a constant voltage source 15, and an emitter follower NPNTr16, which uses the output of the first differential amplification stage as a base input.
17, constant current sources 18 and 19 respectively provided between these emitters and the low potential terminal 2, PNP Trs 20 and 21 forming a differential pair, and a NPNTr 23 and a diode 22 of a current mirror circuit serving as a load thereof. , PNPTr21, NPN, which includes a next-stage amplification stage composed of a constant current source 24 connected to the emitters of the differential pair PNPTr20, 21.
Emitter follower whose base input is the common collector of Tr23
A complementary push with an amplification stage composed of NPNTr24, resistor 25 and NPNTr26, an emitter follower PNPNTr27 which inputs the collector of this NPNTr26 as a base, and a constant current source 28 provided between the emitter of NPNTr32 and the constant voltage terminal 2. NPNTr29, PNPTr30, resistor that configures the pull output stage
31, PNPTr34 comprising an output circuit composed of a base of NPNTr32 and a constant current source 33 connected to the high potential terminal 1, and constituting a current mirror circuit for supplying a bias current to the output stage and each stage , 35, resistors 36, 37, and a constant current source 38 to form a high-gain operational amplifier circuit.

Next, as the operation of this operational amplifier circuit, the input signals at the input terminals 3 and 4 are amplified by the first stage differential amplifier stage, and the output is fed to a normal PNP input type operational amplifier circuit and the emitter follower Tr1.
The amplified input signal is output to the output terminal 5, which is a common emitter of the complementary push-full outputs NPNTr29 and PNPTr30.

FIG. 3 is a block diagram generally showing an operational amplifier circuit. In FIG. 3, 1 kΩ is input from the input terminal to the (+) input terminal 3 via the resistor, and the output terminal 5 is input to the (−) input terminal 4 via the 1 kΩ resistor.

Since this operational amplifier circuit is used with negative feedback, a DC position deviation of at least 180 ° is inherently added to the circuit from the input to the output, and the closed loop of the total gain [1] as shown in Fig. 3 is used. In order to operate stably at, the phase must be compensated so that the total phase shift from input to output does not exceed 360 °.

FIG. 4 is a block diagram showing an operational amplifier that has performed such phase compensation. In FIG. 4, (+), (-)
A differential transistor pair having input terminals 3 and 4 as a base;
A first stage differential amplifier circuit including resistors 8 and 9 and a constant current source whose one end is connected to the second power source 2, and the first power source 1 and (+)
It comprises a next-stage differential amplifier circuit having a capacitor 39 between the input and the output terminal, a resistor 41 between the output terminal 5 and the (-) input, and a series body of the capacitors 40.

In this operational amplifier circuit, the feed-forward phase compensation is performed by the capacitors 39 and 40 and the resistor 41, and a stable frequency characteristic of 6 dB / octave is obtained as a whole as shown in FIG.

In Fig. 5, the gain is attenuated by the characteristic of 6 dB / octave, and the phase shift is constant up to 7 MHz, and becomes larger when it exceeds this. The phase shift at gain [1] is sufficient.

[Problems to be Solved by the Invention]

The above-mentioned conventional high-gain operational amplifier circuit has a multi-stage connection configuration of amplifier circuits by the first stage differential amplifier stage of NPNTr6,7 and the next stage PNP input type operational amplifier circuit in order to achieve high gain. Therefore, as shown in Fig. 5, the open loop gain is several + dB.
And a gain of about 120 dB is combined.

Here, when the output is swung positively and saturated, when the degree of saturation is shallow, the frequency characteristic of the circuit becomes the gain and phase shift as shown in Fig. 6, and due to the saturation of the drive PNPTr34 of the output NPNTr29, Since the phase shift progresses and the NPNTr24, 26 head toward the cutoff direction, the gain also drops, but since the first differential amplification stage and the gain remain a few + dB, the phase shift is 360 ° and the gain is 1 or more in the section A, The oscillation condition will be satisfied, and there is a drawback that oscillation of several + to several hundred KHz related to phase compensation occurs at the output end.

An object of the present invention is to solve the above-mentioned drawbacks and to provide an operational amplifier circuit in which oscillation does not occur in a high frequency range.

[Means for Solving the Problems]

According to the configuration of the present invention, in an operational amplifier circuit including a first-stage differential amplifier circuit and a second-stage differential amplifier circuit, means for detecting that the output of the second-stage differential amplifier circuit is saturated and means for detecting the output And a means for controlling the gain of the first-stage differential amplifier circuit by a saturation signal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an operational amplifier circuit according to an embodiment of the present invention. In FIG. 1, the operational amplifier circuit of this embodiment is
NPNTr42, NPNT for detecting output saturation in the conventional circuit of Fig. 2
r43, resistor 44, and a second pre-drive for the first stage differential amplification stage
And a constant current source 45 of The operational amplifier circuit of the present embodiment is the same as the conventional example in the circuit operation except the time of saturation, but when the total gain number + dB is used in the worst condition, the total gain [1] as shown in FIG. The operation when positively saturated is different, the saturation of the drive Tr34 of the output stage NPNTr29 is detected by PNPTr42 and the resistor 44, and NPNTr43 detects the first constant current source NPNTr12 of the first stage differential amplifier circuit. Cut off the gain of the first differential amplification stage with the second constant current source 45 [1]
Since the input signal has a gain [1] or less and is input to the operational amplifier circuit of the next stage, the gain and the phase deviation of the entire circuit are 360 ° in the section B as shown in FIG. Thus, the gain becomes [1], and it is possible to prevent the oscillation condition from being satisfied.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent the oscillation when the output is saturated with the total gain [1] by detecting the saturation of the output terminal and reducing the gain of the first stage differential amplification stage. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an operational amplifier circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional operational amplifier circuit, and FIG. 3 is a total gain [1] of the operational amplifier circuit. Circuit block diagram, FIG. 4 is a block diagram of the operational amplifier circuit of FIG. 2,
FIG. 5 is a characteristic diagram showing frequency characteristics of the circuit of FIG.
FIG. 7 is a characteristic diagram showing the frequency characteristic when the output is saturated in the conventional example, and FIG. 7 is a characteristic diagram showing the frequency characteristic when the output of the circuit of FIG. 1 is saturated. 1 ... High-potential power supply, 2 ... Low-potential power supply, 3 ... Non-inverting input terminal, 4 ... Inversion input terminal, 5 ... Output terminal, 8,9,1
3,14,25,31,36,37,41,44 …… Resistance, 6,7,12,16,17,23,2
4,26,29,32,43 …… NPN transistor, 20,21,27,30,34,3
5,42 …… PNP transistor, 18,19,24,28,33,38,45 ……
Constant current source, 10,11 …… Diode, 39,40 …… Capacitor.

Claims (1)

[Claims] 1. An operational amplifier circuit comprising a first stage differential amplifier circuit and a second stage differential amplifier circuit, means for detecting that the output of the next stage differential amplifier circuit is saturated, and saturation detected by the means. And a means for controlling the gain of the first-stage differential amplifier circuit according to a signal.