JPH0778938B2 - Magnetic recording / reproducing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus having an auto-tracking function, and particularly to an apparatus which can be easily realized at low cost by using a microprocessor.

2. Description of the Related Art In recent years, microprocessors have been remarkably popularized and have come to be used in many household electric appliances. This is no exception to the case of home video tape recorders (hereinafter abbreviated as VTRs). It is used at the center of the system such as the control of the loading mechanism that pulls out the magnetic tape from the cassette and winds it around the rotary head, and the program reservation that combines a timer. Microprocessors are being actively used. However, in a precise rotation control device for a cylinder motor that drives a rotary head or a capstan motor that runs a magnetic tape at a constant speed, complicated judgment operations and rapid processing of detection signals are required, so a microprocessor is not used. Has relied on dedicated hardware.

FIG. 10 is a block diagram showing a configuration of a servo mechanism during reproduction of a conventional VTR, which is a cylinder motor 2 for driving a rotary head 8 and a first frequency generator for detecting the rotation speed of the cylinder motor 2. 3, a phase detector 4 for detecting a rotation phase of the cylinder motor 2, a first frequency discriminator 40 for detecting an error of an output signal of the first frequency generator 3 with respect to a reference cycle, and a reference signal generator. And a first phase comparator 41 for detecting a phase error between the rotation phase signal obtained by the phase detector 4 and the reproduction reference signal obtained by the reference signal generator 42, and its first phase comparison. Vessel 41
A first adder 43 for mixing the phase error output of the first frequency discriminator 40 and the speed error output of the first frequency discriminator 40, and a first amplifier 44.
And a first drive circuit 12 for driving the cylinder motor 2,
A capstan motor 6 for running the magnetic tape at a constant speed,
A second frequency generator 7 for detecting the rotation speed of the capstan motor 6 and a control head 5 for detecting a control signal recorded at the lower end of the magnetic tape 1.
A second frequency discriminator 45 for detecting an error of the output signal of the second frequency generator 7 with respect to the reference period; and a variable resistor triggered by the output signal of the reference signal generator 42.
A tracking mono-multi circuit 46 whose delay time is variable by 50, a second phase comparator 47 which detects a phase error between the control signal obtained from the control head 5 and the output signal of the tracking mono-multi circuit 46,
A second adder 48 for mixing the phase error output of the second phase comparator 47 and the speed error output of the second frequency discriminator 45, a second amplifier 49, and a capstan motor 6 are provided. It is composed of a second drive circuit 13 for driving.

The operation of the VTR configured as described above will be briefly described with reference to the configuration diagram of FIG. 10 and the timing chart of the main parts shown in FIG.

FIG. 11N shows an output waveform of the reference signal generator 42 shown in FIG. 10, and this signal is used as a reference signal at the time of reproducing the VTR, the first phase comparator 41 and the tracking mono-multi circuit
Supplied to 46. The trapezoidal wave signal of FIG. 11 is the internal waveform of the first phase comparator 41, is the phase reference signal of the cylinder motor triggered by the rising edge of FIG. 11N, and is the phase detection signal of FIG. The rotation phase signal obtained from the device 4, that is, the hold signal (not shown) sampled by the falling edge of P in FIG. 11 and the speed error signal obtained from the first frequency discriminator 40 in FIG. The first
Are mixed in the adder 43 and are supplied to the first drive circuit 12 via the first amplifier 44. Therefore, the cylinder motor, that is, the rotary head 8 rotates in phase synchronization with the reference signal shown in FIG.

FIG. 11Q is a charging / discharging waveform of a capacitor (not shown) in the tracking mono-multi circuit 46 of FIG. 10, and FIG.
The delay time can be varied by being triggered by the rising edge of and changing the time constant with the variable resistor 50 shown in FIG.

FIG. 11R is the output waveform of the tracking mono-multi circuit 46, the trapezoidal wave signal of FIG. 11S is the internal waveform of the second phase comparator 47 of FIG. 10, and the falling edge of FIG. 11R. Which is a phase reference signal of the capstan motor triggered by, and is sampled by the reproduction control signal obtained from the control head 5 of FIG. 10, that is, the rising edge of T of FIG. 11, and its hold signal (not shown), The speed error signal obtained from the second frequency discriminator 45 shown in FIG. 10 is mixed in the second adder 48 to obtain the second amplifier.
It is supplied to the second drive circuit 13 via 49. Therefore, the capstan motor 6 rotates in phase synchronization with the output signal of the tracking mono-multi circuit 46 of FIG. 11R obtained by phase-shifting the reference signal of FIG. 11N.

As described above, when the VTR is reproduced, the rotary head 8 and the reproduction control signal (T in FIG. 11) are phase-synchronized with each other so that the rotary head 8 can best track the track recorded on the magnetic tape 1. Become.

Problems to be Solved by the Invention If the formats of the tracks recorded on the magnetic tape are compatible, the variable resistor 50 may be a fixed resistor, but the magnetic tape expands and contracts due to environmental changes such as temperature changes. In addition, when reproducing a tape recorded by another VTR in which a mechanical error has occurred, it is necessary to change the tracking state during reproduction, that is, the phase relationship between the rotary head and the reproduction control signal. Therefore, the variable resistor 50 shown in FIG. 10 is necessary. Furthermore, this variable resistor needs to be a volume with a click point in order to release it to the user.

In general, the resistance value at the click point of the volume with a click point varies, and another variable resistor is required to correct the variation. Therefore, in the conventional VTR, not only the adjustment volume is required for tracking, but also the operability, that is, the usability is required to be improved.

Means for Solving the Problems In order to solve the above problems, in the magnetic recording / reproducing apparatus of the present invention, the frequency-modulated wave signal is recorded by the rotary head, and the control signal of a constant cycle is recorded by the control head. At the time of reproducing the recorded signal recorded on the recorded recording medium, an error with respect to the reference phase of the phase difference between the head switching signal indicating the rotation phase of the rotary head and the reproduced control signal is detected, and based on the error signal. A magnetic recording / reproducing apparatus for controlling the rotation of a running motor of the recorded recording medium, wherein the tracking variable means for varying the reference phase and the frequency-modulated wave signal reproduced from the recorded recording medium Sampling means for sampling a signal based on the head switching signal at each constant phase, and the tracking variable hand. Comparing means for performing a magnitude comparison based on a plurality of sampling data obtained by the sampling means when the reference phase is varied at a constant interval by a stage, and a calculation for obtaining a difference between the continuous sampling data and comparing the difference. N times (N ≧ 2; N is an integer) by the means and the comparing means and the calculating means
Selecting means for selecting to detect that the difference between the data is within a certain value continuously, data storing means for taking in the reference phase of the tracking varying means with respect to the sampling data obtained by the selecting means, The reference phase stored in the data storage means is sent to the tracking varying means as the final reference phase.

Effect According to the present invention, the structure described above makes the magnetic tape expandable and contractible due to environmental changes such as temperature changes, and is stable against so-called compatible tapes recorded on other VTRs that have mechanical errors. It is possible to obtain a magnetic recording / reproducing device that realizes the above-described auto tracking function.

Examples Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a VTR having an auto-tracking function according to an embodiment of the present invention, which drives two pairs of rotary heads 8 and 9 for recording and reproducing video signals and audio signals, respectively. A cylinder motor 2 and a capstan motor 6 that runs the tape 1 at a constant speed are controlled, and a microprocessor 10 that realizes an auto-tracking function and the microprocessor 10 via a first analog signal output terminal 27 are provided. A first drive circuit 12 for driving the cylinder motor 2 by the output signal, and a second analog signal output terminal 28 from the microprocessor 10.
The second drive circuit 13 for driving the capstan motor 6 by the signal output via the amplifiers, the amplifier circuits 14, 16 for amplifying the reproduction envelope signals obtained from the rotary heads 8, 9, respectively, and the amplified reproduction. The detection circuits 15 and 17 for peak detection of the envelope signal and the detection outputs of the detection circuits 15 and 17 are input, and the detection circuit 17 controls the signal to detect the presence or absence of recording of the audio signal, that is, the audio signal is recorded. If not, or if the level of the audio signal is less than a certain value, the output of the detection circuit 15, the switch circuit 18 for selecting the output of the detection circuit 17 when the audio signal is recorded, The output of the switch circuit 18 and a signal output from the microprocessor 10 via the third analog signal output terminal 26 are input to form a comparator 19 as a whole. The input terminals 21 to 25 of the microprocessor 10 are connected to the outputs of the first frequency generator 3, the first phase detector 4, the control head 5, the second frequency generator 7, and the comparator 19. There is.

Inside the microprocessor 10, a register 100 for storing data, a random access memory (indicated by an abbreviation symbol RAM in the drawing, hereinafter abbreviated as RAM) 200, and arithmetic and logical operation of digital data are provided. A 16-bit arithmetic unit (abbreviated as ALU in the figure, abbreviated as ALU in the figure) for executing 300, an instruction to be sequentially executed, and a control bus based on the instruction.
The register 100 and RAM 200 and the ALU 300 via 450
Instruction execution circuit (indicated by PLA in the figure) 400 that controls the operation of the
Down count the reference clock signal applied to 20
Count data of the time base counter 500 is supplied via a 17-bit time base counter (indicated by TBC in the figure) 500 and a counter bus 550, and the output data is supplied to the register 100 and the register 100. RAM200,
A capture register block (indicated by an abbreviation CAPREG in the drawing) 700 sent to a data bus 600 connected to the ALU 300, and first to fifth input terminals 21, 22, 2
Applied to 3,24,25, each with different source 6
A capture controller (indicated by an abbreviated symbol CAPTRCTRL in the drawing) 800 for transferring the count data of the time base counter 500 to the capture register block 700 when the edge of the type of capture symbol arrives is provided.

Further, the reference clock signal applied to the clock terminal 20 is supplied to the instruction execution circuit 400 via a timing generator (indicated by an abbreviated symbol TG in the drawing) 900, and read out to the data bus 600. Dedicated memory (abbreviated as ROM in the figure, abbreviated as ROM below) 1000, I / O port 1100, first DA converter 1200, second
A DA converter 1300 and a third DA converter 1400 are connected, and the RAM 200 and the ROM 1000 have address decoders 250 and 1050, respectively.

The capture controller 800 and the capture register block 700 fetch the count data whose minimum resolution accuracy is higher than the instruction execution cycle from the time base counter 500 when the edge of the capture signal arrives, and the instruction execution circuit 400 Depending on the specific instruction from the ALU300 or the register 10
0 or constitutes a capture circuit for sending to the RAM 200.

Regarding the VTR configured as above, the configuration diagram shown in FIG. 1 and the capture controller 800 shown in FIG.
The operation will be described with reference to the specific configuration diagram of FIG. 3 and the timing chart of the main part shown in FIG.

First, FIG. 2 is a logic circuit diagram showing a specific configuration example of the capture controller 800 of FIG.
The control units 810 to 850 of the same configuration are connected to the input terminals 21, 22, 23, 24, 25 of the control units 810 to 850, and the control units 810 to 850 are connected to the common reference clock input terminal 801 and the capture register block 700, respectively. It has a data transfer clock input terminal 802, and further has individual reset terminals 811 to 851, individual flag output terminals 812 to 852, and individual data transfer terminals 813 to 853.

Next, FIG. 3 shows the third DA converter 1400 and the comparator 11 of FIG. 1 and the capture controller shown in FIG.
FIG. 3A is a timing chart for explaining the operation of the AD conversion mechanism constituted by the control unit 850 and the capture register block 700 which constitute 800, and FIG. 3A is applied to the clock terminal 20 of FIG. A clock signal waveform, FIG. 3B is a signal waveform obtained by dividing the signal waveform of FIG. 3A, and this signal is supplied to the reference clock input terminal 801 of FIG. 2 as a reference clock signal.

Further, FIG. 3C shows a count clock signal waveform of the time base counter 500 constituted by a synchronous counter having a master slave type flip-flop as a unit stage, and a leading edge (leading edge) with an arrow is shown. ) Changes the output of the master section of the flip-flop of each unit stage, and changes the output of the slave section at the trailing edge (trailing edge).

FIG. 3D shows a clock signal waveform for data transfer generated from the signal waveforms of FIGS. 3A and 3B, and is supplied to the data transfer clock input terminal 802 of FIG.

Further, FIG. 3E is an analog output signal of the third DA converter 1400 applied to the non-inverting input terminal of the comparator 11 of FIG. 1, and FIG. 3F is output from the detection circuit 10 of FIG. 3 is an output signal obtained by comparing the peak detection signal of the reproduction envelope signal and the signal of FIG. 3E by the comparator 11.

Now, when the signal waveform shown in FIG. 3F is applied to the fifth input terminal 25 of FIG. 2, the level of the reference clock input terminal 801 shifts to “1” after the leading edge thereof arrives. At the time, the output level of the NAND gate 854 shifts to "1" as shown in FIG. 3G, and at the time when the level of the reference clock input terminal 801 shifts to "0", the output level of the NAND gate 855 shifts to the first level. When the level of the reference clock input terminal 801 again shifts to "1" as shown in FIG. 3H, the NAND gate 8
The output level of 56 shifts to "1" as shown in FIG. Since each of the NAND gates 854, 855, and 856 constitutes a bistable circuit with another pair of NAND gates, when the output level shifts to "1", the state is maintained until a reset signal is applied to another NAND gate side. Hold the above
At the time when the output level of the NAND gate 856 shifts to "1", the output level of the paired NAND gate 857 shifts to "0" and the output level of the AND gate 858 shifts to "0". The output level of the gates 854 and 855 returns to "0".

In this way, when the leading edge of the external signal arrives at the fifth input terminal 25, the second data transfer terminal 853
, A signal waveform as shown in FIG. 3J is sent through the AND gate 859, and this signal transfers the count data from the time base counter 500 in FIG. 1 to the capture register block 700.

That is, in the signal waveform of FIG. 3F, the timing at which the level shifts from “0” to “1” depends on the potential of the output signal of the detection circuit 10 of FIG. 1 and is therefore transferred to the capture register block 700. Time base counter 5
The count data of 00 also depends on the potential of the output signal of the detection circuit 10.

The output signal of the NAND gate 856 is the flag output terminal 8
It is sent to 52 and is used as a capture flag signal indicating that the count data of the time base counter 500 has been transferred, and the software (program) confirms that this capture flag is set at the reset terminal 851. After confirmation, the reset signal is applied.

Next, FIG. 4 is a block diagram showing a concrete example of the capture register block 700. Each data input terminal is connected to the D0 terminal to D7 terminal, and the data output terminal is connected to the Q1 terminal to Q8 terminal. A unit register 750 composed of eight memory cells and a data input terminal D
0 terminal to D15 terminal, and data output terminal is Q1 terminal to
Unit registers 740 and 730 made up of 16 memory cells connected to the Q16 terminal, and 16 data registers connected to the D1 to D16 terminals and data output terminals to the Q1 to Q16 terminals, respectively. The unit registers 720 and 710 formed of memory cells form the whole.

Each unit register 710 to 750 has two control signal input terminals, and the data transfer signals from the capture controller 800 shown in FIG. 2 are applied to the read terminals 711 to 751 respectively, and the select terminal 712. ~ 752
The output side of each unit register is made active by a specific read instruction stored in the program storage area of the instruction execution circuit 400, and the data output Q1 pin to Q1
A select signal for reading is applied to the data bus 600 of FIG. 1 through the 6 terminals.

By the way, the transfer control signal from the data transfer terminal 853 in FIG. 2 is supplied to the read terminal 751 in FIG. 4, and the 8-bit count data of the time base counter 500 is transferred to the unit register 750. However, in the embodiment of the present invention shown in FIG. 1, since the scan counter for conversion and the register for storing the conversion result use the mechanism prepared as the capture circuit, the load on the hardware is increased. Is considerably lighter.

By the way, the connection positions of the data input terminals and the data output terminals of the unit registers 730 to 750 are shifted by one bit in FIG. 4, but this is for the following reason.

First, the same 8-bit count data as that supplied to the DA converter 1400 of FIG. 1 is supplied to the input section of the 8-bit unit register 750, but the DA converter 1400 is used to increase the sampling rate. Further, it is desirable to supply the count data of the time base counter 500 closer to the LSB (least significant bit) to the unit register 750.

Regarding the unit registers 730 to 740, the LSB of the time base counter 500 is matched with the LSB of the unit register in order to improve the resolution of the timing of capturing the edge of the external signal. The data input terminals are left-shifted by one bit so that the same number of bits as ~ 740 can be processed at one time up to twice the interval. Such a unit register 73
With the bit shift configuration of 0 to 740, for example, when the frequency of the reference clock signal is selected to be 2 MHz, the unit register 73
Count data having a resolution of 500 ns can be obtained from 0 to 740, while count data having a resolution of 1 usec can be obtained from the unit registers 710 to 720, so that the arrival cycle of an external signal having a frequency of about 30 Hz is It can be measured by processing.

The operation of the VTR having the auto-tracking function configured as described above will be described with reference to the configuration diagram shown in FIG. 1 and the operation flowcharts and operation waveform diagrams shown in FIGS. 5 to 8.

FIG. 5 shows a control means for operating the capstan motor 6 by processing the count data obtained when the leading edge of the control signal recorded on the magnetic tape arrives as the traveling phase detection data of the magnetic tape, that is, the capstan motor 6 6 is a flowchart showing an example in which the phase control during reproduction of is realized by a program built in the microprocessor 10 of FIG. 1.

The flowchart of FIG. 5 will be described with reference to the operation waveform diagram of the conventional VTR of FIG.

VTR by processing blocks 451 and 453 and branch 452 in FIG.
The reference signal at the time of reproduction, that is, the signal corresponding to FIG. 11N is created, and REF and TRM in the processing block 453 are constants, and are the repetition period of the reference signal and the central value of the tracking shifter amount, respectively. Yes, in the memory 1, the count value corresponding to the leading edge of the next reference signal, that is, the 11th
The time corresponding to the rising edge of FIG. N, the tracking shifter amount, that is, the time corresponding to the falling edge of FIG. 11R is written in the memory 2.

As will be described later in detail, the memory 3 is written with the amount of change from the center value of the tracking shifter amount for the auto tracking function.

Next, the processing blocks 454 and 456 and the branch 455 create a phase reference signal of the capstan motor, that is, a trapezoidal wave signal corresponding to FIG.
At 55, it is judged whether or not the count value of the time base counter 500 of FIG. 1 exceeds the tracking shifter amount written in the memory 2, and if it exceeds, at processing block 456 the arrival of the reproduction control signal is judged. Reset the NL flag to check the existence (indicates that it has not arrived)
Then, the count value corresponding to the boundary point between the high level (hereinafter abbreviated as H level) period of the trapezoidal wave signal of FIG. 11S and the slope section is written in the memory 4. Therefore, TPZ in the processing block 456 is a constant corresponding to the H level period.

Next, in branch 457, it is checked whether or not a reproduction control signal has arrived. This indicates that the capture controller 800 has transferred the count value of the time base counter 500 to the capture register block 700 at the leading edge of the reproduction control signal applied to the third input terminal 23 of the microprocessor 10 of FIG. This can be done by checking if the CTL flag is set. If the CTL flag has been set, processing continues at processing block 458 where register 100 of FIG.
The register file, that is, the count value latched in the capture register block 700 in FIG. 1 is transferred to the memory 5 via the accumulator (hereinafter abbreviated as Acc).

And after checking the NL flag on branch 459,
The processing block 460 and the branch 461 determine whether or not the time at which the control signal arrives is earlier than the time written in the memory 4, that is, the boundary point between the H level section and the slope section in FIG. 11S. If YES, the process proceeds to the processing block 463, Acc is set to a value corresponding to the H level in FIG. 11S, and if NO, the process proceeds to the processing block 462.

Processing block 462 and branch 464 now check to see if the arrival time of the control signal has passed the slope section of FIG. 11S. KEISH in processing block 462
A is a count value (constant) corresponding to the slope section in FIG. 11S
Is. If the slope section has passed, the process proceeds to processing block 465, where Acc is set to a value corresponding to the low level (hereinafter abbreviated as L level) of the trapezoidal wave signal of FIG. 11S.

Then, by processing blocks 469 and 470, the value corresponding to the phase error left in Acc is written in the memory 6, and the NL
The flag is set. If the control signal has not arrived on branch 457, ie, the CTL flag has not been set, processing block 466 and branch 4
67, the count value of the time base counter 500 is
It is checked whether or not the time corresponding to the boundary point between the slope section and the L level section in FIG. 11S has passed, and if yes, a processing block 468 sets Acc to a value corresponding to the L level in FIG. 11S. Set and proceed to processing block 469 above.

As described above, the phase control of the capstan motor 6 is performed.

Next, the auto-tracking operation will be described with reference to the flowcharts of FIGS. 6 and 8 and the operation waveform chart of FIG.

FIG. 6 shows a reproduction envelope signal obtained from the rotary head 8 or 9 shown in FIG. 1, which is amplified by the amplifier circuit 14 or 16 and peak-detected by the detector circuit 15 or 17, and the above-mentioned capture circuit, DA converter and comparator are provided. 9 is a flow chart showing an example in which the means for loading the AD-converted digital data into a memory is realized by a program built in the microprocessor 10 of FIG. 1.

FIG. 7K is a head switching signal of the pair of rotary heads 8 or 9 attached to the cylinder motor.
Fig. L shows a reproduction envelope signal obtained from the rotary head 8 or 9 and Fig. 7M shows the signal by the detection circuit.
It shows the signal that is peak-detected by 15 or 17. That is, the signal of FIG. 7M is the comparator 19 of FIG.
Is a signal applied to the inverting input terminal of the signal, and the signal is AD-converted by the capture controller 800, the capture register block 700, etc. as described above.

Branches 401, 405, and 410 in FIG. 6 are processes for branching a flow according to the value of the state variable A set in the RAM, that is, the memory.

First, when A = 0, the processing block 402 is executed by the branch 401.
Head switching signal input to the I / O port 1100 of FIG. 1 (HSW, FIG. 7K, abbreviated as HSW signal hereafter)
The HSW signal goes low after the signal level of
When the level is detected, the state variable A is set to 1 by the processing block 404.

When A = 1, the branch 405 advances to the processing block 406, the signal level of the HSW signal is fetched into Acc, the branch 407 detects the rising edge of the HSW signal, advances to the processing block 408, and detects about 8 ms later. In order to set the timer. As can be seen from the envelope signal shown in FIG. 7L, the envelope signal output obtained from the rotary head is not constant due to head variations and recording track non-linearity. This is to keep the point at the same position, that is, about 8 ms after the rising edge of the HSW signal.

The timer set is realized by using the time base counter 500 shown in FIG. 1 or by using a soft counter that is executed depending on how many times a specific instruction on the program has passed.

Then proceed to processing block 409 where the state variable A is incremented to two.

When A = 2, the branch 410 jumps to the processing block 411, and it is determined whether or not the timer set when A = 1 has completed counting. If yes, the process proceeds to processing block 412, and the peak detected signal (M in FIG. 7) of the reproduction envelope signal is AD as described in FIGS. 3 and 4.
The register file in which the converted digital value is fetched, that is, the count value latched in the capture register block 700 in FIG. 1 is transferred to the memory 7.

In other words, it is about 8 from the rising edge of the HSW signal in the memory 7.
The data of the register file after ms (R ₁ , R _{2 in} FIG. 7) is taken in. Next, at process block 413, the state variable A is reset to zero.

By repeating the above flow, the amplitude level of the envelope signal after a fixed time from the rising edge of the HSW signal can be always captured in the memory.

Next, about the main flow of auto tracking
This will be described with reference to the flowchart in the figure.

First, the branch 414 determines whether or not auto-tracking is being executed. If yes, the process proceeds to the branch 418, and if not, the process proceeds to the branch 415. Branch 415 determines whether the VTR is in recording mode or playback mode, and branches in playback mode.
Proceeding to step 416, here it is judged whether or not the first switch circuit 31 in FIG. 1 has been pressed by the user. If yes (switch ON), then the procedure advances to processing block 417, where it is set in the memory. The variable B, the memory 6 and the memory 3 are cleared, the variable C is set to 15, and the process proceeds to the branch 420. On the other hand, if the branch 415 and the branch 416 are negative, the program moves to the next program.

Next, depending on the value of the state variable B, branches 420,423,430,444
The flow branches.

First, when B is 0, the processing block 421 is executed by the branch 420.
And in process block 412 of the flow of FIG.
The data of the memory 7 in which the amplitude level of the reproduction envelope signal is fetched is transferred to Acc and stored in the memory 6 again. The state variable B is then incremented to 1 in processing block 422.

When B is 1, the process proceeds to the processing block 424 by the branch 423, and the fifth step is performed to shift the tracking shifter amount by 1 ms.
A tracking amount of 1 m is added to the data in the memory 3 described in the figure.
Subtract the value corresponding to s.

Then, the process proceeds to processing block 425, variable D is set to 2, processing block 426 decrements the value of variable C by 1, and branch 427 determines whether the value of variable C has become 1 or not. For example, in processing block 429, the state variable B is set to 3, and if not, processing block 42
At 8, the state variable B is set to 2.

If B is 2, branch 430 leads to processing block 431 where variable D is decremented by 1, then branch 432
In, it is determined whether the variable D is 0. That is,
Using the variable D, the processing blocks 425, 431 and branch 4
A soft timer is realized by 32, which means that the program delays the time required to pass the processing block 431 twice. This is because it takes time for the capstan motor 6 of FIG. 1 to complete the phase pull-in after shifting the tracking shifter amount by 1 ms in the processing block 424.

Then, after the predetermined time has passed, the process proceeds to the processing block 433,
About 8 ms after the rising edge of the HSW signal after changing the tracking shifter amount, that is, the amplitude level of the reproduction envelope at R in FIG. And H before changing the tracking shifter amount in processing block 421.
The difference between the amplitude level of the reproduction envelope signal about 8 ms after the rising edge of the SW signal and the data in the memory 6 that has been fetched is taken.

Then, in branch 434, it is determined whether the value remaining in Acc is positive or negative. If it is positive, that is, if the envelope signal level after the tracking shifter amount is changed is larger, the processing block 435 transfers the amplitude level of the reproduction envelope signal after the tracking shifter amount is changed to the memory 6 and the tracking is performed. The data of the memory 3 in which the shifter amount is stored is transferred to the memory 8.

That is, the memories 6 and 8 store about 8 ms after the rising edge of the HSW signal up to that point, that is, the maximum envelope signal level in FIG. 7R and the tracking shifter amount at that time.

Next, proceeding to processing block 436, the amplitude level of the reproduction envelope after changing the tracking shifter amount, that is, the memory 7
The difference between the value obtained by adding 1 to and the value in memory 6 is taken, and branch 43
At 7, it is determined whether the difference is a positive number of 2 or less.

That is, it is determined whether or not the absolute value of the difference between the amplitude levels of the reproduction envelopes of the memory 6 and the memory 7 that are continuously captured is 1 or less. If not, processing block 44.
If so, then processing block 438 is entered and memory 10 is incremented.

Next, in the branch 439, when the memory 10 is larger than 3, it proceeds to the processing block 441, and when it is smaller than 3, it proceeds to the processing block 442, and when it is 3, it adds 3 to the tracking shifter amount memory 3 in the processing block 440. Transfer to memory 11. That is,
When the difference between the amplitude levels of the reproduction envelopes is within 1 for three consecutive times, the first continuous tracking shifter amount is stored.

FIG. 9 is a graph showing the relationship between the tracking shifter amount and the amplitude level of the envelope signal when the tracking amount is varied during the reproduction of the triple recording tape. In the case of the triple recording tape, the track width is narrower than that of the standard recording tape, but since the heads having the same width are used, the reproduction envelope signal level has a waveform having a flat portion as shown in FIG. . In addition, considering the image quality and SN ratio, the best point is near the click point in FIG. 9, that is, the point where it begins to become flat. Therefore, the best tracking position is obtained by the processing blocks 436,437,438,439,440 on the triple recording tape.

Next, in processing block 441, memory 10 is cleared,
The processing block 442 transfers the memory 7 to the memory 6. Also, the state variable B is set to 1 in processing block 443.

When B is 3, the flow advances to processing block 445 by branch 444, and the data in the memory 11 in which the best tracking shifter amount in R in FIG. 7 is stored is transferred to Acc.

Next, in branch 446, it is determined whether or not the memory 11 is 0. If yes, the data of the memory 8 in which the tracking shifter amount when the amplitude level of the reproduction envelope signal becomes maximum is stored is transferred to the memory 3, and if not, the memory 11
Is transferred to the memory 3. Then, in processing block 449, the variables B and C and the memory 10 are cleared.

By the above flow, the tracking shifter amount is 1 ms
It is possible to shift five times, compare reproduction envelope signal levels each time, and use the first tracking shifter amount where the difference between three consecutive reproduction envelope signal levels is within 1 as the final tracking shifter amount.

However, when the tracking shifter amount is not detected, the tracking shifter amount which becomes the maximum value of the reproduction envelope signal level about 8 ms after the rising edge of the HSW signal (R in FIG. 7) out of 15 times is the final tracking amount. Use the shifter amount.

As is apparent from the above description, the magnetic recording / reproducing apparatus having the auto-tracking function of the present invention records the frequency-modulated wave signal with the rotary head and the control signal with a constant period by the control head. A head switching signal (HSW signal) indicating the rotational phase of the rotary head and the reproduced control signal when reproducing the recorded signal of the recorded recorded recording medium (represented by the magnetic tape 1 in the embodiment). An error in the phase difference between the reference recording phase and the reference phase is detected (in the embodiment, the phase control means is constituted by the flowchart of FIG. 5), and the running motor for the recorded recording medium is executed based on the error signal. (In the example, the capstan motor 6 is used.)
A magnetic recording / reproducing apparatus for controlling the rotation of the recording medium, the tracking varying means for varying the reference phase (in the embodiment, the tracking varying means is constituted by the processing block 424 of FIG. 8), and the recorded recording. A signal (represented by a detection signal in the embodiment) based on the frequency-modulated wave signal (represented by a reproduction envelope signal in the embodiment) reproduced from the medium is supplied to the head switching signal at a constant phase. Sampling means for sampling (in the embodiment, the sampling means is constituted by the flowchart of FIG. 6), and a plurality of samplings obtained by the sampling means when the reference phase is varied at fixed intervals by the tracking varying means. Comparison means for performing size comparison based on the data (in the embodiment, the processing block of FIG. 433 and 435 and a branch 434) and calculating means for obtaining a difference between the continuous sampling data and comparing the difference (composed of a processing block 436 and a branch 437 of FIG. 8 in the embodiment), Detecting means for detecting that the difference between the data is within a certain value consecutively N times (N ≧ 2, N is an integer) by the comparing means and the calculating means (in the embodiment, the branch of FIG.
437), selecting means for selecting the first sampling point detected by the detecting means (in the embodiment, the processing blocks 438, 441 and branch 439 of FIG. 8), and the selecting means. A data storage means (in the embodiment, which is constituted by processing blocks 435 and 440 in FIG. 8) for taking in the reference phase of the tracking variable means with respect to the obtained sampling point and a reference phase stored in the data storage means It is characterized in that it comprises means for sending it to the tracking means as a reference phase (in the embodiment, it is composed of processing blocks 445, 447, 448 and branch 446 in FIG. 8), and it is characterized by environmental changes such as temperature changes. The so-called compatibility-deteriorated tape recorded on another VTR where the magnetic tape has expanded or contracted or mechanical errors have occurred. It is possible to obtain a magnetic recording / reproducing apparatus that realizes a stable auto-tracking function even with respect to the magnetic field. Of course, it does not require the adjustment volume like the conventional VTR, so it is possible to improve the operability.

[Brief description of drawings]

FIG. 1 is a block diagram of a magnetic recording / reproducing apparatus having an auto-tracking function in one embodiment of the present invention, FIG. 2 is a concrete logic circuit diagram of the capture controller 800 of FIG. 1, and FIG. FIG. 4 is a timing chart for explaining the circuit operation of the figure, FIG. 4 is a block diagram of the capture register block 700, FIGS. 5, 6, and 8 are flowcharts showing the operation of the main part of FIG. 1, and FIG. 6 is a timing chart for explaining the flowchart of FIG. 6, FIG. 9 is a graph showing the relationship between the tracking shifter amount and the reproduction envelope signal level, and FIG. 10 is a block diagram showing the configuration of a servo mechanism during reproduction of a conventional VTR. , FIG. 11 is a timing chart for explaining the operation of the main part of FIG. 1 ... Magnetic tape, 2 ... Cylinder motor, 6 ... Capstan motor, 19 ... Comparator, 100 ... Register, 200 ... RAM, 300 ... ALU, 400 ... Command execution means, 5
00 …… Time base counter, 700 …… Capture register controller, 800 …… Capture controller, 1
000 ROM, 1400 DA converter.

Claims (2)

[Claims] 1. A rotational phase of the rotary head is reproduced when a recorded signal of a recorded recording medium in which a frequency-modulated wave signal is recorded by the rotary head and a control signal of a constant period is recorded by the control head. In a magnetic recording / reproducing apparatus for detecting an error with respect to a reference phase of a phase difference between the head switching signal and the reproduced control signal, and controlling the rotation of a running motor of the recorded recording medium based on the error signal, Tracking variable means for changing the reference phase, sampling means for sampling a signal based on the frequency-modulated signal reproduced from the recorded recording medium with the head switching signal at a constant phase, and reference by the tracking variable means When the phase is varied at regular intervals, Comparing means for performing a magnitude comparison based on the sampling data, computing means for obtaining a difference between the continuous sampling data, and comparing the difference. N times (N ≧ 2; N is an integer) by the comparing means and the computing means. ) Detection means for continuously detecting that the difference between the data is within a predetermined value, selection means for selecting the first sampling point detected by the detection means, and sampling points obtained by the selection means A magnetic recording / reproducing apparatus comprising: a data storage unit for taking in a reference phase of the tracking variable unit; and a unit for sending the reference phase stored in the data storage unit to the tracking variable unit as a final reference phase. 2. The detecting means detects that a difference in voltage level of signals based on the frequency-modulated wave signal reproduced from the recorded recording medium is 40 mv or less at consecutive sampling points. The magnetic recording / reproducing apparatus according to claim 1.