JPH0779086B2 - Crystal growth method - Google Patents
Crystal growth methodInfo
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- JPH0779086B2 JPH0779086B2 JP24171987A JP24171987A JPH0779086B2 JP H0779086 B2 JPH0779086 B2 JP H0779086B2 JP 24171987 A JP24171987 A JP 24171987A JP 24171987 A JP24171987 A JP 24171987A JP H0779086 B2 JPH0779086 B2 JP H0779086B2
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- substrate
- oxide film
- layer
- crystal growth
- growth
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- Drying Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】 [概要] 結晶成長方法のうち、被成長基板の前処理方法に関し、 被成長基板面に出来るだけ薄いバッファ層を形成するこ
とを目的とし、 化合物半導体からなる被成長基板を加熱処理して膜厚15
〜30Åの熱酸化膜を生成し、該熱酸化膜に蒸発原子の分
子線を照射しながら前記被成長基板を加熱して該熱酸化
膜を含む膜厚30〜60Åの基板表面層を除去し、次いで、
前記被成長基板に結晶成長する工程が含まれることを特
徴とする。DETAILED DESCRIPTION OF THE INVENTION [Outline] Among crystal growth methods, the present invention relates to a pretreatment method for a substrate to be grown, which is made of a compound semiconductor for the purpose of forming a buffer layer as thin as possible on the surface of the substrate to be grown. Heat treatment to a film thickness of 15
~ 30 Å thermal oxide film is generated, the substrate to be grown is heated by irradiating the thermal oxide film with a molecular beam of vaporized atoms to remove the substrate surface layer having a thickness of 30 to 60 Å including the thermal oxide film. , Then
It is characterized in that a step of growing crystals on the substrate to be grown is included.
[産業上の利用分野] 本発明は結晶成長方法のうち、特に被成長基板の前処理
方法に関する。[Field of Industrial Application] The present invention relates to, among crystal growth methods, a pretreatment method for a substrate to be grown.
半導体装置を製造する際、結晶基板に沿つて半導体膜を
エピタキシャル成長するエピタキシー法は必須の基礎技
術であるが、特に、III−V属の化合物半導体層をエピ
タキシャル成長して、高性能半導体素子を作成する研究
が盛んにおこなわれており、例えば、GaAs/AlGaAs・InP
/InGaAs系などのヘテロ接合構造を形成し、このヘテロ
構造を利用した超高速デバイスや光デバイスが開発され
つつある。When manufacturing a semiconductor device, an epitaxy method of epitaxially growing a semiconductor film along a crystal substrate is an indispensable basic technique, but in particular, a III-V group compound semiconductor layer is epitaxially grown to produce a high-performance semiconductor device. Research is being actively conducted, for example, GaAs / AlGaAs / InP.
An ultra-high speed device and an optical device using a heterojunction structure such as / InGaAs system are being developed.
そのような化合物半導体層をエピタキシャル成長する方
法として、分子線結晶成長(MBE)法が開発されてお
り、これは急峻な接合が形成できる成長法として知られ
ている。しかし、高品位な結晶成長層を得るためには、
その基盤となる結晶基板面の品質が極めて重要である。A molecular beam crystal growth (MBE) method has been developed as a method for epitaxially growing such a compound semiconductor layer, and this is known as a growth method capable of forming a steep junction. However, in order to obtain a high-quality crystal growth layer,
The quality of the surface of the crystal substrate which is the basis of this is extremely important.
[従来の技術] 第5図はMBE法を適用するガスソース分子線結晶成長装
置の概要を示しており、1は真空成長容器、2は被成長
基板(ウエハー),3はMo(モリブデン)ステージ,4はヒ
ータ,5は分子線源セル,6はシャッタ,7は液体窒素シュラ
ウド,8はゲートバルブである。このうち、被成長基板2
はMoステージ3に保持され、ヒータ4で加熱されて、例
えば、被成長基板2がGaAs基板の場合には600〜700℃に
加熱される。且つ、分子線源セルは複数個が設けられ、
例えば、HEMTなどのGaAsデバイスを成長させる場合に
は、As分子線源セル,Ga分子線源セルその他の分子線源
セルが被成長基板2に対向して配置されている。[Prior Art] FIG. 5 shows an outline of a gas source molecular beam crystal growth apparatus to which the MBE method is applied. 1 is a vacuum growth container, 2 is a substrate to be grown (wafer), 3 is a Mo (molybdenum) stage. Reference numeral 4 is a heater, 5 is a molecular beam source cell, 6 is a shutter, 7 is a liquid nitrogen shroud, and 8 is a gate valve. Of these, the growth substrate 2
Is held on the Mo stage 3 and heated by the heater 4, and is heated to 600 to 700 ° C. when the growth substrate 2 is a GaAs substrate, for example. Moreover, a plurality of molecular beam source cells are provided,
For example, when growing a GaAs device such as HEMT, an As molecular beam source cell, a Ga molecular beam source cell and other molecular beam source cells are arranged to face the substrate 2 to be grown.
このような結晶成長装置を用いて、被成長基板に分子線
エピタキシャル成長を行なう場合、被成長基板の成長面
を清浄にする前処理がおこなわれており、例えば、被成
長基板がGaAs基板の場合は、真空中において被成長基板
を約300〜400℃で加熱して、表面に付着していた水分を
除去し、更に、成長直前には約600℃で3〜5分間加熱
して基板表面の自然酸化膜を除去し、しかる後、所要の
結晶成長層の成長をおこなつている。このような水分と
自然酸化膜(膜厚10Å程度)を除去するのが、従来の前
処理方法である。When molecular beam epitaxial growth is performed on a growth substrate using such a crystal growth apparatus, pretreatment for cleaning the growth surface of the growth substrate is performed. For example, when the growth substrate is a GaAs substrate, In a vacuum, the substrate to be grown is heated at about 300-400 ℃ to remove the moisture adhering to the surface, and immediately before growth, it is heated at about 600 ℃ for 3-5 minutes to keep the surface of the substrate natural. The oxide film is removed, and then the required crystal growth layer is grown. The conventional pretreatment method is to remove such moisture and natural oxide film (film thickness of about 10Å).
[発明が解決しようとする問題点] しかし、上記の前処理方法では水分や酸素の除去はでき
ても、炭化水素や二酸化炭素として基板面に付着してい
る炭素(C)を除去することはできない。このような炭
化水素や二酸化炭素は真空成長容器の内部あるいは大気
中から飛来して付着する。[Problems to be Solved by the Invention] However, although the above pretreatment method can remove water and oxygen, it does not remove carbon (C) adhering to the substrate surface as hydrocarbons or carbon dioxide. Can not. Such hydrocarbons and carbon dioxide fly from the inside of the vacuum growth container or the atmosphere and adhere.
そのように、GaAs基板表面に炭素が付着した状態で、そ
の面に結晶成長層をエピタキシャル成長すると、炭素原
子がGaAs中に混入してアクセプタ(p型)として働き、
GaAs基板と結晶成長層との間に界面準位を形成して、デ
バイス特性を害することになる。Thus, when carbon is attached to the surface of the GaAs substrate and a crystal growth layer is epitaxially grown on that surface, carbon atoms mix into GaAs and act as acceptors (p-type),
An interface state is formed between the GaAs substrate and the crystal growth layer, which impairs device characteristics.
従来、この界面準位の影響を回避するために、1μm近
い膜厚の厚いバッファ層を形成しているが、この厚いバ
ッファ層を設けることは結晶成長処理の工数が嵩み、そ
れだけスループットを低下させることになり、且つ、デ
バイス特性を劣化させる原因になる。Conventionally, in order to avoid the effect of this interface state, a thick buffer layer having a film thickness of about 1 μm is formed. However, providing this thick buffer layer increases the man-hours for crystal growth processing, and thus lowers the throughput accordingly. And cause deterioration of device characteristics.
本発明は基板面に出来るだけ薄いバッファ層を形成する
ことを目的とした結晶成長法の前処理方法を提案するも
のである。The present invention proposes a pretreatment method of a crystal growth method for the purpose of forming a buffer layer as thin as possible on a substrate surface.
[問題点を解決するための手段] その目的は、第1図の原理を説明する図に示すように、
化合物半導体からなる被成長基板10を加熱処理して膜厚
15〜30Åの熱酸化膜12を生成し、該熱酸化膜に蒸発原子
の分子線を照射しながら前記被成長基板を加熱して該熱
酸化膜を含む膜厚30〜60Åの酸化膜基板遷移層11を除去
し、次いで、前記被成長基板に結晶成長する工程が含ま
れる結晶成長方法によつて達成される。[Means for Solving Problems] The purpose thereof is as shown in the diagram for explaining the principle of FIG.
The growth substrate 10 made of a compound semiconductor is heat-treated to form a film
A thermal oxide film 12 of 15 to 30 Å is generated, and the growth substrate is heated while irradiating the thermal oxide film with a molecular beam of vaporized atoms, and an oxide film substrate transition of 30 to 60 Å including the thermal oxide film. This is accomplished by a crystal growth method that includes the steps of removing layer 11 and then crystal growing on the substrate to be grown.
[作用] 即ち、本発明は、薄い熱酸化膜を生成して、この熱酸化
膜を含む基板表面層を蒸発原子の分子線で照射しながら
被成長基板を加熱して除去する。そうすれば、表面に付
着した炭素原子も除かれ、清浄で結晶性の良い表面が表
われて、その表面に結晶成長層をエピタキシャル成長す
れば、結晶品質の良い成長層が得られる。[Operation] That is, according to the present invention, a thin thermal oxide film is formed, and the substrate to be grown is heated and removed while the substrate surface layer including the thermal oxide film is irradiated with a molecular beam of vaporized atoms. Then, the carbon atoms attached to the surface are removed, and a clean and well-crystallized surface appears. If a crystal growth layer is epitaxially grown on the surface, a growth layer with good crystal quality can be obtained.
[実施例] 以下、図面を参照して実施例によつて詳細に説明する。[Examples] Hereinafter, examples will be described in detail with reference to the drawings.
上記の被成長基板10をGaAs基板とし場合、膜厚15〜30Å
の熱酸化膜12はGa2O3の多いGa2O3・As2O3膜で、熱酸化
膜12とほぼ同じ膜厚15〜30Åの酸化膜基板遷移層11はAs
の多いGaAsの層である。従つて、本発明では膜厚15〜30
Åの薄い熱酸化膜とその下層の膜厚15〜30Åの結晶品質
の悪い酸化膜基板遷移層を除去するものである。When the above-mentioned substrate 10 to be grown is a GaAs substrate, the film thickness is 15 to 30 Å
The thermal oxide film 12 of is a Ga 2 O 3 · As 2 O 3 film containing a large amount of Ga 2 O 3 , and the oxide film substrate transition layer 11 having a thickness of 15 to 30 Å, which is almost the same as the thermal oxide film 12,
It is a layer of GaAs with a large amount. Therefore, in the present invention, the film thickness of 15 to 30
It removes a thin Å thermal oxide film and an underlying oxide film substrate transition layer of 15-30 Å film thickness with poor crystal quality.
さて、表面に付着した炭素原子を除去するためには、そ
の部分を熱酸化して熱酸化膜を除去すれば良いが、この
熱酸化膜を出来るだけ薄く形成して除去する方法が望ま
しい。厚い膜厚の熱酸化膜を除去すれば、表面に凹凸が
できて表面荒れを生じ、それが著しいと結晶成長層の品
質が低下することになるからである。そのために実験し
て求めたGaAs基板の加熱温度に対する酸化膜厚(縦軸)
と加熱時間(横軸)の関係図を第2図に示している。同
図より10〜30分の加熱時間の間に酸化膜厚は飽和し、且
つ、加熱時間10分までは加熱温度が高いほど膜厚の増加
が大きいことが判る。従つて、これより加熱温度が低い
ほど酸化膜厚の再現性が良いと考えられ、且つ、酸化膜
厚を薄くするためには低温加熱が適切で、加熱温度300
〜350℃では5〜10分でほぼ酸化膜の生成が飽和してい
る。この加熱条件での表面状態を測定したところ、酸化
膜厚(酸素存在の深さ)は15〜30Å,酸化膜基板遷移層
(結晶の乱れある層)も15〜39Åであることが判つた。Now, in order to remove the carbon atoms attached to the surface, it is sufficient to thermally oxidize that portion to remove the thermal oxide film, but it is desirable to form this thermal oxide film as thin as possible and remove it. This is because, if the thick thermal oxide film is removed, the surface becomes rough, and the surface becomes rough, and if it is remarkable, the quality of the crystal growth layer will deteriorate. For that purpose, the oxide film thickness (vertical axis) with respect to the heating temperature of the GaAs substrate was obtained experimentally.
FIG. 2 shows the relationship between the heating time and the heating time (horizontal axis). From the figure, it can be seen that the oxide film thickness is saturated during the heating time of 10 to 30 minutes, and that the film thickness increases more as the heating temperature increases up to the heating time of 10 minutes. Therefore, it is considered that the lower the heating temperature is, the better the reproducibility of the oxide film thickness is. Moreover, the low temperature heating is suitable for thinning the oxide film thickness, and the heating temperature 300
At ˜350 ° C., the oxide film formation is almost saturated in 5 to 10 minutes. When the surface condition was measured under these heating conditions, it was found that the oxide film thickness (depth of oxygen existence) was 15 to 30Å and the oxide film substrate transition layer (layer with disordered crystal) was 15 to 39Å.
一方、反射型高速電子線回折(RHEED)法による観測で
は、熱酸化膜は真空中において620〜640℃以上,3〜5分
間程度の加熱処理によつて蒸発して除去されることが明
らかとなつている。On the other hand, the observation by the reflection type high-energy electron diffraction (RHEED) method revealed that the thermal oxide film is evaporated and removed by the heat treatment in vacuum at 620 to 640 ° C or higher for 3 to 5 minutes. I'm running.
次に、このデータに基づいて、MBE法を用いてGaAs基板
上に、第3図に示すような選択ドープGaAs/n−AlGaAsヘ
テロ構造を成長した実施例について説明する。第3図に
おいて、20は半絶縁性GaAs基板,21はGaAsバッファ層,22
はAlGaAsスペーサ層,23はn−AlGaAs電子供給層,24はn
−GaAsコンタクト層で、これはHEMT用のヘテロ構造であ
る。まず、GaAs基板20を350℃に加熱したホットプレー
ト上に載せて、大気中で10分間加熱して膜厚15〜30Åの
熱酸化膜を基板表面に生成する。Next, based on this data, an example in which a selectively doped GaAs / n-AlGaAs heterostructure as shown in FIG. 3 is grown on a GaAs substrate using the MBE method will be described. In FIG. 3, 20 is a semi-insulating GaAs substrate, 21 is a GaAs buffer layer, 22
Is an AlGaAs spacer layer, 23 is an n-AlGaAs electron supply layer, and 24 is n
-GaAs contact layer, which is a heterostructure for HEMTs. First, the GaAs substrate 20 is placed on a hot plate heated to 350 ° C. and heated in the atmosphere for 10 minutes to form a thermal oxide film having a film thickness of 15 to 30 Å on the substrate surface.
次いで、このGaAs基板20をMoステージに貼着して、前記
ガスソース分子線結晶成長装置(第5図参照)に挿入
し、基板準備室(ゲートバルブ8の右側にあり、図示し
ていない)において400℃,10分間加熱して水分を除去す
る。次に、真空成長容器1に移し、As分子線を照射しな
がら680℃(結晶成長時の基板加熱温度)に加熱して10
分間保持し、膜厚30〜60Åの熱酸化膜を含む基板表面層
を除去する。このAs分子線を照射する目的は温度680℃
においてAsが蒸発し易いから、それを抑えるためであ
る。Next, this GaAs substrate 20 is attached to a Mo stage, inserted into the gas source molecular beam crystal growth apparatus (see FIG. 5), and a substrate preparation chamber (on the right side of the gate valve 8 and not shown). Heat at 400 ° C for 10 minutes to remove water. Next, it is transferred to the vacuum growth container 1 and heated to 680 ° C. (substrate heating temperature during crystal growth) while irradiating with As molecular beam.
Hold for minutes to remove the substrate surface layer including the thermal oxide film with a thickness of 30 to 60Å. The purpose of irradiating this As molecular beam is 680 ℃
This is because As is likely to evaporate, so that As is suppressed.
次いで、温度680℃に保持したまま、第3図に示す選択
ドープGaAs/n−AlGaAsヘテロ構造を成長する。これはHE
MT用結晶成長層で、GaAsバッファ層の膜厚を変化させた
ものを成長し、その膜厚および他の成長層のデータを次
の通りにする。Then, while maintaining the temperature at 680 ° C., the selectively-doped GaAs / n-AlGaAs heterostructure shown in FIG. 3 is grown. This is HE
A crystal growth layer for MT is grown by changing the film thickness of the GaAs buffer layer, and the data of the film thickness and other growth layers are as follows.
GaAsバッファ層21;膜厚0.1,0.2,0.4μmAlxGa1-xAsスペ
ーサ層22;膜厚60Å,x=0.3n−AlxGa1-xAs電子供給層23;
膜厚900Å, x=0.3 不純物濃度1018/cm3 n−GaAsコンタクト層24;膜厚100Å, 不純物濃度1018/cm3 このように、バッファ層21の膜厚を0.1,0.2,0.4μmに
変化させているが、従来のバッファ層の膜厚は0.6μm
であり、従来の前処理によつてバッファ層21の膜厚を0.
1,0.2,0.4,0.6μmに変化させたデータも作成してい
る。GaAs buffer layer 21; thickness 0.1,0.2,0.4μmAl x Ga 1-x As spacer layer 22; thickness 60Å, x = 0.3n-Al x Ga 1-x As electron supply layer 23;
Film thickness 900Å, x = 0.3 Impurity concentration 10 18 / cm 3 n-GaAs contact layer 24; Film thickness 100Å, Impurity concentration 10 18 / cm 3 Thus, the thickness of the buffer layer 21 is 0.1, 0.2, 0.4 μm. Although changing, the thickness of the conventional buffer layer is 0.6 μm
Therefore, the film thickness of the buffer layer 21 is reduced to 0 by the conventional pretreatment.
We have also created the data that changed to 1,0.2,0.4,0.6μm.
この結晶構造の試料によつて測定したデータを第5図に
示しており、第5図はバッファ層の膜厚(縦軸)に対す
る二次電子ガスの電子移動度(左縦軸)およびシート電
子濃度(右縦軸)の関係図で、ホール測定は77°kでお
こなつたものである。The data measured by the sample having this crystal structure is shown in FIG. 5, which shows the electron mobility (second vertical axis) of the secondary electron gas and the sheet electron with respect to the film thickness of the buffer layer (vertical axis). In the relationship diagram of concentration (right vertical axis), Hall measurement is performed at 77 ° k.
第5図において、黒丸,黒三角は本発明を適用した上記
試料における電子移動度(黒丸),シート電子濃度(黒
三角)、白丸,白三角は従来の前処理法を適用した電子
移動度(白丸),シート電子濃度(白三角)であり、こ
れより、本発明にかかる前処理方法を適用すれば、バッ
ファ層の膜厚を0.2μmとした場合、電子移動度85000cm
2/Vs,シート電子濃度5×1011/cm2となり、従来のバッ
ファ層の膜厚を0.6μmとした場合に比べて遜色のない
特性を有している。且つ、バッファ層の膜厚を薄くする
と、結晶成長層全体の膜厚が薄くなり、成長過程で発生
する結晶欠陥が減少して、欠陥密度は約1/2に低減され
る利点があり、更に、表面のモホロジー(表面粗さ)も
結晶成長には問題なく良好である。ちなみに、従来の前
処理法によつて膜厚0.2μmのバッファ層を形成する
と、電子移動度48000cm2/Vs,シート電子濃度3.3×1011
/cm2の値しか得られず、これは基板と結晶成長層の界
面における電子トラップの影響によるものと解釈され
る。In FIG. 5, black circles and black triangles represent electron mobility (black circles), sheet electron density (black triangles), white circles and white triangles in the above sample to which the present invention is applied, and white circles and white triangles represent electron mobility (conventional pretreatment method). (White circles) and sheet electron density (white triangles). From this, when the pretreatment method according to the present invention is applied, the electron mobility is 85000 cm when the thickness of the buffer layer is 0.2 μm.
2 / Vs, sheet electron concentration is 5 × 10 11 / cm 2 , which is comparable to the conventional buffer layer thickness of 0.6 μm. Moreover, when the thickness of the buffer layer is reduced, the thickness of the entire crystal growth layer is reduced, and the crystal defects generated in the growth process are reduced, which has the advantage that the defect density is reduced to about 1/2. The surface morphology (surface roughness) is also good for crystal growth without problems. By the way, if a buffer layer having a thickness of 0.2 μm is formed by the conventional pretreatment method, the electron mobility is 48000 cm 2 / Vs, and the sheet electron concentration is 3.3 × 10 11
Only a value of / cm 2 is obtained, which is interpreted to be due to the effect of electron traps at the interface between the substrate and the crystal growth layer.
従つて、本発明によれば界面のトラップは減少し、薄い
バッファ層を形成しても良質の結晶成長層が得られ、例
えば、HEMTのような電子デバイスでは、動作時に基板バ
イアス効果を除去することができる。このように、本発
明を適用して薄いバッファ層を設けると、結晶成長処理
工数が減少してスループットが向上すると共に、デバイ
ス特性が改善される効果がある。Therefore, according to the present invention, interface traps are reduced, and a good crystal growth layer can be obtained even if a thin buffer layer is formed. For example, in an electronic device such as HEMT, the substrate bias effect is removed during operation. be able to. As described above, when the present invention is applied to provide a thin buffer layer, the number of man-hours for crystal growth treatment is reduced, throughput is improved, and device characteristics are improved.
上記はGaAs基板を実施例とし、蒸発し易い原子のAs分子
線を照射しながら加熱した例であるが、本発明はその他
の化合物半導体基板、例えばInP基板やInSb基板にも適
用でき、その場合の照射分子線は燐(P)やアンチモニ
ー(Sb)である。The above is an example in which the GaAs substrate is used as an example and is heated while irradiating the As molecular beam of atoms that easily evaporate, but the present invention can be applied to other compound semiconductor substrates, for example, InP substrate and InSb substrate. The irradiation molecular beam of is phosphorus (P) or antimony (Sb).
[考案の効果] 以上の説明から明らかなように、本発明にかかる結晶成
長法の前処理によれば、膜厚の薄いバッファ層を設け
て、スループットが向上し、且つ、高品質な結晶成長層
がえられて、電子デバイスや光デバイスの性能向上に貢
献するものである。[Effects of the Invention] As is clear from the above description, according to the pretreatment of the crystal growth method according to the present invention, a buffer layer having a small film thickness is provided, the throughput is improved, and high-quality crystal growth is achieved. The layers are provided to contribute to improving the performance of electronic devices and optical devices.
第1図は本発明にかかる原理を説明する図、 第2図は加熱温度に対する酸化膜厚と加熱時間の関係
図、 第3図は本発明を適用するヘテロ構造の断面図、 第4図は第3図の実施例におけるバッファ層膜厚と電子
移動度,シート電子濃度の関係図、 第5図はガスソース分子線結晶成長装置の概要図であ
る。 図において、 1は真空成長容器、2は被成長基板、3はMoステージ、
4はヒータ、5は分子線源セル、8はゲートバルブ、10
は被成長基板、11は酸化膜基板遷移層、12は熱酸化膜、
20は半絶縁性GaAs基板、21はGaAsバッファ層、22はAlGa
Asスペーサ層、23はn−AlGaAs電子供給層、24はn−Ga
Asコンタクト層を示している。FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a relational diagram of oxide film thickness and heating time with respect to heating temperature, FIG. 3 is a sectional view of a heterostructure to which the present invention is applied, and FIG. FIG. 3 is a relationship diagram of the buffer layer film thickness, electron mobility and sheet electron concentration in the embodiment of FIG. 3, and FIG. 5 is a schematic diagram of a gas source molecular beam crystal growth apparatus. In the figure, 1 is a vacuum growth container, 2 is a substrate to be grown, 3 is a Mo stage,
4 is a heater, 5 is a molecular beam source cell, 8 is a gate valve, 10
Is a growth substrate, 11 is an oxide film substrate transition layer, 12 is a thermal oxide film,
20 is a semi-insulating GaAs substrate, 21 is a GaAs buffer layer, 22 is AlGa
As spacer layer, 23 is n-AlGaAs electron supply layer, 24 is n-Ga
The As contact layer is shown.
Claims (2)
理して膜厚15〜30Åの熱酸化膜を生成し、該熱酸化膜に
蒸発原子の分子線を照射しながら前記被成長基板を加熱
して該熱酸化膜を含む膜厚30〜60Åの基板表面層を除去
し、次いで、前記被成長基板に結晶成長する工程が含ま
れてなること特徴とする結晶成長方法。1. A growth substrate made of a compound semiconductor is heat-treated to form a thermal oxide film having a film thickness of 15 to 30 Å, and the growth substrate is heated while irradiating the thermal oxide film with a molecular beam of vaporized atoms. Then, a step of removing the substrate surface layer having a film thickness of 30 to 60 Å including the thermal oxide film and then performing crystal growth on the substrate to be grown is included.
線はAs分子線からなることを特徴とする特許請求の範囲
第1項記載の結晶成長方法。2. The crystal growth method according to claim 1, wherein the compound semiconductor is GaAs and the molecular beam of vaporized atoms is an As molecular beam.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24171987A JPH0779086B2 (en) | 1987-09-25 | 1987-09-25 | Crystal growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24171987A JPH0779086B2 (en) | 1987-09-25 | 1987-09-25 | Crystal growth method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6482611A JPS6482611A (en) | 1989-03-28 |
| JPH0779086B2 true JPH0779086B2 (en) | 1995-08-23 |
Family
ID=17078518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24171987A Expired - Fee Related JPH0779086B2 (en) | 1987-09-25 | 1987-09-25 | Crystal growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0779086B2 (en) |
-
1987
- 1987-09-25 JP JP24171987A patent/JPH0779086B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 第46回応明物理学会学術講演予稿集(1985)P.6473a−F−4 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6482611A (en) | 1989-03-28 |
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