JPH0779105B2 - Wiring forming method for semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a wiring forming method for a semiconductor device suitable for forming wiring on a semiconductor substrate on which a base having a step portion is formed.

[Prior Art] When a plurality of wirings are formed adjacent to each other so as to intersect with the step portion in the manufacturing of a semiconductor device, anisotropic dry etching is used to form a wiring material layer. When patterned, the etching residue easily occurs in the step portion.

2 (a) and 2 (b) are views for explaining the state of occurrence of this etching residue. FIG. 2 (a) is a partial plan view of the semiconductor device, and FIG. 2 (b) is a plan view. 2 is a perspective view showing a part of the semiconductor device shown in FIG. Second
As shown in FIGS. (A) and (b), the wiring 22 is a semiconductor substrate.
It is formed so as to intersect with the step portion 21a of the base formed on 21. When the wiring 22 is formed by performing anisotropic etching such as RIE using the photoresist as a mask, the etching residue 22a as shown in the figure is likely to appear at the step portion 21a at the end of the etching.

Such an etching residue 22a causes a short circuit between wirings when the wirings 22 are formed adjacent to each other.
When forming 22, it is necessary to prevent the etching residue 22a from occurring.

FIGS. 3A and 3B show the above-mentioned etching residue 22.
It is a perspective view which shows the conventional wiring formation method for suppressing generation | occurrence | production of a in process order.

First, as shown in FIG. 3A, a wiring material 32 is deposited on the semiconductor substrate 31 on which the step portion 31a is formed, and a photoresist 33 is applied on the wiring material 32 to form a desired material. Transfer the wiring pattern of. Next, as shown in FIG. 3B, isotropic etching is performed using the photoresist 33 as a mask, whereby the wiring material 32 is patterned to form a predetermined wiring 34. At this time, the wiring 34 is overhanged so that the undercut 34a is inserted from the pattern end of the photoresist 33 by the dimension a, whereby
Etching residue is prevented from occurring in the step portion 31a.

4A to 4C are perspective views showing another conventional wiring forming method for preventing the occurrence of etching residue in the order of steps. First, as shown in FIG. 4 (a), a wiring material is adhered and formed on a semiconductor substrate 41 on which an underlayer having a step portion 41a is formed, and a first photoresist 43 is formed by coating on the wiring material. Then, the wiring pattern is transferred. continue,
Using the first photoresist 43 as a mask, anisotropic dry etching is performed to form the wiring 42 having a predetermined pattern. At this time, an etching residue 42a of the wiring material is generated in the step portion 41a (first photolithography step).

Next, as shown in FIG. 4B, after peeling off the first photoresist 43 on the wiring 42, a second photoresist 44 is newly applied and formed on the substrate, and a normal photolithography technique is used. By using, for example, the second photoresist 44 so that the etching residue 42a between the adjacent wirings is exposed.
An opening 44a is formed in the.

Next, isotropic etching is performed by using the second photoresist 44 as a mask to remove the etching residue 42a of the step portion 41a, and then the second photoresist 44 is removed, as shown in FIG. Wiring having a shape as shown in
Get 42. In this method, the etching residue 42a slightly remains after the isotropic etching, but in this state, the inconvenience such as the short circuit between the wirings is sufficiently avoided.

[Problems to be Solved by the Invention] However, the above-described conventional wiring forming method has the following problems.

That is, in the case of the conventional method shown in FIG.
In order to sufficiently remove the etching residue using a, it is necessary to undercut the wiring member 32 adhered to the side surface of the step portion 31a by approximately the film thickness. Therefore, it is necessary to set the pattern width of the wiring 34 thicker in advance by taking into account the undercut. Further, the larger the amount of undercut, the worse the controllability of the dimension, so that the variation in the pattern dimension inevitably increases. From the above, in the case of this conventional method, it is difficult to form fine wiring.

In addition, as in the conventional method shown in FIG.
When a second photolithography step is added to remove 42a, the minimum size of the opening 44a that can be formed by this second photolithography step and the second dimension
The wiring interval cannot be made smaller than the dimension including the margin of the alignment accuracy with respect to the wiring pattern in the photolithography process. For this reason, it is still difficult to form fine wiring by this conventional method.

The present invention has been made in view of such problems,
An object of the present invention is to provide a wiring forming method for a semiconductor device, which can easily form a fine wiring pattern while avoiding a short circuit between wirings.

[Means for Solving the Problem] A method for forming a wiring of a semiconductor device according to the present invention includes a step of depositing a wiring material on a semiconductor substrate on which an underlayer having a step portion is formed, and patterning on the wiring material. A step of forming a wiring having a predetermined pattern by etching the wiring material using the first photoresist as a mask; and a step of coating and forming a second photoresist on the first photoresist and the semiconductor substrate. , The second
Exposing the whole surface of the photoresist and developing the photoresist to leave the side surface portion of the wiring and remove the second photoresist in other portions, and masking the first photoresist and the remaining second photoresist. And a step of etching away the portion of the wiring material remaining in the step portion.

[Operation] According to the present invention configured as described above, the entire surface exposure and development are performed on the first photoresist and the second photoresist formed on the semiconductor substrate. As a result, the second photoresist remains on the side surface of the wiring, and the other portion is removed. Therefore, the first and second side surfaces of the wiring are respectively aligned without alignment with the wiring pattern.
And a second photoresist can be left behind and this first
And, by removing the etching residue of the wiring material remaining in the step portion using the second photoresist as a mask, unlike the conventional case where a photoresist having an opening in the etching residue is formed, alignment accuracy is improved. The etching residue can be removed without considering the margin required for the above and without being restricted by the minimum size of the opening.

Therefore, according to the present invention, it is possible to sufficiently prevent the occurrence of a short circuit between the wirings and to narrow the distance between the wirings and to keep the pattern width small, so that the wiring having the fine pattern can be easily formed. You can

Embodiments Embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

FIGS. 1A to 1E are perspective views showing the method of this embodiment in the order of steps. Each drawing shows a part of the layer structure formed in each step.

First, as shown in FIG. 1 (a), a polycrystalline silicon film is deposited on the substrate 11 as a wiring material in order to form the wiring 12 on the underlying semiconductor substrate 11 having the step portion 11a. A first photoresist 13 containing, for example, a novolac-based resin as a main component is applied and formed on the substrate, and a desired wiring pattern is transferred to the first photoresist 13. Then, the first photoresist 13
The wiring 12 is formed by anisotropically etching the polycrystalline silicon film using as a mask. Then, the first
By performing isotropic etching using the photoresist 13 as a mask, the wiring 12 is etched so that the wiring 12 is slightly undercut with respect to the first photoresist 13. In this case, the etching amount and its variation can be sufficiently controlled by suppressing the etching amount to a slight amount. At this time, the stepped portion 11a
Although there is a slight reduction in the degree as compared with the stage where anisotropic etching is performed, there is still the etching residue 12a of the polycrystalline silicon film.

Next, as shown in FIG. 1B, a second photoresist 14 containing, for example, polymethylmethacrylate as a main component is applied and formed on the entire surface of the substrate.

Then, as shown in FIG. 1C, the second photoresist 14 is irradiated with deep ultraviolet rays to be exposed on the entire surface. In this case, the novolac resin (first photoresist 13) is polymethylmethacrylate (second photoresist 1).
Greater absorption of far-ultraviolet light than 4). Therefore, the first
In the portion of the second photoresist 14 that has entered the undercut in the lateral lower portion of the photoresist 13, the amount of exposure is significantly reduced, and it becomes substantially the unexposed portion 14b. In the second photoresist 14, the exposed portion 14a extends from the surface of the second photoresist 14 to a predetermined depth.

Then, the second photoresist 14 is formed under the predetermined developing condition.
When the developing process is applied to the exposed portion 14a, the exposed portion 14a shown in FIG.
Only this is removed, and the unexposed portion 14b remains on the side surface of the wiring 12, as shown in FIG. Therefore, wiring 12
Are the first photoresist 13 and the second photoresist on the top and side, respectively.
The photoresist 14 is covered with the unexposed portion 14b. Further, at this time, the etching residue 12a remaining in the step portion 11a is exposed.

Thereafter, as shown in FIG. 1 (e), the substrate is exposed by isotropic etching using the first photoresist 13 and the unexposed portion 14b of the second photoresist 14 as a mask. The etching residue 12a is removed. Then, the unexposed portions 14b of the first photoresist 13 and the second photoresist 14 are removed. In this state, the etching residue 12a is only a small portion masked by the unexposed portion 14b of the second photoresist 14.

Although polycrystalline silicon is used as the wiring material in the above-described embodiments, aluminum (Al) or the like may be used as the wiring material.

As the second photoresist 14, in addition to the resist material containing polymethylmethacrylate as a main component, for example, a resist material containing polyglycidylmethacrylate as a main component can be used. Also in this case, in the far-ultraviolet exposure process and the development process, by appropriately setting the exposure condition and the development condition, respectively, the photoresist does not remain on the stepped portion 11a of the base, and the side surface of the first photoresist 13 is prevented. Undercut part at the bottom, that is, wiring
It is possible to sufficiently leave the unexposed portion 14b only on the side surface of 12.

[Effects of the Invention] As described above, according to the present invention, the entire surface of the second photoresist is exposed and developed, so that a part of the side surface of the wiring is left and the other is removed. Since the etching residue of the wiring material remaining in the underlying step portion is removed by etching using the remaining second photoresist and the first photoresist as a mask, alignment accuracy in the case where a photolithography process is added as in the conventional case There is no dimensional restriction due to the above, and it is not necessary to consider the dimensional prospective amount in the case of etching under the condition that a large undercut occurs. Therefore, the wiring having the fine pattern can be easily formed.
At the same time, even when the wiring is miniaturized, the remaining wiring material can be effectively removed by etching, so that it is possible to easily obtain a high-quality fine wiring without a short circuit between the wirings.

[Brief description of drawings]

1 (a) to 1 (e) are perspective views for explaining the method of the embodiment of the present invention in the order of steps, and FIGS. 2 (a) and 2 (b) are diagrams showing the etching residue of the wiring material in the step portion of the semiconductor substrate FIG. 2 (a) is a diagram showing a state of occurrence, and FIG.
FIG. 2 (b) is a perspective view showing a part of it,
FIGS. 3A and 3B are perspective views showing the first conventional method in the order of steps, and FIGS. 4A to 4C are perspective views showing the second conventional method in the order of steps. 11,21,31,41; semiconductor substrate, 11a, 21a, 31a, 41a; stepped portion, 1
2,22,34,42; Wiring, 12a, 22a, 42a; Etching residue, 13,4
3; first photoresist, 14, 44; second photoresist, 14a; exposed portion, 14b; unexposed portion, 32; wiring material, 33; photoresist, 34a; undercut, 44a; opening

Claims (1)

[Claims] 1. A step of depositing a wiring material on a semiconductor substrate on which an underlayer having a step portion is formed, and the wiring material is etched by using the patterned first photoresist as a mask. A step of forming a wiring having a predetermined pattern; a step of coating and forming a second photoresist on the first photoresist and the semiconductor substrate; and a step of subjecting the second photoresist to overall exposure and development to obtain the wiring. A side surface of the wiring material is removed to remove the second photoresist in the other area, and the wiring material remaining in the step portion using the first photoresist and the remaining second photoresist as a mask. And a step of removing the portion by etching.