JPH0779150B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention has a lead frame, and by improving the shape of the lead frame, the influence of power supply noise due to transient current is mitigated. The present invention relates to such a semiconductor integrated circuit.

(Prior Art) An integrated circuit device in which a large number of semiconductor elements are assembled to have one function, so-called IC, is formed by encapsulating a semiconductor chip having a large number of elements in an envelope. . A plurality of pad electrodes are provided on the semiconductor chip for inputting / outputting signals, supplying power supply voltage, and the like.

FIG. 5 is a block diagram of a circuit constructed on a typical memory IC chip. An address signal is input to the address pad electrode 11 from the outside of the chip. The address signal input to the pad electrode 11 is input to the address decoder 13 via the address buffer 12, and the data is read from the address of the memory circuit 14 according to the decode output of the address decoder 13. The data read from the memory circuit 14 is amplified by the sense amplifier 15 and further supplied to the output buffer 17 via the output circuit 16. Then, data is output from the output buffer 17 to the outside through the pad electrode 18 for data output.

By the way, in order to operate this memory IC chip, it is necessary to apply a power supply voltage and a reference voltage from the outside. Of these, the high-potential power supply voltage V _CC is applied to the power supply pad electrode 19, and two types of ground voltage reference voltages, V _SS 1 and V _SS 2, are dedicated power supply pad electrodes 20 and 21, respectively. Applied to. A load capacitance 24 is parasitically attached to the data output pad electrode 18.

Here, the power supply voltage applied to the power supply pad electrode 19
V _CC is an internal circuit 22 including an address buffer 12, an address decoder 13, a memory circuit 14 and a sense amplifier 15,
It is commonly supplied to the peripheral circuit 23 including the output circuit 16 and the output buffer 17. However, regarding the reference voltage,
Two kinds of voltages, V _SS 1 and V _SS 2, are independently supplied to the internal circuit 22 and the peripheral circuit 23. The reason for this is as follows.

There are various types of memory ICs, but typical SRAM
In many cases (static type RAM), ROM, etc., the output data is multi-bit, and generally 8 bits or 16 bits. The value of the load capacitance 24 attached to the output pad electrode for outputting each bit data is usually 10
It is about 0 pF. In a memory having a multi-bit structure, it is necessary to charge and discharge a plurality of these load capacitors at the same time, and a large current flows due to the charge and discharge in the power supply wiring in the chip. For this reason, the wiring length in the chip is particularly long, and when a large current as described above flows through the reference voltage wiring having a large resistance component or inductance component, the reference voltage greatly changes in the chip. Therefore, supplying a reference voltage V _SS 1 to the internal circuit 22, by supplying independent reference voltage V _SS 2 in the peripheral circuit 23 having an output buffer which large current flows, the reference voltage V _SS 2 Even if noise is generated, the reference voltage V _SS 1 is not affected. Also, the fifth
In the figure, the reference voltage of the output circuit 16 and the output buffer 17 is V
_Although it is set to _SS 2, the reference voltage for the internal circuit of the output circuit 16 may be set to V _SS 1 and the reference voltage V _SS 2 may be supplied only to the output buffer 17.

On the other hand, the IC is provided with a plurality of leads having an inner lead portion and an outer lead portion formed integrally with the inner lead portion in addition to the semiconductor chip. Then, after the tip portion of the inner lead portion and the pad electrode provided on the semiconductor chip are electrically connected by a thin metal wire made of, for example, Au or Al called a bonding wire, the inner lead portion is made of ceramic or It is enclosed together with a semiconductor chip in an envelope made of plastic, etc. On the other hand, the outer lead portion exposed from the envelope is cut and bent into a predetermined shape so that, for example, as shown in the oblique view of FIG. Used as a connection terminal. In FIG. 6, 30 is an envelope, and 31 is an outer lead portion exposed from the envelope 30.

In Fig. 7, the IC chip is enclosed and the external connection terminal is, for example, 28
It is a top view which shows the conventional internal structure of the envelope of a pin.
In the figure, 33 is the boundary line of the envelope, and inside the envelope
The IC chip 34 is enclosed. On the chip 34, the pad electrode 19 for the power supply voltage V _CC , the reference voltages V _SS 1, V _SS
Various pad electrodes including the pad electrodes 20 and 21 for 2 are provided. Reference numeral 35 is an inner lead portion of each lead for power supply voltage and signal input / output, and 36 is a bonding wire. In FIG. 7, pad electrodes other than those for power supply voltage and outer lead portions of leads are omitted.

As shown in the figure, in the past, the reference voltage of a circuit in which a large current flows, such as an output buffer, is separated from other circuits on the IC chip, but the leads are common for both the inner lead part and the outer lead part. There is.

By the way, in recent years, in the high-speed memory for which the access time has been shortened, the output load capacity is rapidly filled for speeding up.
Due to the discharge, the fluctuation of the reference voltage due to the inductance component in the lead for supplying the reference voltage cannot be ignored. For example, in the IC as shown in FIG. 7, the value of the inductance in the inner lead portion 32 of the reference voltage supply lead is calculated. The self-inductance L of the inner lead portion is defined by the length of the inner lead portion is l, the width is w,
When the thickness is t, it is approximately expressed by the following equation.

Here, as an example of typical values, l = 1.5 (cm) and w = 0.0
Substituting 5 (cm) and t = 0.02 (cm) into the above equation 1, L
The value of is about 12.8 (nH).

On the other hand, the discharge current of the output buffer 17 in the memory shown in FIG. 5 will be calculated. FIG. 8 is an equivalent circuit diagram of a portion related to the output buffer 17 in FIG. In FIG. 8, C is a load capacitance, Q is an N-channel type output transistor in the output buffer for discharging the load capacitance C,
L is a self-inductance component existing in the inner lead portion. In this case, it is assumed that the load capacitance C is discharged, and the P-channel type charging output transistor connected to the power supply voltage V _CC in the output buffer is off, so it is omitted here. If this memory has an 8-bit configuration, the value of the load capacitance C is 100 pF, which is the value for 1 bit.
It is 800pF which is 8 times of The dimension of the channel width W and the channel length L for one output transistor is usually W = 30.
Since it is set to 0 (μm) and L = 2.2 (μm), 8
Equivalent channel width W of output transistor Q for bit
Is 2400 (μm) and the channel length L is 2.2 (μm).

Here, when the signal Dout in the load capacitance C is charged to 5 (V) in advance and Dout is set to the "1" level, the signal Din shown in the waveform diagram of FIG. 9 is applied to the gate of the output transistor Q. The characteristic diagram of FIG. 10 shows the result of a change in the discharge current Is which is input and then turned on when the transistor Q is turned on, which is obtained by computer simulation. The noise generated in the reference voltage V _SS 2 is proportional to the rate of temporal change of the discharge current Is, that is, dIs / dt, and its maximum value dIs / dt (max) is about the position indicated by the straight line A in the figure. 78 x 1
0 ⁶ (A / See). Therefore, when discharging the load capacitance C, the maximum voltage V _SS 2 (max) at the pad electrode 21 of the reference voltage V _SS 2 is expressed by the following equation.

V _SS 2 (max) = L · {dIs / dt (max)} ... 2 Here, L = 12.8 (nH), dIs / dt (ma obtained earlier
Substituting x) = 78 × 10 ⁶ (A / Sec), V _SS 2 (max) ≈ 1
(V). That is, in the conventional IC as shown in FIG. 7, the voltage of the pad electrode 21 on the chip, which is supposed to be 0 (V), rises to 1 (V) at the maximum.
Therefore, since the other pad electrode 20 is also affected by this voltage fluctuation, there is a drawback that the internal circuit is apt to malfunction in the conventional case.

(Problems to be Solved by the Invention) As described above, in the conventional reaction body integrated circuit, the pad electrodes for supplying the power supply voltage are separately provided on the semiconductor chip for a circuit in which a large amount of current flows and a circuit in which it does not. , I try to prevent malfunctions due to noise, but that is still not enough.

The present invention has been made in view of the above circumstances, and an object thereof is to improve the shape of the lead frame to suppress noise generated in the path of the power supply voltage, thereby causing malfunction. An object of the present invention is to provide a semiconductor integrated circuit capable of keeping the voltage extremely low.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit according to the present invention includes a semiconductor chip having a plurality of pad electrodes formed on a surface thereof, an envelope for housing the semiconductor chip, and A plurality of leads each formed of an inner lead portion housed in the envelope and an outer lead portion exposed from the envelope, each inner lead portion being electrically connected to each pad electrode of the semiconductor chip; An inner lead portion and an outer lead portion, the inner lead portion including at least one unconnected lead that is not electrically connected to the pad electrode of the semiconductor chip, and at least the power supply voltage of the plurality of leads. The inner lead portion ahead of the outer lead portion of the power supply lead for supplying the power to the semiconductor chip is divided into a plurality of parts. Together, the non-connection lead is arranged in the vicinity of the power supply lead, and the inner lead portion of the non-connection lead has its tip not extended to the vicinity of the semiconductor chip, It is characterized in that it is formed so as to exist only near the boundary portion of the envelope.

A semiconductor integrated circuit according to the present invention includes a semiconductor chip having a plurality of pad electrodes formed on a surface thereof, an outer enclosure for accommodating the semiconductor chip, an inner lead portion accommodated in the enclosure, and the outer enclosure. An inner lead portion and an outer lead portion, each inner lead portion being electrically connected to each pad electrode of the semiconductor chip, and an inner lead portion and an outer lead portion. An outer lead of a power supply lead that has at least one unconnected lead whose lead portion is not electrically connected to a pad electrode of the semiconductor chip, and which supplies at least a power supply voltage to the semiconductor chip among the plurality of leads. The area of the inner lead part from the above part is made wider than the inner lead parts of other leads, and The continuous lead is arranged close to the power supply lead, and the inner lead portion of the non-connection lead does not have its tip extended to the vicinity of the semiconductor chip. It is characterized in that it is formed so as to exist only near the boundary.

(Function) By increasing the area of the inner lead portion of the lead for supplying the power supply voltage, the power supply capacity of the inner lead portion is increased, and noise generated in the pad electrode on the semiconductor chip is absorbed by this inner lead portion. To be done. Moreover, by forming the inner lead portion in the vicinity of the boundary portion of the envelope in the connectionless lead, it is possible to further increase the area of the inner lead portion of the lead for supplying the power supply voltage.

In addition, by connecting each of the inner lead portions divided into a plurality of parts to the pad electrode on the semiconductor chip independently, the influence of noise between the divided inner lead portions is greatly reduced. Even in this case, by forming the inner lead part in the vicinity of the boundary part of the envelope, it is possible to increase the area of each of the divided inner lead parts. The power supply current supply capacity of the unit is increased.

(Examples) Hereinafter, the present invention will be described by examples with reference to the drawings.

FIG. 1 is a plan view showing the internal structure of an envelope according to a first embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 1, only the reference voltage lead and the signal input / output lead in the envelope are shown. In this embodiment, although not shown, a memory IC chip having two pad electrodes (20, 21) for the reference voltages V _SS 1 and V _SS 2 on its surface is provided as in the case of FIG. It is enclosed in an envelope. Similar to FIG. 7, 35 is an inner lead portion of each lead, 31 is an outer lead portion integrally formed with each inner lead portion 35, and 33 is a boundary line of the envelope. Each outer lead portion 31 exposed to the outside of the envelope is used as a DIP type external connection terminal as shown in FIG. 6 by bending it into a predetermined shape.

In this embodiment, in the inner lead portion 35 of the lead for the reference voltages V _SS 1 and V _SS 2, the outer lead portion 31 of the lead is used.
Is divided into two inner lead portions 35A, 35B, the tip of each inner lead portion 35A, 35B and a reference voltage on a chip (not shown) in which the circuit shown in FIG. 5 is configured. Two pad electrodes for V _SS 1 and V _SS 2 are connected to each other via bonding wires.

Further, in this embodiment, one unconnected lead that is not electrically connected to the pad electrode on the chip is provided. The connectionless lead is composed of an inner lead portion 35C and an outer lead portion 31C, and the inner lead portion 35C is partially formed near the boundary of the envelope. That is, the inner lead portion 35C is not extended to the position of the chip inside the envelope.

In such a configuration, a large current flows through the peripheral circuit 23 (all shown in FIG. 5) provided with the output buffer 17, and the reference voltage V _SS 2 at the pad 21 is instantaneously changed as described above. It is assumed that it floats by about 1 (V). At this time, the voltage fluctuation of the reference voltage V _SS 2 is due to the inner lead part of the lead.
Transmitted to 35B. However, the pad 20 to which the internal circuit 22 (shown in FIG. 5) is connected has the same outer lead portion of the lead via the independent bonding wire and the inner lead portion 35A separated from the inner lead portion 35B. It is connected with 31. Therefore, the voltage fluctuation of the reference voltage V _SS 2 transmitted to the inner lead portion 35B is not transmitted to the inner lead portion 35A to which the internal circuit 22 is connected. Therefore, the reference voltage V _SS 1 is always stable without being affected by the current flowing through the output buffer, and the internal circuit 22 performs a normal operation without causing a malfunction. In an IC memory that requires high-speed operation, it is necessary to instantaneously flow a large amount of current to the output buffer. By dividing the inner lead part for the reference voltage in this way, the effect of reducing power supply noise on the internal circuit is reduced. large.

Further, in this embodiment, a connectionless lead is provided, and the inner lead portion 35C is partially formed only near the boundary portion of the envelope, and is extended to the position of the chip inside the envelope. Absent. Therefore, compared with the case where the inner lead portion 35C is extended to the position of the chip inside the envelope, the shape of the inner lead portions 35A and 35B for the reference voltages V _SS 1 and V _SS 2 is designed. The degree of freedom is increased, and the area of both lead portions 35A and 35B can be increased.

FIG. 2 is a plan view showing the internal structure of the envelope according to the second embodiment of the semiconductor integrated circuit of the present invention. Also in the case of FIG. 2, only a plurality of leads including leads for the reference voltage in the envelope are shown.

In this embodiment, the inner lead portions 35A and 3A for the reference voltage V _SS 1 which are divided into two in the embodiment of FIG. 1 are used.
5B is integrated and integrated as an inner lead portion 35D, and the inner lead portion 35D is configured to have a larger area than other inner lead portions for signal input / output.

Further, also in this embodiment, one unconnected lead which is composed of the inner lead portion 35C and the outer lead portion 31C and is not electrically connected to the pad electrode on the chip is provided. It is partially formed near the boundary of the envelope and does not extend to the chip position.

In this embodiment, the inner lead portion 35 for transmitting the reference voltage is used.
Since the area of D is wider than the inner lead portions for other signal input / output, it is possible to suppress the noise generated in the path of the reference voltage and prevent the malfunction of the circuit due to the noise.

Moreover, in this embodiment, the connectionless lead is provided, and the inner lead portion 35C is partially formed only near the boundary portion of the envelope, and is extended to the position of the chip inside the envelope. Since there is no inner lead portion 35C, the degree of freedom in designing the shape of the inner lead portion 35D for the reference voltage increases compared to the case where the inner lead portion 35C is extended to the position of the chip inside the envelope. The area can be further increased.

FIG. 3 is a plan view showing the internal structure of the envelope according to the third embodiment of the semiconductor integrated circuit according to the present invention. In this embodiment, similarly to the embodiment of FIG. 1, the reference voltage V _SS 1,
In the inner lead portion 35 of the lead for V _SS 2, the outer lead portion 31 of the lead and two inner lead portions
The inner lead portion 35C of the non-connection lead that is divided into 35A and 35B and is not electrically connected to the pad electrode on the chip is connected to other inner lead portions for signal input / output near the boundary of the envelope. The mechanical strength of the inner lead portion for signal input / output is increased by connecting the inner lead portion to one.

FIG. 4 is a plan view showing the internal structure of the envelope according to the fourth embodiment of the semiconductor integrated circuit of the present invention. In this embodiment, as in the embodiment of FIG. 2, the inner lead portion 35D of the reference voltage lead is widened and
By connecting the inner lead portion 35C of the connectionless lead, which is not electrically connected to the pad electrode on the chip, with one of the inner lead portions for other signal input / output near the boundary of the envelope, The mechanical strength of the inner lead portion for signal input / output is increased.

As described above, in each of the above-described embodiments, the inner lead for transmitting the reference voltage to the chip is divided into two, or the area of this inner lead portion is made wider than the inner lead portions for other signals. The noise generated in the path of the reference voltage can be suppressed, and the malfunction of the internal circuit due to the noise can be prevented. Moreover, in each of the above embodiments, the connectionless lead is provided, and the inner lead portion 35C of this terminal is partially formed only near the boundary of the envelope, and the position of the chip inside the envelope is Since it is not extended to, compared with the case where this inner lead part 35C is extended to the position of the chip inside the envelope,
The degree of freedom in designing the shape of the inner lead portion for the reference voltage is increased, and the area of this lead portion can be easily increased.

It is needless to say that the present invention is not limited to the above embodiments and various modifications can be made. For example, in each of the above-described embodiments, the case where the present invention is applied to the lead side that transmits the reference voltage to the chip has been described, but this can also be applied to the lead side that transmits the power supply voltage to the chip. It is also possible to implement both.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit in which noise generated in the path of the power supply voltage can be suppressed, and thereby malfunctions can be suppressed to an extremely low level. it can.

[Brief description of drawings]

FIG. 1 is a plan view showing the internal structure of an envelope according to the first embodiment of the present invention, and FIG. 2 is a plan view showing the internal structure of the envelope according to the second embodiment of the present invention. FIG. 4 is a plan view showing the internal structure of an envelope according to a third embodiment of the present invention, FIG. 4 is a plan view showing the internal structure of an envelope according to the fourth embodiment of the present invention, and FIG. FIG. 6 is a block diagram showing a circuit configuration of a typical memory IC chip, FIG. 6 is a perspective view of a semiconductor integrated circuit, and FIG. 7 is a plan view showing an internal configuration of an envelope of a conventional semiconductor integrated circuit. Is an equivalent circuit diagram of a part of the circuit of FIG. 5, FIG. 9 is a waveform diagram of signals used in the circuit of FIG. 8,
FIG. 10 is a characteristic diagram of the circuit shown in FIG. 20,21 …… Pad electrode for reference voltage, 30 …… Enclosure, 31,
31C …… Lead outer lead part, 33 …… Envelope boundary line, 34 …… IC chip, 35,35A, 35B, 35C, 35D …… Lead inner lead part, 36 …… Bonding wire.

Claims (2)

[Claims] 1. A semiconductor chip having a plurality of pad electrodes formed on a surface thereof, an envelope for accommodating the semiconductor chip, a liner lead portion accommodated in the envelope, and the envelope. An inner lead portion, and a plurality of leads each of which is formed of an exposed outer lead portion, each inner lead portion being electrically connected to each pad electrode of the semiconductor chip, and an inner lead portion and an outer lead portion. From at least one unconnected lead that is not electrically connected to the pad electrode of the semiconductor chip, and from the outer lead portion of the power supply lead that supplies at least the power supply voltage to the semiconductor chip among the plurality of leads. The inner lead part is divided into a plurality of parts, and the non-connection lead is close to the power supply lead. The inner lead part of this connectionless lead is formed so that its tip does not extend to the vicinity of the semiconductor chip and exists only in the vicinity of the boundary of the envelope within the envelope. A semiconductor integrated circuit characterized in that 2. A semiconductor chip having a plurality of pad electrodes formed on a surface thereof, an envelope for accommodating the semiconductor chip, an inner lead portion accommodated in the envelope, and exposed from the envelope. Outer leads, each inner lead being electrically connected to each pad electrode of the semiconductor chip, and a plurality of leads, an inner lead and an outer lead. At least one unconnected lead that is not electrically connected to the pad electrode of the semiconductor chip is provided, and the outer lead portion of the power supply lead that supplies at least the power supply voltage to the semiconductor chip among the plurality of leads is first The area of the inner lead part of this is larger than the inner lead parts of other leads, and The inner lead part of this non-connection lead is located close to the power supply lead, and its tip is not extended to the vicinity of the semiconductor chip. A semiconductor integrated circuit characterized in that it is formed so as to exist only in.