JPH0779167B2 - Integrated semiconductor pressure sensor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an integrated semiconductor pressure sensor in which a resistor is formed on a silicon diaphragm and an integrated circuit such as an operational amplifier is formed in a peripheral thick portion.

[Outline of Invention]

In the semiconductor pressure sensor according to the present invention, a first semiconductor layer of the first conductivity type is grown on a high-concentration semiconductor wafer, and a second semiconductor layer of the second conductivity type is further grown on the first semiconductor layer. An integrated semiconductor pressure sensor configured according to the above, wherein a central portion of a first type conductivity type single crystal silicon substrate is anisotropically etched to a position close to a first type conductivity type first semiconductor layer. A semiconductor pressure sensor having a predetermined diaphragm thickness is constructed by etching the rest of the single crystal silicon substrate by isotropic etching as well as etching.

[Conventional technology and its problems]

(Prior Art) In a silicon diaphragm type semiconductor pressure sensor, for example, as shown in FIG. 5, an N type epitaxial layer 2 is formed on a P type substrate 1 and the center of the P type substrate is etched to form a diaphragm. is doing. Then, four diffusion resistors are formed at the center and the periphery of the diaphragm, and each resistor is connected to form a bridge circuit. The pressure applied to the diaphragm is measured by converting the pressure change applied to the diaphragm into the voltage change across the bridge circuit. I am trying to do it. An amplifier that amplifies a voltage change across the bridge circuit is formed around the diaphragm. Such an amplifier has an N on top of a P-type substrate.
It is composed of a type buried layer 3 and a transistor and the like covered with ap ⁺ type separation diffusion layer 4 covering the type buried layer 3. In such a semiconductor pressure sensor, since the sensitivity is inversely proportional to the square of the thickness of the diaphragm portion, it is necessary to form the diaphragm sufficiently thin and highly accurate in order to make the sensitivity characteristics uniform.

However, a silicon wafer causes a variation of, for example, about ± 4 μm in manufacturing, and when the silicon diaphragm is formed by etching, the temperature of the etching solution, the diffusion state, the composition change of the etching solution, and the like cause a variation of, for example, ± 4 μm.
There is a degree of variation. Therefore, even if the diaphragm thickness is set thin, for example, to 30 μm in order to obtain sufficient sensitivity, it is difficult to make the thickness uniform due to variations in the manufacturing process. For example, the broken line A or B in FIG. As shown, the sensitivity of the semiconductor pressure sensor may be too high or too low, resulting in a poor product yield.

Therefore, in order to make the thickness of the diaphragm uniform, Japanese Patent Laid-Open No.
-42597, as shown in FIG. 6, a high concentration P ⁺ -type boron layer 6 (impurity concentration 5) is formed on a P-type silicon substrate 5.
(× 10 ¹⁹ pieces / cm ³ or more) is formed, an N-type epitaxial layer 7 is grown on top of it to form diffusion resistance, and anisotropic etching is performed from below to the P ⁺ -type boron layer 6 to form a diaphragm. A technique for making the thickness uniform has been proposed.

(Problems to be Solved by the Invention) However, when controlling the thickness of the silicon diaphragm by such a conventional method, the impurity concentration of the P ⁺ -type boron layer 6 below the N-type epitaxial layer 7 is high. ,
The resistivity ρ becomes 0.028 Ω · cm or less, and the value of ρ becomes extremely low. Therefore, when an operational amplifier is formed around the diaphragm as shown in FIG. 5, the N-type buried layer 3
However, there is a problem in that high-concentration diffusion that compensates for this is required, and crystal defects may occur. Further, when an integrated circuit is formed around the silicon diaphragm, a reverse bias is applied between the N-type epitaxial layer 2 and the P-type substrate 1 thereunder in order to electrically isolate each active element such as a transistor. Apply, but P-type substrate 1
If the resistivity is low, the breakdown voltage of the junction is low. Therefore, in the method disclosed in JP-A-53-42597, an integrated semiconductor pressure sensor is constructed by incorporating a circuit such as an amplifier circuit for amplifying the output of the resistance bridge or a temperature compensation circuit around the silicon diaphragm. There was a problem that I could not do it.

[Object of the Invention]

The present invention has been made in view of such problems of the conventional semiconductor pressure sensor, and is configured such that the diaphragm is made uniform in thickness and a circuit such as an amplifier circuit is mounted around the diaphragm. To do this is a technical issue.

[Constitution and effect of the invention]

(Means for Solving Problems) The present invention is an integrated semiconductor pressure sensor in which a resistor is formed on a silicon diaphragm and an integrated circuit such as an operational amplifier is formed in a peripheral thick portion, which is shown in FIG. Is formed on a first-type conductivity type single-crystal silicon substrate having a conductivity in a predetermined range that can be etched, has a predetermined thickness, is higher than the silicon substrate, and isotropic etching is impossible. A first semiconductor layer of a first conductivity type having a refractive index, and a second semiconductor layer of a second conductivity type having a predetermined thickness formed on the upper surface of the first semiconductor layer; A diaphragm composed of first and second semiconductor layers formed by anisotropically etching from below the silicon substrate to near the junction surface of the first semiconductor layer and isotropically etching the rest; Semiconductor layer diaphragm A resistor formed on the arm portion, and is characterized in that it has a an integrated circuit including an amplifier for amplifying a voltage change formed around the diaphragm resistance.

(Operation) According to the present invention having such a feature, the single crystal silicon substrate is a semiconductor of the first type conductivity type in a predetermined range capable of anisotropic etching, and a first thickness of the first semiconductor having a predetermined thickness is provided above the single crystal silicon substrate.
The first semiconductor layer of the conductivity type of No. 2 is grown, and the second semiconductor layer of the conductivity type of the second type is further grown on the first semiconductor layer. Then, the single crystal silicon substrate is etched by anisotropic etching to a region immediately below the first semiconductor layer of the first type conductivity type, and the remaining single crystal silicon substrate is etched by isotropic etching. To form.
When etching by isotropic etching, the etching is automatically stopped by the first semiconductor layer above it.

(Effect of the invention) Therefore, according to the present invention, by setting the thickness of the first and second semiconductor layers grown on the top of the single crystal silicon substrate to a predetermined value, the thickness of the diaphragm is adjusted to a silicon wafer or an etching solution. Regardless of the state, it can be specified with extremely high accuracy. Also, since the remaining part of the single crystal silicon substrate is etched by isotropic etching, it is possible to bend the diaphragm edge part with a sharp shape, and the stress concentration at the time of pressure application is relaxed and the semiconductor pressure is hard to break. It can be a sensor. Further second
Since the first semiconductor layer having a relatively high resistivity is formed under the second semiconductor layer of the conductivity type of the above type, it is sufficient to configure an integrated circuit such as an operational amplifier around the diaphragm. A semiconductor having a breakdown voltage can be formed. Further, since the second-type conductivity type buried layer does not need to be diffused at a very high concentration, crystal defects do not occur, and an integrated semiconductor pressure sensor with a high yield can be configured.

[Explanation of Examples]

FIG. 1 is a diagram showing a manufacturing process of an integrated semiconductor pressure sensor according to an embodiment of the present invention. In this figure, a single crystal silicon substrate having a relatively high concentration of P-type impurities is used as a silicon wafer to form a substrate 11 as shown in FIG. 1 (a). Then, an oxide film SiO ₂ 12 is formed on the lower surface thereof. The substrate 11 has a resistivity in a range where anisotropic and isotropic etching is possible, that is, the resistivity ρ is 0.0028Ω.
cm to 0.015 Ω · cm (impurity concentration 8 × 10 ^{18 to} 5 × 10
¹⁹ pieces / cm ³ ) are used. And this P ⁺ type substrate 1
A P-type epitaxial layer 13 is grown on the upper surface of 1 as shown in FIG. It is assumed that the P-type epitaxial layer 13 is grown so as to have a predetermined thickness, for example, 20 ± 1.5 μm. The P-type epitaxial layer 13 has a resistivity such that isotropic etching is impossible, that is, the resistivity ρ is 0.06.
8Ω · cm or more (impurity concentration 9 × 10 ¹⁷ pieces / cm ³ or less)
For example, it has 10 Ω · cm (impurity concentration is 1 × 10 ¹⁵ pieces / cm ³ ). Then, as shown in FIG. 1 (c), an N type buried layer 14 is formed on the epitaxial growth layer 13,
Further, an N type epitaxial layer 15 is grown over the entire surface. Here, the thickness t ₂ of the N-type epitaxial layer 15
Is grown in advance to a predetermined thickness, for example 10 ± 1 μm. Then, as shown in FIG. 1C, the oxide film 12 under the substrate 11 is used as etching masks 12a and 12b for selectively etching by notching only the central portion where the diaphragm is formed.

Then, as shown in FIG. 1 (d), an N-type epitaxial layer is formed.
Diffusion resistors R1 and R3 (not shown) are formed in the center of the diaphragm portion from above 15 and diffusion resistors R2 and R4 are formed around the diaphragm. Then, a P ⁺ -type isolation diffusion layer 16 is formed around the diaphragm portion, and an operational amplifier 17 composed of a passive element such as a predetermined transistor or resistor and an active element is formed between the P ⁺ -type isolation diffusion layer 16 and the N-type buried layer 14 to form a bridge circuit. Form an integrated circuit that amplifies the voltage across.

Then, from below the substrate 11, an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH)
Is used to perform anisotropic etching. As shown in FIG. 1 (e), the anisotropic etching is performed until the thickness of the substrate 11 is slightly left t ₃ , for example, anisotropic until the thickness of the top surface of the N-type epitaxial layer 15 is 35 μm. Etching shall be performed. Then, as shown in FIG. 1 (f), isotropic etching is performed using an acidic etching solution. This etching solution is, for example, hydrogen fluoride (HF), acetic acid (CH ₃ COO
H) and nitric acid (HNO ₃ ) are mixed at a ratio of 1: 8: 3. In the isotropic etching, as shown in FIG. 1 (f), only the remaining portion of the silicon substrate 11 is etched, and the etching is automatically stopped on the surface of the P type epitaxial layer 13 formed on the remaining portion. By the isotropic etching, the ends of the etched substrate 11 and P-type epitaxial layer 13 can be curved as shown in the enlarged view of the C portion in FIG. Since the thickness of the diaphragm is determined by the thickness t ₂ of the thickness t ₁ and the N-type epitaxial layer 15 of P-type epitaxial layer 13 formed on top of substrate 11 In this manner, precision of the thickness of the epitaxial growth The thickness of the diaphragm can be correctly controlled by controlling the thickness.

FIG. 3 is a circuit diagram showing the configuration of the integrated semiconductor pressure sensor according to this embodiment. An operational amplifier having a bridge circuit formed by diffusion resistances R1 and R3 in the center of the diaphragm and diffusion resistances R2 and R4 in the periphery of the diaphragm as shown in the figure, and a feedback resistance and an input resistance around the diaphragm.
17 constitutes a semiconductor pressure sensor that amplifies the output voltage of the bridge circuit.

In the semiconductor pressure sensor thus configured, the thickness of the diaphragm, which greatly affects the sensitivity, can be controlled with high accuracy, so that the pressure sensor can have a small variation in sensitivity as shown in D1 and D2 of FIG.

In this embodiment, a P ⁺ type epitaxial layer and a P type epitaxial layer and an N type epitaxial layer are grown on the substrate, but the conductivity type is reversed to N ^{+ type.}
It is also possible to grow N-type and P-type epitaxial layers on the mold substrate.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of an integrated semiconductor pressure sensor according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a part of the semiconductor pressure sensor shown in FIG. 1 (f) of the semiconductor pressure sensor. FIG. 3 is a circuit diagram showing an example of the circuit configuration of the integrated semiconductor pressure sensor according to this embodiment, FIG. 4 is a diagram showing changes in output voltage with respect to applied pressure, and FIGS. 5 and 6 are conventional semiconductor pressure sensors. It is sectional drawing which shows an example. 11 …… Substrate (single crystal silicon substrate) 12 …… Oxide film, 13 …… P type epitaxial layer (first semiconductor layer), 14 …… N type buried layer 15 …… N type epitaxial layer (second Semiconductor layer) 16 …… P ⁺ type isolation diffusion layer, R1 to R4 …… diffusion resistance, 17 …… operational amplifier

Claims (3)

[Claims] 1. Formed on a first-type conductivity type single crystal silicon substrate having a predetermined range of conductivity capable of being etched, having a predetermined thickness and being higher than the silicon substrate, and isotropic etching is impossible. Type conductivity type first semiconductor layer having different conductivity, and second type conductivity type second semiconductor having a predetermined thickness formed on the upper surface of the first semiconductor layer. And a first semiconductor layer and a second semiconductor layer formed by anisotropically etching from below the silicon substrate to near the bonding surface of the first semiconductor layer and isotropically etching the rest. An integrated circuit including a diaphragm, a resistor formed in a diaphragm portion of the second semiconductor layer, and an integrated circuit formed around the diaphragm and including an amplifier for amplifying a voltage change of the resistor. Conversion Conductor pressure sensors. 2. The integrated device according to claim 1, wherein the first type conductivity type semiconductor is a P type semiconductor, and the second type conductivity type semiconductor is an N type semiconductor. Semiconductor pressure sensor. 3. The single crystal silicon substrate has a resistivity of 0.0028.
It has a conductivity of Ω · cm to 0.015 Ω · cm, and the first semiconductor layer formed on top of it has a resistivity of 0.068Ω.
The integrated semiconductor pressure sensor according to claim 2, which has a resistivity of cm or more.