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JPH0779192B2 - How to join electronic components - Google Patents
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JPH0779192B2 - How to join electronic components - Google Patents

How to join electronic components

Info

Publication number
JPH0779192B2
JPH0779192B2 JP60033948A JP3394885A JPH0779192B2 JP H0779192 B2 JPH0779192 B2 JP H0779192B2 JP 60033948 A JP60033948 A JP 60033948A JP 3394885 A JP3394885 A JP 3394885A JP H0779192 B2 JPH0779192 B2 JP H0779192B2
Authority
JP
Japan
Prior art keywords
wiring board
electronic component
conductive particles
terminals
insulating adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60033948A
Other languages
Japanese (ja)
Other versions
JPS61194796A (en
Inventor
和弘 杉山
敏良 出口
久士 正木
好男 鑓田
好則 厚見
敏晴 玉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP60033948A priority Critical patent/JPH0779192B2/en
Publication of JPS61194796A publication Critical patent/JPS61194796A/en
Publication of JPH0779192B2 publication Critical patent/JPH0779192B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、電子部品を配線基板面に直接接合する電子
部品の接合方法に関するものである。
Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for joining electronic components in which electronic components are directly joined to a wiring board surface.

〔発明の技術的背景〕[Technical background of the invention]

LSIチップや液晶表示パネル等の電子部品を配線基板に
取付ける方法として、電子部品を直接配線基板面に接合
する方法がある。
As a method of attaching electronic components such as an LSI chip and a liquid crystal display panel to a wiring board, there is a method of directly bonding the electronic components to the wiring board surface.

この方法としては、従来、配線基板面の電子部品接合面
に、電子部品の配線基板接合面に形成されている複数の
外部回路接続用端子と対応する複数の電子部品接続用端
子を配列形成し、この配線基板の電子部品接合面に各電
子部品接続用端子の上から異方導電性接着剤を塗布して
その上に電子部品を重ね、この状態で電子部品と配線基
板とを相対的に押圧することにより、電子部品と配線基
板とをその端子同志を導通接続させて接着接合する方法
が採用されている。
In this method, conventionally, a plurality of electronic component connecting terminals corresponding to a plurality of external circuit connecting terminals formed on the wiring substrate connecting surface of the electronic component are arranged and formed on the electronic component connecting surface of the wiring substrate surface. , An electronically conductive adhesive is applied to the electronic component bonding surface of the wiring board from above each electronic component connecting terminal, and the electronic component is overlaid thereon, and in this state, the electronic component and the wiring board are relatively A method has been adopted in which the terminals of the electronic component and the wiring board are electrically connected to each other by being pressed so as to be adhesively joined.

なお、前記異方導電性接着剤は、絶縁性接着剤中に導電
性粒子を、導電性粒子同志が互いに接触し合わないよう
な割合で混入したもので、この異方導電性接着剤からな
る接着剤層は、厚さ方向には導通性を示すが面方向(横
方向)には絶縁性をもっているから、電子部品と配線基
板との接合面に異方導電性接着剤を介在させて電子部品
と配線基板とを相対的に押圧すると、電子部品の各端子
と配線基板の各端子とが導通接続(導電性粒子を介して
導通接続)される。
The anisotropic conductive adhesive is a mixture of electrically conductive particles in an insulating adhesive in such a ratio that the conductive particles do not contact each other, and is made of this anisotropic conductive adhesive. Since the adhesive layer has conductivity in the thickness direction but has insulating property in the surface direction (lateral direction), the anisotropic conductive adhesive is interposed between the electronic component and the wiring board to form an electronic layer. When the component and the wiring board are relatively pressed, each terminal of the electronic component and each terminal of the wiring board are electrically connected (electrically connected via conductive particles).

〔背景技術の問題点〕[Problems of background technology]

しかしながら、上記異方導電性接着剤によって電子部品
と配線基板とを接着接合する方法は、短時間で電子部品
を配線基板に取付けることができるが、この方法では、
電子部品の各端子部と配線基板の各端子との全てが必ず
導通接続されるとは限らず、そのために信頼性が悪いと
いう問題があった。
However, in the method of adhesively bonding the electronic component and the wiring board with the anisotropic conductive adhesive, the electronic component can be attached to the wiring board in a short time.
Not all of the terminals of the electronic component and the terminals of the wiring board are all necessarily electrically connected, and there is the problem of poor reliability.

これは、前記異方導電性接着剤の導電性粒子の分布が不
規則にばらついているためであり、これに対してLSIチ
ップや液晶表示パネル等の電子部品の電子巾は非常に狭
いから、異方導電性接着剤にその導電性粒子の間隔が前
記端子巾より広くなっている箇所があってこの箇所に前
記端子がたまたま対応すると、この部分では電子部品と
配線基板との端子間に導電性粒子が介在されずに、この
部分の端子が導通接続されない状態になる。なお、異方
導電性接着剤中の導電性粒子の混入比を多くしてやれ
ば、導電性粒子の間隔も小さくなるから、全ての端子を
ほぼ確実に導通接続することができるが、このように異
方導電性接着剤中の導電性粒子の混入比を多くすると、
導電性粒子の間隔が密になっている部分で導電性粒子同
志が接触し合って隣接する端子同志を短絡させてしまう
ことになる。
This is because the distribution of the conductive particles of the anisotropic conductive adhesive is irregularly distributed, whereas the electronic width of electronic parts such as LSI chips and liquid crystal display panels is very narrow, If the anisotropic conductive adhesive has a portion where the distance between the conductive particles is wider than the terminal width, and the terminal happens to correspond to this portion, the conductive portion between the electronic component and the wiring board is electrically conductive in this portion. The conductive particles are not interposed and the terminals in this portion are not electrically connected. If the mixing ratio of the conductive particles in the anisotropic conductive adhesive is increased, the distance between the conductive particles also becomes smaller, so that all the terminals can be almost surely conductively connected. If the mixing ratio of conductive particles in the one-way conductive adhesive is increased,
In a portion where the conductive particles are closely spaced, the conductive particles come into contact with each other and short-circuit adjacent terminals.

〔発明の目的〕[Object of the Invention]

この発明は上記のような実情にかんがみてなされたもの
であって、その目的とするところは、異方導電性接着剤
によって電子部品を接着接合する方法と同程度の短い時
間で能率よく電子部品を配線基板に取付けることができ
るとともに、電子部品の各端子を基板面の各端子に導通
不良部分を生ずることなる確実に導通接続することがで
きるようにした電子部品の接合方法を提供することにあ
る。
The present invention has been made in view of the above circumstances, and an object of the invention is to efficiently and efficiently electronic parts in a short time comparable to the method of adhesively bonding electronic parts with an anisotropic conductive adhesive. To provide a method for joining electronic components, in which each of the terminals of the electronic component can be securely connected to each other on the surface of the substrate so that a defective conduction portion is generated. is there.

〔発明の概要〕[Outline of Invention]

この発明の電子部品の接合方法は、前記電子部品と前記
配線基板との接合面の一方に絶縁性接着剤を塗布した
後、この絶縁性接着剤上にメッシュスクリーンを重ねて
その上から導電性粒子を散布し、この導電性粒子のうち
前記メッシュスクリーンの各開口に入った導電性粒子を
前記絶縁性接着剤中に押込んで前記絶縁性接着剤中に多
数の導電性粒子を等間隔に埋込み、この後前記電子部品
と前記配線基板とを重ねて相対的に押圧して前記電子部
品と前記配線基板とを接着接合するものである。
The method for joining electronic components according to the present invention is such that after applying an insulating adhesive to one of the joining surfaces of the electronic component and the wiring board, a mesh screen is overlaid on the insulating adhesive and conductivity is applied from above. Particles are scattered, and among the conductive particles, the conductive particles that have entered each opening of the mesh screen are pushed into the insulating adhesive to embed a large number of conductive particles in the insulating adhesive at equal intervals. After that, the electronic component and the wiring board are overlapped and relatively pressed to bond and bond the electronic component and the wiring board.

つまり、この発明は、絶縁性接着剤中に導電性粒子を埋
込んだ接合材を介して電子部品と配線基板とを接着接合
することにより、異方導電性接着剤によって電子部品を
接着接合する方法と同様に、電子部品と配線基板とを相
対的に押圧して接着剤を硬化させるだけで配線基板に電
子部品をその両方の端子を互いに導通接続させた状態で
接合することができるようにするとともに、前記導電性
粒子を、電子部品と配線基板との両方の端子のうち狭巾
の端子の巾よりも小さくかつ前記電子部品と前記配線基
板とのいずれの端子間隔よりも小さい多数の開口を前記
狭巾端子の巾よりも小さい間隔で等間隔に形成したメッ
シュスクリーンを介して絶縁性接着剤中に埋込むことに
より、対応する全ての端子間に少なくとも1つの導電性
粒子が必ず介在されるようにして、異方導電性接着剤を
用いた場合における導電性粒子の分布のばらつきによる
導通不良部分の発生をなくしたものである。
That is, according to the present invention, the electronic component and the wiring board are adhesively joined via the joining material in which the conductive particles are embedded in the insulating adhesive, so that the electronic component is adhesively joined by the anisotropic conductive adhesive. Similar to the method, it is possible to bond the electronic component to the wiring substrate in a state where both terminals are electrically connected to each other only by relatively pressing the electronic component and the wiring substrate to cure the adhesive. In addition, the conductive particles are provided with a large number of openings smaller than the width of a narrow terminal of both terminals of the electronic component and the wiring board and smaller than any terminal spacing between the electronic component and the wiring board. Is embedded in the insulating adhesive through a mesh screen formed at equal intervals with a width smaller than the width of the narrow terminals, so that at least one conductive particle must be interposed between all corresponding terminals. In the so that, those who lost the occurrence of poor conduction portion due to variation in the distribution of the conductive particles in the case of using an anisotropic conductive adhesive.

〔発明の実施例〕Example of Invention

以下、この発明の一実施例を図面を参照して説明する。 An embodiment of the present invention will be described below with reference to the drawings.

まず、電子部品の接合構造について説明すると、第1図
〜第3図において、1は配線基板であり、この配線基板
1面には第3図に示すように複数の配線2,2,…が形成さ
れている。この各配線2,2,…は、配線基板1のLSIチッ
プ接合部から導出されており、各配線2,2,…のLSIチッ
プ接合部側の端部は、LSIチップ10の配線基板接合面に
配列形成されている複数の外部回路接続用端子11,11,…
とそれぞれ対応するLSIチップ接続用端子2a,2a,…とさ
れている。なお、この各端子2a,2a,…の巾は、LSIチッ
プ10の各端子11,11,…の巾より若干狭い巾とされてい
る。
First, the joining structure of electronic components will be described. In FIGS. 1 to 3, 1 is a wiring board, and a plurality of wirings 2, 2, ... Are provided on the surface of the wiring board 1 as shown in FIG. Has been formed. The wirings 2, 2, ... Are derived from the LSI chip joint portion of the wiring board 1, and the ends of the wirings 2, 2 ,. For forming a plurality of external circuit connection terminals 11, 11, ...
And corresponding LSI chip connection terminals 2a, 2a ,. The width of each terminal 2a, 2a, ... Is slightly narrower than the width of each terminal 11, 11 ,.

3は前記基板1面のLSIチップ接合面に、全てのLSIチッ
プ接合用端子2a,2a,…を覆うように形成された接合材で
あり、この接合材3は、前記LSIチップ接合面にその全
面にわたって均一に塗布した絶縁性接着剤3a中に、多数
の導電性粒子4,4,…を埋設したものである。この導電性
粒子4,4,…は、前記LSIチップ10の外部回路接続用端子1
1,11,…と配線基板1面のLSIチップ接続用端子2a,2a,…
とのうちの狭巾の端子(この実施例では配線基板1面の
LSIチップ接続用端子2a,2a,…)の巾及びLSIチップ10の
外部回路接続用端子11,11,…間の間隔よりも小さい粒径
もの(例えば端子巾およびその間隔が50〜250μである
場合は粒径20〜40μ)とされており、この導電性粒子4,
4,…は、絶縁性接着剤3中に、前記各端子2a,2a,…の巾
よりも小さい間隔で等間隔に埋込まれている。なお、こ
の導電性粒子4,4,…としては、例えばニッケル粒子を金
メッキしたものや、半田粒子、銅粒子を金または銀メッ
キしたもの、またはグラファイト粒子等がある。
3 is a bonding material formed on the LSI chip bonding surface of the substrate 1 so as to cover all the LSI chip bonding terminals 2a, 2a, ..., and this bonding material 3 is formed on the LSI chip bonding surface. A large number of conductive particles 4, 4, ... Are embedded in an insulating adhesive 3a uniformly applied over the entire surface. The conductive particles 4, 4, ... Are the external circuit connection terminals 1 of the LSI chip 10.
, 1, and terminals 2a, 2a, ... for connecting LSI chips on the surface of the wiring board 1
And the narrow terminal (in this embodiment, the wiring board 1 surface
The width of the LSI chip connection terminals 2a, 2a, ..., And the particle size smaller than the interval between the external circuit connection terminals 11, 11, ... of the LSI chip 10 (for example, the terminal width and the interval are 50 to 250 μ). In this case, the particle size is 20-40μ).
4, are embedded in the insulating adhesive 3 at regular intervals smaller than the width of the terminals 2a, 2a ,. The conductive particles 4, 4, ... Are, for example, nickel particles plated with gold, solder particles, copper particles plated with gold or silver, or graphite particles.

また、第3図において、2b,2b,…は配線基板1の一側縁
部に、液晶表示パネル20の配線基板接合面(端子配列
部)に配列されている複数の外部回路接続用端子21,21,
…とそれぞれ対応させて配列形成された表示パネル接続
用端子であり、この表示パネル接続用端子2b,2b,…の配
列部つまり表示パネル接合部にも、表示パネル接合面に
均一に塗布した絶縁性接着剤中に、最大粒子の粒径が前
記表示パネル接続用端子2b,2b,…と液晶表示パネル20の
外部回路接続用端子21,21,…とのうちの狭巾の端子の巾
よりも小さくかつ前記表示パネル接続用端子2b,2b,…お
よび前記外部回路接続用端子21,21,…のいずれの端子間
隔よりも小さい導電性粒子を前記狭巾端子2b,2b,…の巾
よりも小さい間隔で等間隔に埋込んだ接合材3が形成さ
れている。
Further, in FIG. 3, 2b, 2b, ... Are a plurality of external circuit connecting terminals 21 arranged on one side edge portion of the wiring board 1 on the wiring board joint surface (terminal arrangement portion) of the liquid crystal display panel 20. ,twenty one,
The display panel connection terminals are arranged correspondingly to the display panel connection terminals, and the display panel connection terminals 2b, 2b, .. The maximum particle size of the conductive adhesive is smaller than the width of the narrower one of the display panel connecting terminals 2b, 2b, ... And the external circuit connecting terminals 21, 21 ,. Is smaller than the width of the narrow terminals 2b, 2b, ... And the conductive particles are smaller than any of the terminal intervals of the display panel connecting terminals 2b, 2b, ... And the external circuit connecting terminals 21, 21 ,. The bonding material 3 is formed so as to be embedded at equal intervals with a small interval.

そして、前記LSIチップ10は、その各外部回路接続用端
子11,11,…を配線基板1面のLSIチップ接続用端子2a,2
a,…に対応させて前記接合材3の上に重ね、このLSIチ
ップ10と配線基板1とを相対的に押圧してその状態で接
合材3の絶縁性接着剤3aを硬化させることにより、第1
図および第2図に示すように、LSIチップ10の各端子11,
11,…と配線基板1の各端子2a,2a,…とを接合材3中の
導電性粒子4,4,…により導通接続させた状態で前記絶縁
性接着剤3aにより接着接合されている。
In the LSI chip 10, the external circuit connection terminals 11, 11, ... Are connected to the LSI chip connection terminals 2a, 2 on the surface of the wiring board 1.
By stacking on the bonding material 3 corresponding to a, ..., By relatively pressing the LSI chip 10 and the wiring substrate 1 and curing the insulating adhesive 3a of the bonding material 3 in that state, First
As shown in FIG. 2 and FIG. 2, each terminal 11,
, And the terminals 2a, 2a, ... Of the wiring board 1 are adhesively joined by the insulating adhesive 3a in a state in which they are electrically connected by the conductive particles 4, 4 ,.

なお、第1図および第2図において、18は配線基板1に
接合されたLSIチップ10をモールドするエポキシ樹脂等
のモールド樹脂であり、このモールド樹脂18は、LSIチ
ップ10の接合後に塗布される。また、第2図において、
12はLSIチップ10の基材(ここではN型基材)、13はP
型拡散層、14はN型拡散層であり、これら拡散層13,14
が形成されたチップ主面には酸化シリコン(SiO2)から
なる絶縁膜15が形成され、その上にはアルミニウムから
なる配線16が形成されている。この配線16は、前記絶縁
膜15に設けた開口部において前記拡散層13,14のうちの
所定の拡散層と導通されており、この配線16の導出端に
形成されたパッド部16aはそのまま外部回路接続用端子1
1とされている。17は前記配線16を覆う酸化シリコンか
らなる絶縁保護膜であり、この保護膜17は、前記端子2a
部分を除いてチップ全面に形成されている。
In FIG. 1 and FIG. 2, reference numeral 18 is a molding resin such as epoxy resin for molding the LSI chip 10 bonded to the wiring board 1, and the molding resin 18 is applied after the bonding of the LSI chip 10. . In addition, in FIG.
12 is the base material of the LSI chip 10 (here, N-type base material), 13 is P
The diffusion layers 13 and 14 are N-type diffusion layers.
An insulating film 15 made of silicon oxide (SiO 2 ) is formed on the main surface of the chip where is formed, and a wiring 16 made of aluminum is formed thereon. The wiring 16 is electrically connected to a predetermined diffusion layer of the diffusion layers 13 and 14 in the opening provided in the insulating film 15, and the pad portion 16a formed at the lead-out end of the wiring 16 is externally exposed as it is. Circuit connection terminal 1
It is supposed to be 1. Reference numeral 17 denotes an insulating protective film made of silicon oxide that covers the wiring 16, and the protective film 17 is used for the terminal 2a.
It is formed on the entire surface of the chip except for the portion.

また、前記液晶表示パネル20は、その配線基板接合面を
配線基板1の表示パネル接合面に形成した前記接合材3
の上に重ねて押圧し、接合材3の絶縁性接着剤3aを硬化
させることによって前記LSIチップ10と同様にして配線
基板1に接着接合されている。
Further, in the liquid crystal display panel 20, the bonding material 3 whose wiring board bonding surface is formed on the display panel bonding surface of the wiring board 1 is used.
It is bonded and bonded to the wiring board 1 in the same manner as the LSI chip 10 by stacking and pressing on the above and curing the insulating adhesive 3a of the bonding material 3.

次に、前記配線基板1への電子部品の接合手順を、前記
LSIチップ10の接合について第4図を参照し説明する。
Next, the procedure for joining the electronic components to the wiring board 1 will be described below.
Bonding of the LSI chip 10 will be described with reference to FIG.

まず、各配線2,2,…とLSIチップ接続用端子2a,2a,…お
よび表示パネル接続用端子2b,2b,…等を形成した配線基
板1面に、そのLSIチップ接合面全体にわたって絶縁性
接着剤3aを第4図(a)に示すように均一厚さに塗布す
る。なお、この絶縁性接着剤3aは、前記導電性粒子4,4,
…のうち最大粒子の粒径に応じて、例えば最大径粒子の
粒径が40μである場合は端子2a,2a上の層厚が40〜60μ
程度になるように塗布する。
First, the wiring board 1 surface on which the wirings 2, 2, ..., LSI chip connecting terminals 2a, 2a, .. and display panel connecting terminals 2b, 2b ,. The adhesive 3a is applied to a uniform thickness as shown in FIG. Incidentally, this insulating adhesive 3a, the conductive particles 4, 4,
Depending on the particle size of the largest particle, for example, when the particle size of the largest particle is 40μ, the layer thickness on terminals 2a, 2a is 40-60μ
Apply so that it becomes the extent.

次に、この絶縁性接着剤3aの塗布層の上に第4図(b)
に示すようにメッシュスクリーン5を載置する。このメ
ッシュスクリーン5は、テトロン等の樹脂繊維か、また
はエッチング等により微細な開口を形成したステンレス
等の薄板からなるもので、このメッシュスクリーン5
は、前記導電性粒子の4,4,…のうち最大粒子の粒径より
も大きくかつLSIチップ10の外部回路接続用端子11,11,
…と配線基板1面のLSIチップ接続用端子2a,2a,…との
うちの狭巾の端子(この実施例では配線基板1面のLSI
チップ接続用端子2a,2a,…)の巾およびこの各端子2a,2
a…間の間隔よりも小さい多数の開口5a,5a,…を、前記
各端子2a,2a,…の巾よりも小さい間隔で等間隔に形成し
たものとされている。なお、このメッシュスクリーン5
の厚さは、最大径の導電性粒子4の粒径とほぼ同じか、
あるいはそれよりわずかに厚くされている。
Next, on the coating layer of this insulating adhesive 3a, as shown in FIG.
The mesh screen 5 is placed as shown in FIG. The mesh screen 5 is made of resin fiber such as tetron or a thin plate of stainless steel or the like in which fine openings are formed by etching or the like.
Is larger than the particle diameter of the largest particle among the conductive particles 4, 4, ... And the external circuit connecting terminals 11, 11, of the LSI chip 10,
, And the narrower terminals of the LSI chip connection terminals 2a, 2a, ... on the wiring board 1 surface (in this embodiment, the LSI on the wiring board 1 surface
Width of chip connection terminals 2a, 2a,…) and each of these terminals 2a, 2
A large number of openings 5a, 5a, ..., Which are smaller than the intervals between a. In addition, this mesh screen 5
The thickness of is almost the same as the particle diameter of the conductive particles 4 having the maximum diameter,
Or slightly thicker than that.

この後は、第4図(c)に示すように前記メッシュスク
リーン5の上からその全面にわたって導電性粒子4,4,…
をほぼ均一厚さに散布し、次いでその上から第4図
(d)に示すようにローラ6等の加圧治具により加圧し
て、メッシュスクリーン5の各開口5a,5a,…内に入った
導電性粒子4,4,…を絶縁性接着剤3a中に押込んでやる。
この場合、導電性粒子4,4,…の粒径が全て最大粒径であ
れば、メッシュスクリーン5の各開口5a,5a,…内に1個
ずつ導電性粒子4,4,…が入るから絶縁性接着剤3a中に等
間隔に1個ずつの導電性粒子4,4,…が押込まれるが、導
電性粒子4,4,…の粒径を揃えることは歩留りの関係上コ
ストアップにつながるから、この実施例ではある程度小
径の導電性粒子4,4,…も使用している。従って、メッシ
ュスクリーン5の上から導電性粒子4,4,…を散布する
と、最大径の導電性粒子4はメッシュスクリーン5の開
口5aに1個ずつ入って絶縁性接着剤3a中に押込まれ、小
径の導電性粒子4はメッシュスクリーン5の開口5aに複
数個入って絶縁性接着剤3a中に押込まれるが、その場合
でも絶縁性接着剤3a中に押込まれる導電性粒子4,4,…の
間隔は実質的に等間隔になる。
After that, as shown in FIG. 4 (c), the conductive particles 4, 4, ...
Is sprayed to a substantially uniform thickness, and then, as shown in FIG. 4 (d), pressure is applied by a pressure jig such as a roller 6 to enter the openings 5a, 5a, ... Of the mesh screen 5. The conductive particles 4, 4, ... Are pushed into the insulating adhesive 3a.
In this case, if all the particle diameters of the conductive particles 4, 4, ... Are the maximum particle diameters, one conductive particle 4, 4, ... Is inserted in each opening 5a, 5a ,. One conductive particle 4,4, ... Is pressed into the insulating adhesive 3a at equal intervals, but making the particle size of the conductive particles 4,4 ,. Therefore, in this embodiment, the conductive particles 4, 4, ... Having a somewhat small diameter are also used. Therefore, when the conductive particles 4, 4, ... Are sprinkled on the mesh screen 5, the conductive particles 4 having the maximum diameter enter the openings 5a of the mesh screen 5 one by one and are pushed into the insulating adhesive 3a. A plurality of small-diameter conductive particles 4 enter the openings 5a of the mesh screen 5 and are pushed into the insulating adhesive 3a. Even in that case, the conductive particles 4,4, which are pushed into the insulating adhesive 3a, The intervals of ... become substantially equal.

このように絶縁性接着剤3a中に導電性粒子4,4,…を押込
んだ後は、散布した導電性粒子4,4,…を真空吸引により
吸引し、絶縁性接着剤3a中に押込まれてこの絶縁性接着
剤3aに保持された導電性粒子4,4,…を除く導電性粒子4,
4,…を第4図(e)に示すように除去する。なお、この
除去された導電性粒子4,4,…は回収して再使用する。
After the conductive particles 4, 4, ... have been pushed into the insulating adhesive 3a in this way, the scattered conductive particles 4, 4, ... are sucked by vacuum suction and pushed into the insulating adhesive 3a. The conductive particles 4, excluding the conductive particles 4, 4, held by the insulating adhesive 3a
4, ... Are removed as shown in FIG. The removed conductive particles 4, 4, ... Are recovered and reused.

このようにして絶縁性接着剤3中に多数の導電性粒子4,
4,…を埋込んだ接合材3形成した後は、前記メッシュス
クリーン5を撤去して、前記接合材3の上に、LSIチッ
プ10をその外部回路接続用端子11,11…を配線基板1面
のLSIチップ接続用端子2a,2a,…と対応させて重ね、こ
のLSIチップ10と配線基板1とを相対的に押圧(例えばL
SIチップ10を加圧)して、LSIチップ10と配線基板1の
両方の端子11,2aを前記導電性粒子4により導通接続さ
せるとともに、この押圧状態で前記絶縁性接着剤3aを硬
化させてLSIチップ10を配線基板1に接着接合する。
In this way, a large number of conductive particles 4,
After the bonding material 3 in which 4, ... Is embedded is formed, the mesh screen 5 is removed, and the LSI chip 10 and the external circuit connection terminals 11, 11 ... The LSI chip connection terminals 2a, 2a, ... on the surface are overlapped with each other and the LSI chip 10 and the wiring board 1 are relatively pressed (for example, L
The SI chip 10 is pressed) to electrically connect the terminals 11 and 2a of both the LSI chip 10 and the wiring board 1 by the conductive particles 4, and the insulating adhesive 3a is cured in this pressed state. The LSI chip 10 is adhesively bonded to the wiring board 1.

なお、ここではLSIチップ10の接合方法について説明し
たが、液晶表示パネル20も上記と同様な方法で接合す
る。
Although the method of joining the LSI chips 10 has been described here, the liquid crystal display panel 20 is also joined by the same method as described above.

なお、前記絶縁性接着剤3aは、常温硬化型のものでも、
一般にホットメルト型と呼ばれている熱可塑性接着剤で
も、熱硬化型のものでも、あるいはUVインク等でもよ
く、絶縁性接着剤3aとして常温硬化型接着剤またはUVイ
ンクを使用する場合は、絶縁性接着剤3a中に導電性粒子
4,4,…を埋込んで接合材3を形成した後直ちに電子部品
を接合するか、あるいは形成した接合材3の上に剥離紙
を被着して絶縁性接着剤3を自然硬化しないように保護
しておき、電子部品接合時に剥離紙を剥がして直ちに電
子部品を接合すればよい。また、絶縁性接着剤3aとして
ホットメルト型と呼ばれている熱可塑性接着剤または熱
硬化型接着剤を使用する場合は、接合材3を形成した後
に熱風乾燥炉または赤外線等により絶縁性接着剤3aを70
〜130℃の温度で乾燥させておき、電子部品の接合時
に、接合材3の上に電子部品を重ねてプレス治具または
加圧ローラ等により100〜150℃の温度で加熱加圧すれば
よい。
The insulating adhesive 3a may be a room temperature curing type,
It may be a thermoplastic adhesive that is generally called a hot melt type, a thermosetting type, or a UV ink.If a room temperature curing type adhesive or UV ink is used as the insulating adhesive 3a, insulation Particles in conductive adhesive 3a
Immediately after the bonding material 3 is formed by embedding the bonding material 4, 4, ... The protective paper may be protected and the release paper may be peeled off at the time of joining the electronic parts to join the electronic parts immediately. When a thermoplastic adhesive or a thermosetting adhesive called hot melt type is used as the insulating adhesive 3a, the insulating adhesive is formed by a hot air drying oven or infrared rays after forming the bonding material 3. 3a to 70
It may be dried at a temperature of ˜130 ° C., and at the time of joining the electronic components, the electronic components may be overlaid on the bonding material 3 and heated and pressed at a temperature of 100 to 150 ° C. by a press jig or a pressure roller. .

しかして、上記接合構造では、前記LSIチップ10や液晶
表示パネル20等の電子部品と配線基板1とを、絶縁性接
着剤3a中に導電性粒子4,4,…を埋込んだ接合材3を介し
て接着接合しているから、電子部品と配線基板1とを相
対的に押圧して絶縁性接着剤3aを硬化させるだけで配線
基板1に電子部品をその両方の端子を互いに導通接続さ
せた状態で接合することができ、従って、異方導電性接
着剤によって電子部品を接着接合する方法と同程度の短
い時間で能率よく電子部品を取付けることができる。ま
た、この接合構造では、前記導電性粒子4,4,…の最大径
を、電子部品と配線基板1との両方の端子のうち狭巾の
端子の巾よりも小さくかつ前記電子部品と前記配線基板
1とのいずれの端子間隔よりも小さくし、かつこの導電
性粒子4,4,…を、前記狭巾端子の巾よりも小さい間隔で
等間隔に絶縁性接着剤3a中に埋込んでいるために、対応
する全ての端子間に少なくとも1つの導電性粒子4が必
ず介在されることになり、従って、異方導電性接着剤を
用いた場合のように導電性粒子の分布のばらつきにより
導通不良部分が発生することはないから、電子部品の各
端子を配線基板1の各端子に導通不良部分を生ずること
なく確実に導通接続することができる。さらに、上記接
合方法では、配線基板1面に塗布した絶縁性接着剤3aの
上にメッシュスクリーン5を重ねてこのメッシュスクリ
ーン5の上から導電性粒子4,4,…を散布し、この導電性
粒子4,4,…のうちメッシュスクリーン5の各開口5a,5a,
…内に入った導電性粒子4,4,…を絶縁性接着剤3a中に押
込んで接合材3を形成しているから、前記絶縁性接着剤
3a中の導電性粒子4,4,…の分布を確実に等間隔にするこ
とができる。
Thus, in the above-mentioned joining structure, the electronic component such as the LSI chip 10 and the liquid crystal display panel 20 and the wiring board 1 are bonded to each other by the bonding material 3 in which the conductive particles 4, 4, ... Are embedded in the insulating adhesive 3a. Since they are adhesively bonded to each other by simply pressing the electronic component and the wiring board 1 relatively to cure the insulating adhesive 3a, the electronic component is electrically connected to the wiring board 1 at both terminals thereof. Therefore, the electronic components can be efficiently attached in as short a time as the method of adhesively joining the electronic components with the anisotropic conductive adhesive. Further, in this joint structure, the maximum diameter of the conductive particles 4, 4, ... Is smaller than the width of a narrow terminal of both terminals of the electronic component and the wiring board 1, and the electronic component and the wiring are It is made smaller than any terminal interval with the substrate 1, and the conductive particles 4, 4, ... Are embedded in the insulating adhesive 3a at equal intervals smaller than the width of the narrow terminal. Therefore, at least one conductive particle 4 is inevitably interposed between all corresponding terminals, and therefore conduction is caused by the uneven distribution of the conductive particles as in the case of using the anisotropic conductive adhesive. Since no defective portion is generated, each terminal of the electronic component can be surely electrically connected to each terminal of the wiring board 1 without generating a defective portion. Further, in the above-mentioned joining method, the mesh screen 5 is laid on the insulating adhesive 3a applied to the surface of the wiring substrate 1, and the conductive particles 4, 4, ... Of the particles 4, 4, ..., the openings 5a, 5a of the mesh screen 5
Since the conductive particles 4, 4, ... Entered inside are pushed into the insulating adhesive 3a to form the bonding material 3, the insulating adhesive is
It is possible to surely make the distribution of the conductive particles 4, 4, ... In 3a evenly spaced.

なお、上記実施例では、電子部品を接着接合する接合材
3を配線基板1側に形成しているが、この接合材3は第
5図に示すように電子部品例えばLSIチップ10の配線基
板接合面に形成してもよく、また、前記LSIチップ10の
外部回路接続用端子11,11,…は、第2図に示したパッド
部16aの上に金等をメッキしてバンプ16bを形成した第5
図に示すような構造としてもよい。
In the above embodiment, the bonding material 3 for adhesively bonding the electronic components is formed on the wiring board 1 side. However, as shown in FIG. 5, the bonding material 3 is bonded to the electronic components, for example, the wiring board of the LSI chip 10. The external circuit connection terminals 11, 11, ... Of the LSI chip 10 may have a bump 16b formed by plating gold or the like on the pad portion 16a shown in FIG. Fifth
The structure shown in the figure may be used.

また、上記実施例では、配線基板1と電子部品の接合面
全体に接合材3を介在させているが、この接合材3は端
子配列部分にのみ介在させてもよく、さらに前記接合材
3は、配線基板1または電子部品に塗布する代わりに、
あらかじめシート状に成形しておいて配線基板1と電子
部品との間に挟み込むようにしてもよい。
Further, in the above embodiment, the bonding material 3 is interposed on the entire bonding surface between the wiring board 1 and the electronic component. However, the bonding material 3 may be interposed only in the terminal array portion. , Instead of applying to the wiring board 1 or electronic parts,
It may be formed into a sheet shape in advance and sandwiched between the wiring board 1 and the electronic component.

〔発明の効果〕〔The invention's effect〕

この発明によれば、絶縁性接着剤中に導電性粒子を埋設
した接合材を介して電子部品と配線基板とを接着接合し
ているから、異方導電性接着剤によって電子部品を接着
接合する方法と同程度の短い時間で能率よく電子部品を
配線基板に取付けることができるとともに、前記導電性
粒子を電子部品と配線基板との両方の端子のうち狭巾の
端子の巾およびこの狭巾端子間の間隔よりも小さい多数
の開口を前記狭巾端子の巾よりも小さい間隔で等間隔に
形成したメッシュスクリーンを介して絶縁性接着剤中に
埋込むことにより、対応する全ての端子間に少なくとも
1つの導電性粒子が必ず介在されるようにしているか
ら、異方導電性接着剤を用いた場合における導電性粒子
の分布のばらつきによる導通不良部分の発生をなくし
て、電子部品の各端子を基板面の各端子に導通不良部分
を生ずることなく確実に導通接続することができる。
According to the present invention, since the electronic component and the wiring board are adhesively joined via the joining material in which the conductive particles are embedded in the insulating adhesive, the electronic component is adhesively joined by the anisotropic conductive adhesive. The electronic component can be efficiently attached to the wiring board in a short time as long as the method, and the conductive particles have the narrow width of the terminals of both the electronic component and the wiring board and the narrow width terminal. By embedding a large number of openings, which are smaller than the intervals between them, in an insulating adhesive through mesh screens formed at equal intervals at intervals smaller than the width of the narrow terminals, at least between all corresponding terminals. Since one conductive particle is always interposed, the occurrence of defective conduction due to uneven distribution of conductive particles when an anisotropic conductive adhesive is used is eliminated, and each terminal of an electronic component is eliminated. It can be reliably conductively connected without causing conduction failure portions to the terminals of the substrate surface.

【図面の簡単な説明】[Brief description of drawings]

第1図〜第4図はこの発明の一実施例を示したもので、
第1図は第3図のB−B線に沿う拡大断面図、第2図は
第1図のA−A線に沿う拡大断面図、第3図は配線基板
と電子部品の斜視図、第4図は電子部品の接合方法を工
程順に示す配線基板の端子配列線に沿う断面図である。
第5図はこの発明の他の実施例を示す配線基板と電子部
品の端子配列線に沿う断面図である。 1……配線基板、2……配線、2a……LSIチップ接続用
端子、2b……表示パネル接続用端子、3……接合材、3a
……絶縁性接着剤、4……導電性粒子、5……メッシュ
スクリーン、5a……開口、6……ローラ、10……LSIチ
ップ、11……外部回路接続用端子、20……液晶表示パネ
ル、21……外部回路接続用端子。
1 to 4 show an embodiment of the present invention.
1 is an enlarged sectional view taken along line BB in FIG. 3, FIG. 2 is an enlarged sectional view taken along line AA in FIG. 1, FIG. 3 is a perspective view of a wiring board and electronic parts, FIG. 4 is a sectional view taken along the terminal arrangement line of the wiring board, showing the method of joining electronic components in the order of steps.
FIG. 5 is a sectional view taken along the terminal arrangement line of the wiring board and the electronic component showing another embodiment of the present invention. 1 ... Wiring board, 2 ... Wiring, 2a ... LSI chip connection terminal, 2b ... Display panel connection terminal, 3 ... Bonding material, 3a
Insulating adhesive, 4 conductive particles, 5 mesh screen, 5a opening, 6 roller, 10 LSI chip, 11 external circuit connection terminal, 20 liquid crystal display Panel, 21 ... External circuit connection terminal.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 正木 久士 東京都西多摩郡羽村町栄町3丁目2番1号 カシオ計算機株式会社羽村技術センター 内 (72)発明者 鑓田 好男 東京都西多摩郡羽村町栄町3丁目2番1号 カシオ計算機株式会社羽村技術センター 内 (72)発明者 厚見 好則 東京都西多摩郡羽村町栄町3丁目2番1号 カシオ計算機株式会社羽村技術センター 内 (72)発明者 玉木 敏晴 東京都西多摩郡羽村町栄町3丁目2番1号 カシオ計算機株式会社羽村技術センター 内 (56)参考文献 特開 昭51−21192(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hisashi Masaki Hisashi Masaki 3-2-1, Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (72) Inventor Yoshio Akita Sakae-cho, Hamura-cho, Nishitama-gun, Tokyo 3-2-1, Casio Computer Co., Ltd., Hamura Technology Center (72) Inventor Yoshinori Atsumi 3-2-1, Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd., Hamura Technology Center (72) Inventor Tamaki Toshiharu 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd., Hamura Technical Center (56) References JP-A-51-21192 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】配線基板との接合面に複数の外部回路接続
用端子を形成した電子部品を、前記電子部品の各端子と
対応する複数の電子部品接続用端子を形成した配線基板
面に直接接合する電子部品の接合方法において、前記電
子部品と前記配線基板との接合面の一方に絶縁性接着剤
を塗布した後、この絶縁性接着剤上に、前記電子部品と
前記配線基板との両方の端子のうち狭巾の端子の巾より
も小さくかつ前記電子部品と前記配線基板とのいずれの
端子間隔よりも小さい多数の開口を前記狭巾端子の巾よ
りも小さい間隔で等間隔に形成したメッシュスクリーン
を重ねて、その上から導電性粒子を散布し、この導電性
粒子のうち前記メッシュスクリーンの各開口に入った導
電性粒子を前記絶縁性接着剤中に押込んで前記絶縁性接
着剤中に多数の導電性粒子を等間隔に埋込み、この後前
記電子部品と前記配線基板とを重ねて相対的に押圧して
前記電子部品と前記配線基板とを接着接合することを特
徴とする電子部品の接合方法。
1. An electronic component having a plurality of external circuit connecting terminals formed on a joint surface with a wiring board is directly attached to a wiring substrate surface having a plurality of electronic component connecting terminals corresponding to the respective terminals of the electronic component. In a method of joining electronic components to be joined, after applying an insulating adhesive to one of the joining surfaces of the electronic component and the wiring board, both the electronic component and the wiring board on the insulating adhesive A plurality of openings smaller than the width of the narrow terminals and smaller than any terminal spacing between the electronic component and the wiring board are formed at equal intervals smaller than the width of the narrow terminals. The mesh screens are overlapped, and the conductive particles are sprayed on the mesh screens. The conductive particles in the openings of the mesh screen among the conductive particles are pushed into the insulating adhesive to form the insulating adhesive. Multiple leads to Embedded sex particles at equal intervals, the joining method of the electronic component, characterized in that by relatively pressing superposed and said wiring board and the electronic component after the bonding bonding the wiring board and the electronic component.
JP60033948A 1985-02-22 1985-02-22 How to join electronic components Expired - Lifetime JPH0779192B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60033948A JPH0779192B2 (en) 1985-02-22 1985-02-22 How to join electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60033948A JPH0779192B2 (en) 1985-02-22 1985-02-22 How to join electronic components

Publications (2)

Publication Number Publication Date
JPS61194796A JPS61194796A (en) 1986-08-29
JPH0779192B2 true JPH0779192B2 (en) 1995-08-23

Family

ID=12400727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60033948A Expired - Lifetime JPH0779192B2 (en) 1985-02-22 1985-02-22 How to join electronic components

Country Status (1)

Country Link
JP (1) JPH0779192B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001184618A (en) * 1999-12-24 2001-07-06 Hitachi Ltd Magnetic disk drive

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015083364A1 (en) 2013-12-02 2015-06-11 東芝ホクト電子株式会社 Light-emission device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5121192A (en) * 1974-08-14 1976-02-20 Seikosha Kk DODENSEISETSU CHAKUSHIITO

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001184618A (en) * 1999-12-24 2001-07-06 Hitachi Ltd Magnetic disk drive

Also Published As

Publication number Publication date
JPS61194796A (en) 1986-08-29

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