JPH0779227B2 - comparator - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 5 and 6) Problems to be solved by the invention Means for solving the problems Action Example Explanation of the principle of the present invention (No. Fig. 1) First embodiment of the present invention (Figs. 2 and 3) Second embodiment of the present invention (Fig. 4) Effect of the invention [Outline] A reference voltage and an input voltage are alternately selected and input to obtain a comparison result. Regarding a comparator, a switch circuit for alternately selecting and outputting a reference voltage and an input voltage, and an output of the switch circuit, for the purpose of providing a comparator capable of suppressing a flow-through current without increasing the circuit scale of the comparator. On the side, a circuit unit that serves as a switch that short-circuits or non-short-circuits the capacitor and the first inverter connected via the capacitor and the input / output terminal of the first inverter is cascaded in one or more stages. A comparator comprising a connected comparison circuit section and a semiconductor circuit section for selectively outputting and outputting an output signal of the comparison circuit section, wherein the semiconductor circuit section has a source connected to a high potential power line side. A first P-channel transistor having a gate for receiving the output of the comparison circuit unit, a source connected to the low potential power line side, and a first N-channel transistor for receiving the output of the comparison circuit unit at the gate; It is connected between the potential power supply line side and the output terminal, and the gate is connected to the first P
A second P-channel transistor connected to the drain of the channel transistor, and a second N-channel connected to the drain of the first N-channel transistor while being connected between the low potential power supply side and the output terminal. A transistor is connected between the drain of the first P-channel transistor and the drain of the first N-channel transistor.

[Industrial application field]

The present invention relates to a comparator, and more particularly, to a comparator that is used in an A / D converter or the like and obtains a comparison result by alternately selecting and inputting a reference voltage and an input voltage, and particularly, low power consumption and the number of elements of the circuit. The present invention relates to a comparator that is reduced.

A high-speed A / D converter for image processing or the like employs a parallel or serial-parallel system, and a chopper type comparator is often used as its comparator. Since the chopper type comparator has a simple structure and high speed, it is advantageous over other types of comparators when a large number of parallel or series-parallel type comparators are used.

[Conventional technology]

As a conventional chopper type comparator of this type, there is one as shown in FIG. 5, for example. In FIG. 5, 1
Is a chopper type comparator, S ₁ is a switch for selectively outputting the reference voltage V _ref , S ₂ is a switch for selectively outputting the input voltage V _in , C ₁ , C ₂ are capacitors, I ₁ , I ₂ , I
₃ is an inverter connected in series with capacitors C ₁ and C ₂ ,
S ₃ and S ₄ are connected in parallel to the inverters I ₁ and I ₂ , respectively,
A switch that short-circuits or non-short-circuits the input / output terminals of I ₁ and I ₂ . The inverter I ₁ and the switch S ₃ constitute the chopper stage 2 and the inverter I ₂ and the switch S ₄ constitute the chopper stage 3, respectively. The switches S _{1 to} S ₄ , the capacitors C ₁ and C ₂ and the inverters I _{1 to} I ₃ are comparators. It constitutes part 4. The output of the comparator unit 4 is the inverters I ₄ , I ₅ and the switches S ₅ , S ₆
Is input to the latch unit 5.

In this configuration, focusing on the first stage chopper stage 2,
If the switches S ₁ and S ₃ are now ON, the inverter I
_Since the input and output of ₁ are shorted, V _B = V _C.
The input voltage of the capacitor C _{1 at} this time is V _A = V _ref, and the voltage charged in the capacitor C ₁ is V _ref −V _B. Since switches S ₁ and S ₃ are off, switch S ₂
When is turned on, V _A = V _in and the change amount dV _A = V _ref −V _in . In this case, the change of the input voltage V _B of the inverter I ₁ dV
_B is equal to dV _A. When the gain of the inverter I ₁ is represented by G, the variation of the output voltage V _C dV _C = −G × dV _B = G × (V _in −V
_ref ). Next stage capacitor C ₂ and chopper stage 3
Is for amplifying the gain of the first stage chopper stage 2,
The inverter I ₃ has a function of amplifying the voltage of V _in −V _ref .

However, this chopper type comparator 1 has two modes, a reset mode and a comparison mode. In the reset mode, a through current flows between V _{DD and} V _SS in the chopper stages 2 and 3, so that power consumption increases. There was a drawback. Therefore, it is necessary to prevent the shoot-through current in the reset mode in order to suppress the power consumption.

The speed and accuracy of the chopper type comparator 1 depend on the speed accuracy of the chopper stages 2 and 3, and various improvements such as the transistor size and the number of chopper stages have been added. For example, there is such one as shown in FIG. 6 (b) (see Japanese Patent Laid-Open No. 1-133410). This is a chopper type comparator 1 shown in FIG. 6 (a).
In the next stage of the chopper stage 3, inverters I ₃ and the switch
By providing a clocked inverter 6 instead of S ₃ , a through current is prevented from flowing to the third-stage inverter I ₃ at the time of reset (at the time of auto zero).

[Problems to be Solved by the Invention]

However, even in such a conventional chopper type comparator, the chopper 2 which is most widely used at present.
In the chopper type comparator with one stage and one inverter, a through current flows through the two chopper stages. Further, if the number of chopper stages is reduced or the process condition is changed to the transistor size to reduce the through current, the speed and accuracy generally tend to deteriorate.

Therefore, an object of the present invention is to provide a comparator capable of suppressing a shoot-through current without increasing the circuit scale of the comparator.

[Means for Solving the Problems]

In order to achieve the above object, the comparator according to the present invention is
A switch circuit for alternately selecting and outputting the reference voltage and the input voltage, a capacitor, a first inverter connected via the capacitor, and an input / output terminal of the first inverter on the output side of the switch circuit. A comparator including a comparison circuit unit in which circuit units each including a short-circuited or non-short-circuited switch are cascade-connected in one or more stages, and a semiconductor circuit unit that selectively outputs an output signal of the comparison circuit unit and extracts the output signal. In the semiconductor circuit section, the source is connected to the high-potential power line side, the gate is connected to the first P-channel transistor for receiving the output of the comparison circuit section, and the source is connected to the low-potential power line side. And a first N-channel transistor for receiving the output of the comparison circuit section, and a gate connected to the high potential power line side and the output terminal.
A second P-channel transistor connected to the drain of the channel transistor, and a second N-channel connected to the drain of the first N-channel transistor while being connected between the low potential power supply side and the output terminal. A transistor is connected between the drain of the first P-channel transistor and the drain of the first N-channel transistor.

[Action]

In the present invention, the first P-channel transistor and the first N-channel
A switch is provided between the channel transistor and the second P-channel transistor, the gates of which receive the potential between the first P-channel transistor and the switch and between the first N-channel transistor and the switch at the subsequent stage. And a second N-channel transistor is provided.

Therefore, when the switch is turned off during the reset period, the switching of one switch causes the inverter composed of the first P-channel transistor and the first N-channel transistor, the second P-channel transistor and the second N-channel transistor to be switched. Through current flowing through the two inverters of the inverter is prevented. Therefore, a large gain can be obtained in the circuit configuration in which the inverters are provided in two stages, and a shoot-through current flowing in both inverters can be appropriately prevented, and as a result, the power consumption of the comparator can be reduced without impairing the speed. It becomes possible to reduce.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

Description of Principle FIG. 1 is an explanatory view of the principle of the present invention, in which the same components as those of the conventional example shown in FIG.

In FIG. 1, reference numeral 11 is a semiconductor circuit (semiconductor circuit section) provided on the output side of a comparator section (comparison circuit section) 10 of a chopper type comparator, and the semiconductor circuit 11 outputs the output signal of the chopper stage 2 to a latch section 5 It is amplified by the switching operation and transmitted. In the semiconductor circuit 11, the source is connected to the high potential power supply V _DD , and the drain is connected to a gate of a P-channel transistor T ₁ (second P-channel transistor) described later and a switch S ₁₁ (predetermined switch) to be described later. _A P-channel transistor T _A (first P-channel transistor T _A (first P-channel transistor) connected to the drain of the channel transistor T _B (first N-channel transistor) and connected to the gate of the N-channel transistor T _B to receive the output of the chopper stage 2 Channel transistor), the source is connected to the low-potential-side power supply V _SS , and the drain is an N-channel transistor T ₂ (second N-channel transistor) described later.
It is connected to the drain of the P-channel transistor T _A through the gate and switches S _11, gate P
An N-channel transistor T _B connected to the gate of the channel transistor T _A , a source connected to V _DD , a drain connected to the drain of the N-channel transistor T ₂ ,
The gate is a P-channel transistor T ₁ connected between the P-channel transistor T _A and the switch S ₁₁ , and the source is
N-channel transistor T connected to V _SS and having its gate connected between N-channel transistor T _B and switch S _11
2 and. That is, the semiconductor circuit 11 has P
Channel transistor T _A and N channel transistor
Insert the switch S ₁₁ to the middle of the inverter 12 composed of T _B, the next-stage inverter consisting respective transistors T _A and the switch S _11, between the T _B from P-channel transistor T ₁ and N-channel transistor T ₂ It is connected to each of the 13 gates. The switch S ₁₁ is a switch element that opens and closes according to the clock pulse signal A.

On the other hand, the output side of the semiconductor circuit 11 is connected to the latch section 14,
Specifically, the node connecting the drains of the P-channel transistor T ₁ and the N-channel transistor T ₂ is connected in series with the two-stage inverters I ₄ and I ₅ , and the input side of the front-stage inverter I ₄ and the rear-stage inverter I _{5 are connected.} Is connected to the input side of the latch section 14 (the input side of the inverter I ₄ ) whose output side is connected via the switch S ₆ .

With the above configuration, switch S ₁₁ is turned off during the reset period.
Setting it to FF suppresses the through current between V _{DD and} V _SS . At this time, at the same time, the P-channel transistor and the N-channel transistor T ₂ are cut off, so that S ₁₁
With an inverter 12 consisting of T _A and T _B
Of the two inverters of the inverter 13 consisting of T ₁ and T ₂
The through current between V _{DD and} V _SS can be suppressed. further,
At the same time, in the latter latch section 14, the switch of S ₁₁
Turn on the switch of S ₆ to retain the data before it becomes FF
Let me latch. In this case, in the circuit of the conventional type shown in FIG. 5, the latch section 5 placed after the comparator section 4 required a circuit having two switches and two inverters. 11
Therefore, the through current between V _{DD and} V _SS at the time of resetting two stages of the inverter can be suppressed by one switch S ₁₁ , and one switch (corresponding to the capacitor C ₂ in FIG. 5) can be omitted. Further, a logic gate such as a NAND gate or an OR gate may be directly connected when a latch is not particularly required.

First Embodiment Hereinafter, an embodiment will be described based on the above-mentioned basic principle. 2 and 3 are diagrams showing a first embodiment of the comparator according to the present invention, in which the same components as those of the explanation of the principle shown in FIG. 1 and the conventional example shown in FIG. ing.

In FIG. 2, reference numeral 21 denotes a chopper type comparator (comparator), and the chopper type comparator 21 has a switch S ₁ (switch circuit) for selectively outputting the reference voltage V _ref by the clock signal CK1, ▲ ▼ 1, and a clock signal CK2, ▲.
▼ switch S ₂ to select and output the input voltage V _in by 2
(Switch circuit), capacitor C ₁ , inverter I ₁ (first inverter) connected in series with capacitor C ₁ , and switch S ₃ connected in parallel with inverter I ₁ and forming chopper stage 2 with inverter I _1. And a comparator section 22 including the semiconductor circuit 11 and a latch section (latch circuit) 14 for latching an output signal of the comparator section 22. Here, the comparator unit 22 and the latch unit
The clock signal CK shown in FIG.
1 is supplied to switches S ₂ , S ₁₁ and S ₆ in the same figure (b).
The clock signal CK2 shown in (2) is supplied, and each switch is turned on at "L" level and turned off at "H" level.

As described above, in this embodiment, the switch S ₁₁ is provided between the P-channel transistor T _A and the N-channel transistor T _B forming the inverter 12 of the semiconductor circuit 11, and each of the transistors T _A , T _B and the switch S is further provided. _An inverter 13 including a P-channel transistor T ₁ and an N-channel transistor T ₂ whose gates receive the potential between ₁₁ is provided. Therefore, in the configuration of two inverters,
Through current of the stage inverter is prevented. That is, in the case of preventing the through current by using the clocked inverter 6 shown in FIG. 6 (b), the through current of one stage of the inverter is simply prevented, and the gain equivalent to that of this embodiment is obtained. Therefore, it is necessary to add one stage of inverter. When an inverter is added, the through current of the added inverter cannot be suppressed. On the other hand, in the present embodiment, one switch S ₁₁ can prevent the through current of the two-stage inverters 12 and 13, so that the through current at the time of auto-zero (when V _ref ON) of the semiconductor chip 21 is surely prevented. However, a large gain can be obtained by the two-stage configuration of the inverter. Further, the circuit scale can be realized with a size substantially equal to that of FIG. 6 (b).

Therefore, according to the present embodiment, the power consumption of the chopper type comparator can be suppressed without impairing the speed and by reducing the circuit scale.

FIG. 4 is a diagram showing a second embodiment of the comparator according to the present invention, and the same components as those of the first embodiment shown in FIG. 2 are designated by the same reference numerals.

As shown in FIG. 4, this embodiment is an example in which the output of the comparator unit 22 is not latched.
N ₀ is input to the input terminal of the NAND gate 23, and the NAND gate 23
The clock signal CK2 is input to the other input terminal of
The output N _X is output from the D gate 23. In this case, when CK2 is “L” and N ₀ is floating, the NAND gate 23 fixes N _X to “H”. The operation timing is the same as that of FIG.

Therefore, even in this embodiment, the same effect as that of the first embodiment can be obtained.

〔The invention's effect〕

According to the present invention, it is possible to suppress the through current without increasing the circuit scale of the comparator, reduce power consumption, and reduce the number of elements in the circuit.

[Brief description of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIGS. 2 and 3 are diagrams showing a first embodiment of a comparator according to the present invention, FIG. 2 is a circuit diagram of the comparator, and FIG. 3 is its operation timing. FIG. 4 is a circuit diagram of a comparator showing a second embodiment of the comparator according to the present invention, FIGS. 5 and 6 are diagrams showing a conventional comparator, FIG. 5 is its circuit diagram, and FIG. It is a circuit diagram of the main part. 2 ... Chopper stage, 10 ... Comparator part (comparison circuit part), 11 ... Semiconductor circuit (semiconductor circuit part), 12, 13 ... Inverter, 14 ... Latch part (latch circuit), 21 ... Chopper type Comparator (comparator), 22 …… Comparator part (comparator circuit part), 23 …… NAND gate (logic gate), S ₁ , S ₂ …… Switch (switch circuit), S ₃ , S ₆ …… Switch, S ₁₁ ...... Switch (predetermined switch), C ₁ …… Capacitor, I ₁ , I ₄ , I ₅ …… Inverter (first inverter), T _A …… P channel transistor (first P channel transistor), T _B ...... N-channel transistor (first N-channel transistor), T ₁ ...... P-channel transistor (second P-channel transistor), T ₂ ...... N-channel transistor (second N-channel transistor).

Claims (1)

[Claims] 1. A switch circuit for alternately selecting and outputting a reference voltage and an input voltage, a capacitor on the output side of the switch circuit, a first inverter connected via the capacitor, and a first inverter of the first inverter. A comparison circuit unit in which a circuit unit including a switch that short-circuits or non-short-circuits the input and output terminals is cascaded in one or more stages, and a semiconductor circuit unit that selectively outputs and outputs an output signal of the comparison circuit unit, A first P-channel transistor having a source connected to a high potential power line side and having a gate for receiving an output of the comparison circuit section; and a source having a low potential power line side. And a first N-channel transistor connected to the gate of the first N-channel transistor for receiving the output of the comparator circuit section, and connected between the high potential power line side and the output terminal, A second P-channel transistor connected to the drain of the channel transistor, and a second N-channel transistor connected between the low potential power supply side and the output terminal and having its gate connected to the drain of the first N-channel transistor. A comparator comprising: a channel transistor; and a switch connected between the drain of the first P-channel transistor and the drain of the first N-channel transistor.