JPH0779248B2 - Combinational logic circuit for decoder - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a combinational logic circuit, and more particularly to a combinational logic circuit for a decoder in a semiconductor integrated circuit.

2. Description of the Related Art FIG. 3 shows an example of a conventional combinational logic circuit for a decoder. Although the output of the actual combinational logic circuit for decoder is very large, the case of the combinational logic circuit for decoder having 16 outputs as shown in FIG. 3 will be described here. The two inputs of the 2-input NAND circuits 1 to 16 have two sets of address signal lines A _{1 to} A ₄ and B _{1 to} B ₄ as shown in FIG.
Are connected to each other at connection point C. At this time, A ₁ ~
When one signal line in A ₄ becomes active (activate) and at the same time one signal line in B _{1 to} B ₄ becomes active (activate), One becomes active. The truth table in this conventional example is shown below.

Problems to be Solved by the Invention In such a conventional example, the coding area in FIG.
NAND selected in A and coding area B
The gate is coded. At this time,
16 wirings 21 to 36 facing the coding area A and 16 wirings 41 to 56 facing the coding area B are required. Generally, in the conventional circuit, when the number of outputs is n, the total is 2n.
Wiring is required toward the coding area of the book. However, as the density of semiconductor memory devices has increased, it has become necessary to reduce the decoder pitch d. However, in the case of the conventional example, basically, for the number n of outputs, a wiring toward the coding area of 2n is required, which becomes a problem when trying to reduce the decoder pitch, and finally, in the semiconductor integrated circuit. This leads to a decrease in the degree of integration of the circuit.

The present invention has been made in view of the above problems, and an object of the present invention is to solve the problem that the decoder pitch inherent in the conventional combinational logic circuit for decoder cannot be reduced.

A combinational logic circuit for a decoder according to the present invention has a two-input logic circuit arranged in series, one input of adjacent two-input logic circuits is sequentially connected, and this connection point Are sequentially connected to the input lines from the two coding areas,
In any of the coding areas, the coding point, which is a connection point between the input line from the coding area and the address information line, is always at a different position on the input line from the adjacent coding area.

Effects According to the present invention, it is possible to significantly reduce the number of wirings toward the coding area, and it is possible to further increase the integration density of the combinational logic circuit.

Example 1 A first example of the present invention is shown in FIG. Here, a case of a combinational logic circuit for a decoder having 16 outputs will be described as in the case of the description of the conventional example. The 2-input NAND circuits 1 to 16 are arranged in series and one input of adjacent 2-input NAND circuits are connected to each other. Further, wirings 21 to 29 and 41 to 48 from this connection point are connected to the address signal lines in the coding area A and the coding area B, respectively.

At this time, when _one signal line in A _{1 to} A ₄ becomes active and at the same time _one signal line in B _{1 to} B ₄ becomes active, one of NAND circuits 1 to 16 is selected. Being activated, it becomes active and outputs. The truth table in this embodiment is shown below.

According to the present invention, in general, when n outputs are required, only wirings directed to a total of (n + 1) coding areas are required, which makes it possible to reduce the decoder pitch and, finally, the semiconductor. Enables high-density integrated circuits.

FIG. 2 shows a second embodiment of the present invention. The difference from the first embodiment is that signals are created in advance by the signal lines A _{1 to} A ₂ and the signal lines B _{1 to} B _2, and the signals are continuously connected and one input is connected to another 2 This is the point of inputting to the connection point of the input logic circuit. The truth table of this is shown below.

By adopting such a method, it is possible to prevent the number of input address signal lines from increasing that much even in a decoder combination logic circuit that requires a large number of outputs.

In the first and second embodiments, the NAND circuit is used as the two-input logic circuit for explanation, but this does not limit the effect of the present invention to NAND.

Further, by considering the power supply of the inverter circuit as one input, it is possible to construct a combinational logic circuit similar to the first and second embodiments. In this case, the inverter circuit has a simpler internal structure than the NAND circuit and the AND circuit, and therefore, there is an advantage that the entire combinational circuit can be made smaller.

EFFECTS OF THE INVENTION The present invention is a combinational logic circuit in which there are consecutively arranged two-input logic circuits, one input of two adjacent two-input logic circuits are connected, and this connection point is an input. By using, there is an effect that the number of wirings toward the coding area can be significantly reduced, and further higher integration of the combination logic circuit for the decoder can be achieved.

[Brief description of drawings]

1 is a circuit diagram of a combinational logic circuit according to the first embodiment of the present invention, FIG. 2 is a circuit diagram of a combinational logic circuit according to the second embodiment of the present invention, and FIG. 3 is a conventional combinational logic circuit. It is a circuit diagram. 1-16 ... 2-input NAND circuit, 21-29 ... Wiring, 41-48 ...
…wiring.

Claims (2)

[Claims] 1. A two-input logic circuit arranged in series, one input of adjacent two-input logic circuits are sequentially connected, and this connection point is sequentially connected to input lines from two coding areas. In any of the coding areas, the coding point, which is a connection point between the input line from the coding area and the address information line, is always at a different position on the input line from the adjacent coding area. Combinational logic circuit for decoder. 2. A combination logic circuit for a decoder according to claim 1, wherein an inverter circuit is used as said two-input logic circuit, one input is a gate, and the other input is a power source of the inverter circuit.