JPH077961B2 - Cell used for control network - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of networks of distributed intelligence and configuration and control, and primarily where those networks are used for detection, communication and control. It relates to an intelligent cell used for.

2. Conventional Technology There are many commercial products that perform detection, control and communication in a network environment. Their products range from very expensive and sophisticated systems to simple systems with few intelligent cells. It will be appreciated that the present invention seeks to obtain a system that has a relatively large amount of intelligence and processing power, but is inexpensive.

One commercially available device "X-10" controls between, for example, a light switch. When the light switch is activated, a code packet is sent through the power line to the receiver at the light. The code packet is sent twice.
The first is sent in its true form, the second in its complement. When the code is received by the receiver, it is interpreted and used to control the light. Mechanical analyzing means are employed to allow the transmitter in the switch to communicate with the specific receiver in the lamp.

The present invention provides significantly higher performance and flexibility than current devices.

Applicants will submit references for the X-10 and other known conventional devices.

SUMMARY OF THE INVENTION A network for detecting, communicating and controlling will be described. A plurality of intelligent cells, each including an integrated circuit having a processor and an input / output, are coupled to the network. When manufactured, each programmable cell receives a unique identification number (48 bits). Their identification number is permanently retained in the cell. The cells can be coupled to various media such as power lines, twisted pair, radio frequency, infrared ultrasound, electric coaxial, etc. to form a network.

The networks are distinguished from each other by the device identification number (ID _S ). Groups of cells within each network are formed to perform a particular function, and the groups are identified by the group ID _S. Communication is performed within the network using the device ID _S , the group ID _S, and the cell ID _S. For example, a task for detecting the state of the switch is assigned to a certain cell (announcer), and a control task such as controlling an electric light is assigned to another cell (listener). A cell can perform multiple tasks and can be a component of multiple groups and can act, for example, as a repeater for one group and as a listener in another group. Once manufactured, the cells are identical except for the cell ID.
They are programmed to perform tasks for a particular group or groups.

The preferred embodiment of this cell is a multiprocessor and multiple I /
Including O sub-part. Any processor can communicate with any I / O subsection. This allows the program to run continuously without the potential interruptions caused by the I / O interface. The I / O section includes a programmable AD converter, a programmable DA converter, and other circuits for other modes of operation.

This network protocol offers great flexibility,
For example, groups can be formed and / or modified at least once the cells are in place. It will be appreciated that the intelligence for this network is distributed among the cells. In general, networks are lightly loaded, but are prepared for any race and other conditions that may occur. In general, communication between cells is optimized for performing the functions assigned to the group, rather than for the transmission of data not related to the control functions of the network. For this reason, usually the packets carrying the message are Ethernet, Arbor, Apple Talk, X.
-25 and relatively short compared to other broadband and data communication equipment.

Other aspects of the invented network and cell will be apparent from the detailed description of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a typical application of the present invention.

FIG. 2 is a diagram showing cell grouping.

FIG. 3 is another block diagram similar to FIG. 2 used to show within a group of cells.

FIG. 4 is a line frequency used to explain the sub-channel.

FIG. 5 is a line frequency showing a plurality of cells. This line frequency is used to describe cell grouping using the present invention.

FIG. 6 is a chart showing the format of the packet used in the present invention.

FIG. 7 is a chart showing the packet style destination list portion of FIG.

FIG. 8 shows the sequence of steps used to form a group of cells in the present invention.

FIG. 9 is a chart showing the code assignment for the six-choice coding used in the present invention.

FIG. 10 is a block diagram of communication and control cells.

FIG. 11 is a block diagram of a portion of the instruction decode logic used within the processor of the cell of FIG.

FIG. 12 is a detailed block diagram of the process of FIG.

FIG. 13 is a timing diagram for the processor of FIG. This figure also shows the latches and registers used to perform the pipelining employed by the cell.

FIG. 14 is a block diagram showing the presently preferred embodiment of the six-choice encoder.

FIG. 15 is a block diagram showing the presently preferred embodiment of a six-choice decoder.

FIG. 16 is a block diagram showing the presently preferred embodiment of the six-choice code checker.

FIG. 17 is an electric circuit diagram of one buffer section of the I / O section.

FIG. 18 is an electric circuit diagram of the counting function and the timing function for the I / O sub section.

FIG. 19 is an electrical circuit diagram of the control and state machine for the I / O section.

FIG. 20 is an electrical schematic for the sample and hold means associated with the I / O subsection.

FIG. 21 shows the network formed in the I / O subsection for performing the digital-to-analog conversion.

FIG. 22 shows the network formed in the I / O subsection for performing analog-to-analog conversion.

FIG. 23 is an electric circuit diagram showing the communication part of the I / O sub-unit.

FIG. 24 is a state diagram used for communication competition with the I / O sub-unit.

FIG. 25 is a state diagram for link level ARQ.

FIG. 26 is a state diagram for connecting the primary station.

FIG. 27 is a state diagram for connecting a secondary station.

FIG. 28 is a block diagram for the grouping device.

FIG. 29 is a diagram showing how the system ID is encoded for sending in a packet and encoded in the cell.

FIG. 30 is a diagram used for explaining the operation of the input / output unit and the operation of the semaphore register.

DETAILED DESCRIPTION OF THE INVENTION An apparatus and method for communicating, detecting, and controlling in a network is described. If the network contains multiple intelligent cells, the cells are generally a programmable one-chip remote controller, a programmable one-chip remote detector, and a programmable one-chip telecommunications device, ( Has distribution detection, communication, control and network configuration intelligence, configuration and control when interconnected to other cells via various media.Devices are organized in a hierarchy based on communication needs. It has a network of cells, which are organized into behavioral "groups" independent of the network hierarchy. Groups of cells are commonly used to perform group functions. Is performed by assigning the
It performs control and detection. Generally, each cell has a unique identification number and performs information processing tasks such as bidirectional communication protocols, input / output, packet processing, analog and digital detection and control. In general, a device made up of cells has the property of storing network configuration information distributed throughout the device. Then, the automatically sent message is communicated between cells. Each device also has a unique identification (ID). The identification is 48 bits in the presently preferred embodiment. Moreover, it is a programmable input / output that can be used in many applications
It includes I / O circuitry and provides flexible digital programming to configure cells for specific detection, communication, control, I / O, analog I / O, communication I / O, and communication bit rate.

In order that the invention may be fully understood, the following description sets forth numerous details of particular matters, such as particular frequencies. However, it will be apparent to one skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits, methods, etc. have not been described in order to avoid unnecessarily elaborating the invention and obscuring it.

I Overview of Applications of the Invention Before describing the present invention in detail, an understanding of typical applications may be helpful in understanding the following detailed description. FIG. 1 shows a simple and typical application based on the use of the invention in the home. In FIG. 1,
Switch 22 is used in accordance with the present invention to control electric lamp 23.

Device 20 includes a cell 27, which is connected to switch 22. The cell is also connected to transceiver 29. Power for transceivers and cells is provided by power supply 30. The power supply receives power from lines 24 and 25. For this example, the line
24 and 25 are normal household distribution lines (for example, 110 VAC), and the power source 30 is a 5 volt DC power source. Cell 27 is preferably an integrated circuit. This will be explained in more detail starting from FIG. Transceiver 29 may be any one of many well known devices for receiving and transmitting digital data, where the transmitted data does not undergo any processing. The entire device 20 is
It can be small enough to fit in a normal wall-mounted electric box that normally houses the switch.

Device 21 can also be small enough to fit in a typical outlet and includes power supply 31 and transceiver 33. Power supply 31 and transceiver 33 are power supply 30 and transceiver 29
Each can have the same structure. This cell 28 is coupled to a transceiver 30, a power supply 29 and a solenoid operated power switch 32. Cell 28 can be the same as cell 27, except for programming and identification number. That will be explained later. Output from cell 28 is solenoid
Control 32 to operate the power switch. The power switch connects the light 23 to the power lines 34 and 35. As will be seen later, the cell 28 provides a digital or analog output that can control a rheostat (not shown) or the like to provide a lamp 23.
So that it can be dimmed.

The break 26 in the power lines 24 and 25 is used to indicate that it is not necessarily in the same circuit as the power line 34 or 35. The transceiver 29 does not necessarily communicate directly with the transceiver 33, the communication between the transceivers is between another cell and the devices 20 and 21.
It will be appreciated that it may require a link through a transceiver to relay a packet sent between.

In FIG. 1, transceivers 29 and 33 communicate via a power line. Transceivers can communicate with one another in a myriad of ways over innumerable media and at any baud rate. For example, the transceiver can each transmit and receive radio frequency or microwave signals via the antenna. The transceivers can be connected via communication lines, such as ordinary twisted wire or fiber optic cables, so that they communicate with each other independently of the power lines. Other known communication media can be employed between the transceivers, such as infrared communication or ultrasonic communication. A typical communication speed is 10K bits per second (KBPS) for power lines. Higher transmission rates are possible in the case of radio frequency, infrared media, stranded wire, fiber optic links and other media.

Cell 27 detects the opening or closing of switch 22 and then prepares the packet containing the message which initiates the state of switch 22. The packet is a transceiver 29 and a wire
It is sent to the cell 28 via 24 and 25. The cell 28 acknowledges the message by sending the packet back to the cell 27, and by turning on or off the electric lamp 23 by operating the solenoid control power switch 32, it responds to the message it receives. I also work.

Each cell has a unique 48-bit identification number (ID number).
The identification number is also called a cell address. In the presently preferred embodiment, each cell receives its permanent unique ID number as part of the manufacturing process. (It cannot be changed in subsequent manufacturing.) About 2 ⁴⁸ possible I
With the D-number, you can see that each cell has a unique ID number, no matter how big the network is for practical purposes or how many networks are connected to each other. Let's do it. Then the clustering device
Access the ID and assign the system ID to each cell. Also, the grouping device collects cells into groups and performs various functions related to the groups.

As shown in FIG. 1, the main function of cell 27 is to "announce", that is, to send the status of switch 22 on network communication lines 24 and 25 and 34 and 35. It is shown as "A" to indicate that. On the other hand, the main function of cell 28 in FIG. 1 is to "listen" to the network, and in particular to listen to the message from cell 27, so cell 28 is designated by the letter "L". In later figures, the "A" and "L" designations are used to refer to an announcer device such as device 20 and a listener device such as device 21, particularly in connection with grouping of multiple cells. For purposes of explanation, it is sometimes the case that the cell itself transmits or receives data without the transceiver's reference. (In some cases, a transceiver can be just a passive network or just wires. Those networks or wires couple the input / output terminals of a cell to a wire. The I / O portion of the cell is a stranded wire. It will be appreciated that it can provide an output signal that can drive, etc. Thus, the cells themselves can act as transceivers for some media.) As will be explained next, cells 27 and 28 are attributes of a multiprocessor. Is a processor having. Before or after installing the cells, they can be programmed to perform the required functions of the cells, such as announcers or listeners, and for grouping combinations.

II Network Organization and Definitions A. Definitions Cell: A cell is an intelligent programmable element or elements that perform at least one of remote control, remote sensing, and telecommunications, and other When interconnected to similar elements, they form a communications network or communication device in which intelligence is distributed, a control network or control device, and a detection network or detection device.

Announcer: The announcer is the originator of the swarm message.

Listeners: Listeners are those who receive swarm messages.

(In some cases, the announcer may ask the listener for status information.) Repeater: A repeater is a cell that reads packets from the medium and broadcasts those packets in addition to other functions.

Group: A group of cells that work together for a common function (eg, a switch that controls a set of lights) is called a "group."

In FIG. 2, the group 37 is an announcer 37a and a listener 3
It has 7b and 37c and a listener 40. Group 38 includes announcer 38a, listeners 38b, 38c, and listener 40.
FIG. 2 shows that one cell (cell 40) can be a listener in two groups. Announcer 37a
Is a light switch function, it is a cell 37
The light can be controlled via b, 37c, 40. Similarly, the switches associated with announcer 38a are cells 37c, 37.
The lights can be controlled via b, 40.

In FIG. 3, group 42 is an announcer 44, 45 and a listener.
Including 46 and 47. Group 43 shares cell 44 with Group 42, but
44 is a listener for group 43. Group 41 group cell 47
Although shared with 42, cell 47 is an announcer for group 41 and can announce to group 48 listeners 48, for example. Cell 47 also acts as a listener for group 42.
One cell can be an announcer for one group and a listener for another as shown (cells can be programmed to perform their functions, which will be discussed later). However, as intended here, a cell cannot be the announcer for more than one group.

(In the presently preferred embodiment, each cell has three pairs of input / output line pairs and select lines. Each pair shares a common set of resources. If the required shared resources do not conflict. Lines can be used independently for several functions.
In another function, the lines are used in pairs. In this example, a pair of leads from cell 27 are coupled to the switch of the lamp and another pair is used for communication from announcer, cell 27. ) Sub-Channel: FIG. 4 shows a first plurality of cells communicating over a common medium such as strand 50 (cell as "C", announcer as "A"). ,
Listeners are shown as "L"). This (eg, stranded wire 50) is a sub-channel, ie, a set of cells in which all cells communicate directly with each other over the same medium.
Broadcast by any member of the sub-channel, such as cell 49, is heard over strand 50 by all members of the sub-channel.

Channel: A channel has two or more sub-channels in which all cells communicate using the same medium. Fourth
The figure shows another plurality of channels coupled to the strand 52 to form another sub-channel. Suppose cells 56 and 57 communicate with each other over twisted wire 72. They form yet another subchannel. The cells associated with the strands 50, 52, 72 form a channel. The only communication between the sub-channels is cells 56 and 57 because the strands 50, 52, 72 are one continuous strand and one sub-channel 50 is so far from the second sub-channel 52. It is possible to make it through the part of the twisted line 72 that is drawn between. In this case cells 56 and 57 have any other function (eg announcer or listener)
In addition to being able to do so, those cells are assigned to be "repeaters".

Group 55 is shown in FIG. This group has announcers and listeners in two sub-channels. Another group 75 is shown. This group has an announcer on one sub-channel 51 and one sub-channel 52.

Since the sub-channels use different media, the sub-channels are not part of the same channel.

Gateway: A gateway reads packets from two types of media and rebroadcasts those packets. The cell can be the gateway. Communication between the channels is done via the gateway 54.

In FIG. 4, an additional subchannel containing cell 58 is coupled to another medium, such as a common power line. cell
58 is shown connected to the channel 54. The channel gateway communicates with strand 52. The gateway 54 does not necessarily perform an announcer function or a listener function, but rather, in the illustrated embodiment, performs a channel function by communicating between two types of media.

Sub-network: The sub-network contains all cells with the same system identification number (system ID). For example, all cells in a home can have the same system ID. Therefore, the channels of FIG. 4 can be part of the same sub-channel sharing the same system ID.

Whole network: A whole network can contain multiple sub-channels, each with a different system ID.
A communications processor is used to exchange packets between the sub-networks. The communications processor translates a packet that exchanges its system ID, addressing and other information. Each factory building can have its own system ID, but by exchanging system IDs, control between the two is used. (In this application, the term "network" is used in its more general sense, so it refers to anything other than "total network" as defined in this section.) Other terms used later are as follows: Is.

Probe packet: A packet sent by flooding. This packet accumulates route information as it travels through the network.

Grouping device: A device that controls the determination of paths between cells, assigns cells to groups, and assigns functions to members of groups.

Conflict: A condition that exists when two or more cells are trying to broadcast on the same subchannel at the same time and their signals interfere.

B. Group formation 1. Cells assigned to the group by the grouping device after installation.

It is assumed that the plurality of cells shown in FIG. 5 are all connected through a power line in the home for communication and are part of the same channel. Furthermore, one cell, announcer
Suppose 60, is grouped with a listener 65.
Lines between cells, such as line 59, are used to indicate which cells can communicate directly with each other. For example, announcer 60
And the cell 61 can communicate with each other. (Cells 61, 62, 63, 64,
66 can of course be another group of announcers or listeners, but is shown as "C" in Figure 5 for purposes of illustration. The announcer 60 and the cells 61, 62, 63 are all in communication with each other, so they are in the same sub-channel. Similarly, cells 62, 64, 65, 66 are in different sub-channels. (Fig. 5 has another vice-channel.) But, importantly, announcer 60 and listener 65
Announcer 60
There are innumerable routes from which a message can be sent to listener 65, for example routes or cells through cells 61 and 64
There is a route through 62 and 64.

Note that all cells are on the same power distribution unit in the house, but they may not communicate directly with each other. For example, the announcer 60 may be provided in one circuit that is only coupled to the listener 65 through long wires along the length of the house and the low impedance of the breaker panel. Even though the cells are in close physical proximity to one another, the high frequency communication message may be attenuated during its path to prevent direct communication between the cells.

In the following description, it is assumed that each cell can broadcast without disturbing the broadcast of other cells. That is, the messages do not interfere with each other. If there is any conflict, it will be dealt with in the protocol section of this application.

In one embodiment, the group of announcers 60 and listeners 65 are formed using the grouping device shown in FIG.
Before this group was formed, announcer 60 and listener 65
Note that is a regular cell and is not shown as an announcer or listener. Each clustering device can be assigned a unique 48-bit system ID (48-bit number is used in the presently preferred embodiment) at the time of manufacture. In the currently preferred embodiment,
Each grouping device includes a cell. The cell ID becomes the system ID. This ensures that each device has a unique system ID. For example, each home has its own "clustering" device and thus has its own system ID used within the home. This system ID is used in the cell packet for network. In this example, the grouping device can utilize the cell IDs of cells 60 and 65. (Various ways to get the cell ID are described later.) Three pairs of input / output (I / O) lines (or select pins) on a cell.
The grouping device is connected to the cell 60 by communicating via a pair of, and the grouping device reads the 48-bit ID number of the cell 60. (Various methods of determining the cell ID are described in the next section.) The clustering device then generates a random bit binary number. In the presently preferred embodiment, the binary number is 10 bits. This number also functions as a group identification number (also called a group address) of the group having the announcer 60 and the listener 65. For other group IDs already assigned to determine if the group ID has already been used,
The clustering device checks the number. (For example, one clustering device does not lose track of all cluster IDs assigned to one home.) The clustering device programs cell 60 to
The cell 60 is designated as an announcer.

The grouping device causes the announcer 60 to broadcast the group number in a special packet. The packet, if all cells in the network have been designated as being members of this group, causes those cells to acknowledge the message.

The clustering device now determines the ID number of cell 65. this is,
This can be done by connecting the grouping device directly to the cell 65 even before the cell is installed, or by other methods described in the next section. (You can assign ASCII names to cells and groups, such as "entrance lights" (cell names) and "outside lights" (group names).) This will give you the cell or group ID by accessing the ASCII name. Used to allow selection.

Now, the grouping device causes the announcer 60 to send the probe packet. The probe packet contains the ID of cell 65. The packet commands all cells that receive the packet to repeat it and commands cell 65 to acknowledge the packet. Each cell that receives the probe packet repeats itself and adds its own ID number to the repeated packet. Each cell only repeats the packet once (the mechanism that prevents the probe packet from being repeated more than once will be described later).

Cell 65 appears to be the most direct in the figure (via cell 62) and longer ones, eg cells
Take packets through a myriad of routes, including those via 61 and 64. It is assumed that the probe packet that reaches cell 65 first follows the most direct path and thus the preferred path. (This is assumed to pass through cell 62.) Cell 65 is a packet that indicates that the probe packet is sent by cell 60 and repeated by cell 62 and is intended for cell 6. 65 receives. Other packets received by cell 65 after this first packet are discarded by cell 65.

Cell 65 now sends an acknowledgment back to announcer 60. This packet contains the routing of the probe packet (eg, repeated by cell 62). The packet instructs cell 62 to repeat the packet to confirm that it has received it.

After the announcer 60 receives the acknowledgment packet for cell 65, it determines that cell 62 must be a repeater. The grouping device causes the announcer 60 to send a repeater assignment packet that includes the cell 62's unique ID number, the group number, and a message that informs the cell 62 that the cell 62 has been assigned the function of a repeater for that group. . This causes cell 62 to repeat all of its packets for the group containing announcer cells 60 and 65. Another message is sent from announcer 60 under the control of the clustering device, which is repeated by cell 62, designating cell 65 as the listener and letting that cell act on the message for that group. The grouping device assigns the component number stored in the cell of the component to the component.

The above group formation is shown in FIG. 8 as a step or block 68.
Indicated by ~ 72. Block 68 shows the broadcast of the probe packet (eg, cell 60 sends the first probe packet to all cells). The packet contains the address of the destination cell. As the packet progresses through the network, it accumulates the packets and their cell ID numbers and repeats the packet (block 69). Block 70 shows the acknowledgment to the probe packet from the destination address cell (eg cell 65). This packet returns the repeater ID number contained in the first received probe packet. A repeater assignment packet is sent by the announcer to cause each repeater to rebroadcast to the group packet. This is indicated by block 71. Finally, a destination cell, such as cell 65, is designated as the listener, as indicated by block 72.

2. A cell assigned to a group by a pre-installation grouping device.

There may be several types of pre-installation grouping devices. For example, see Figure 28 for a device that may be used. One type is a device used by manufacturers to pre-assign cells to groups. Another type of pre-installation grouping device is one that retailers or other cell vendors can use to assign cells to groups prior to installation.

The grouping device assigns cells to groups and assigns the cell's functions to the groups. The clustering device can also assign a system ID to the cell. System ID assigned by the pre-installation grouping device
Is not necessarily a unique system ID. (The post-installation grouper assigns a unique system ID to each system.) One method that can be used by the pre-installation grouper to generate the system ID is with a range of 48 bit addresses,
Selecting the system ID from the system ID number set aside for use as the pre-installation system ID. group
Similar to cell IDs in the range 1-1023, which are set aside for use as ID and group addresses, cell IDs in the range 1024-2047 can be set aside for use as pre-installation system IDs.

It is desirable that the clustering device and other network control devices identify the pre-installation system ID as opposed to the post-installation system ID. Do not assign a cell ID to the range set aside for the pre-installation system ID, because copying the cell ID will generate a system ID after installation.
Therefore, ID numbers within that range are not assigned to cells as cell IDs.

Sometimes the cell is sold as a set pre-assigned to the group by the manufacturer. The type of pre-installation grouping device used by the manufacturer assigns cells to groups by writing the appropriate code in the cell's non-volatile memory. The user can install such a set of cells and, if the set of cells can communicate via a sub-channel, the set of cells will operate without allocation by the post-installation grouping device. Will.

Users can assign cells to groups when they are purchased or at any time prior to installation. Unlike the case described previously, those cells are not assigned to a group by the manufacturer and are referred to as unassigned cells. All unassigned cells have the same system ID and a system ID number set aside for use only by the assigned cell.

The user may use a pre-installation grouping device that may be different from the pre-installation grouping device used by the manufacturer,
Assign a set of cells to a group.

Typically, those grouping devices operate on one cell at a time. The operator commands the clustering device to generate a new group ID and system ID, and then each cell is connected to the device. The operator commands the grouping device to assign cells to the group while the cell is connected to the grouping device. The clusterer will use the same group ID for the cell until instructed by the operator to generate a new group and system ID
And assign the system ID to the cell.

If a user can install such a set of cells and the set of cells can communicate via a sub-channel, it will work without the use of post-installation grouping devices.

3. Group unassigned cells and self-assign after installation.

Unassigned cells can form a group and can be assigned to the group by itself after installation as follows.

The first announcer, which is stimulated via the first announcer's sensor input (eg, a light switch), controls the group formation process. It randomly selects a system ID from the range of system ID numbers set aside for the pre-installation grouper. It randomly selects a group ID number. It then broadcasts a group ID number for the response from any cell that is a member of that group. If the sending cell receives any such response, it randomly selects another group ID. The process by which the cell selects a random group ID until it finds an unused group ID on the device on which it is operating, and tests to see if that group ID is already in use. Continue.

Factory-assigned default configuration information for unassigned cells identifies its function as a listener or announcer. If an unassigned cell is an announcer, it waits for its detection input to be resourced, and when it is stimulated, the cell sends the addressed packet to the group.

If the unallocated cell is a listener, that listener will listen to the packet after power up. The cell takes the group ID from the first packet it receives and assigns itself to that group. The cell then sends a response to the announcer cell. This response is not just a packet acknowledgment. It is the packet that identifies the cell as a listener in the group, and the packet must be acknowledged by the announcer. This ensures that all listener identification packets will reach the announcer, even if there are conflicts and conflicts in the process.

The cell that sent the group announcement composes a list of members of the group as each response arrives. It then sends a packet to each listener and assigns that listener a number of members of the group.

4. Unassigned cells that combine existing groups after installation.

Unassigned cells can be added to existing devices and assigned to groups in a manner similar to the above method described in Section 3 above. The listener connects the device and group in the same way as in Chapter 3 above.

In the above example, the announcer waits to be stimulated via its sensor input. The unassigned announcer waits for its first sensor input stimulus or its first received packet. Of those two events,
The first event that occurs determines the next action of the announcer cell.

If the cell were first stimulated, it controls the group formation process exactly as in the example above. If the announcer cell first receives a group packet, it joins the group as an announcer. Then it is
A packet is sent to the group announcer for configuration information about the group (size of the group, number of announcers, etc.) and assignment of numbers for the elements of the group.

C. How to identify cells for grouping In order for the grouping device to perform the steps necessary to form a group or to add a cell to a group, the ID of the cell to be added to the group must be known. . The grouping device then uses those cell IDs to address commands to the cells during the grouping process. The method used by the user with the grouping device to obtain the cell ID is tabulated below. The performance of the grouping device or other control device in communication with the cell in the example below can be limited by the safety procedure, if any.

Security procedures, communication restrictions, and security levels are not important to the present invention. The examples below assume no safety procedures are taken. In particular, it may not be possible to communicate with the cell in which the clustering device is installed, unless the clustering device has the device key (system ID and encryption key).

1. Direct connection to the cell.

The clustering device can connect to the I / O line of the cell package and then send a message to that cell requesting the cell's ID. ID of the cell before or after the cell is installed
You can use a physical connection to find out. To protect the security of the system, known means (eg fuses or programmed disable instructions) can be used to allow the user to disable this function in the installed cell.

2. Selection of cells by use of special pins In order to physically select cells by stimulating the cell input pin that is designated to perform the selection function, the user must select a grouping device or some other selection Equipment can be used. The grouping device communicates with the cell via the normal communication channel and sends a broadcast message requesting that all selected cells respond with their ID. Since only one cell is selected, only that cell responds to the request. Physical selection can be used to find the cell's ID before or after the cell is installed. Also, in order to protect the safety of the system, means are provided to allow the user to disable this function.

3. Query All Names of Previously Grouped Cells In this example, assume that ASCII "group" and "cell" names have already been assigned to cells. According to this method, the group name and cell name (ASCII
The grouping device queries those cells to inform their name. The user scrolls through the list of group names by using the grouping device. The user selects a group name believed to contain the target cell. The grouping device displays the names of all cells in the group and the tasks (announcer, listener, repeater) assigned to those cells. The user selects the name of the cell believed to be the target cell.

If the selected cell is an announcer, the grouping device counts to the user activating that announcer by stimulating that announcer's input. For example, if the cell is attached to a light switch, the user will flash the light. The cell sends the announcement packet to the swarm. The grouping device listens to the communication channel to find the group number and component number, or other code of the activated announcer.

If the selected cell is a listener cell, the clustering device (using the group number and the component number for addressing) sends a packet that instructs the cell to toggle the output of that cell. Send to. For example, if the cell controls a light, the light will blink. This allows the user to confirm that the user has selected the correct cell.

The clustering device sends a packet to the target cell that instructs the target cell to return its cell ID. The grouping device then knows the target ID and can continue the group assignment process.

The question name is used before finding the cell ID before or after the cell is installed.

4. Group Stimulation This method is used in networks where the ASCII names of groups and cells are assigned. The user commands the grouping device to wait for the next group announcement. The user then stimulates the announcer in the targeted group. For example, if the announcer is a light switch, the user throws the switch. The grouping device listens to the announcement packet and then retrieves the group ID.

The user can confirm that the group ID is for the desired group by having those listeners send packets to the grouping device that instruct them to toggle the output of all group listeners. The user confirms that it is the desired group by observing the movement of the listener cell (eg, if the group is composed of lighting controls, the lights are on).

Now, with the group ID, the grouping device broadcasts a packet requesting that each cell respond with its cell name until it finds the cell of interest. The user selects the name and the grouping device knows the ID of the cell and can continue the group assignment process.

If the user chooses, the cell ID can be verified before proceeding with the grouping procedure. The following procedure is used to verify that the ID is for the target cell.

Given that the selected cell is the announcer, the clustering device teaches the user to activate the announcer by stimulating the announcer's input. For example, if the cell is attached to a light switch, the user blinks the switch. The grouping device can then find the group address and cell component number.

If the selected cell is a listener, the grouping device sends a packet to the cell (using the group number and component number for addressing) that instructs the cell to toggle the cell's output. For example, if the cell controls a light, the light will blink. This allows the user to confirm that the user has selected the correct cell.

5. Stimulate announcer This method is used in networks where the ASCII name of a group or cell is not assigned, but announcers and listeners are assigned. The clustering device then sends a packet to all cells in the network, instructing each announcer to broadcast the packet containing the announcer's ID when the announcer is stimulated. The clustering device then teaches the user to stimulate the announcer by activating its detected device, eg, turning on the light switch for the light switch announcer. The user stimulates only one announcer, so the clustering device receives only one packet with the cell ID.

There is an opportunity for different announcer cells to be stimulated at the same time. Perhaps someone else turns on the light switch, or a temperature sensor detects a temperature change. The user may wish to confirm that the received ID is for the correct cell. In order to confirm that the cell ID is correct, the user gives a second announcer stimulus,
Make sure the same results occur.

6. Toggle listener This method is used in networks where no group or cell name is assigned. The clustering device broadcasts a packet that queries the cell, which is the listener responding with its own ID. Since the grouping device needs to limit the number of responding cells, the packet contains an ID bit mask to limit the response to a subset of possible cell IDs. When the clustering device generates a list of listener IDs, it allows the user to toggle each listener, causing the listener cell to turn its output on and off. The user continues through the list of listener cells until the user observes that the target cell is toggling its output. The user then identifies the cell to the grouping device, which can continue the grouping operation.

D. Packets The packet delivered by the automated cell contains a large number of fields. For example, the format used for group presentation is shown in FIG. Other packet formats are described in Appendix A. Each packet starts with a preamble used to synchronize the input circuit of the receiving cell (bit synchronization). The preamble code used in this preferred embodiment is described as part of the six-choice triplet combination code (FIG. 9). A 6-bit flag field starts and ends each packet. The Fratfield code is also shown in FIG.

Preferably, each cell reads the entire packet, computes the cyclic redundancy code (CRC) for the packet, excluding the contention timer field, and compares it to the CRC field of the packet that received the result. . ALU in Figure 12
102 is hardware for calculating the packet CRC,
A CRC register 130 for storing the intermediate result.
If the packet CRC cannot be verified for an incoming packet, the packet will be discarded. The packet CRC is 16 bits as calculated, and is then converted to a 24 bit field using the encoding of FIG. 9 for transmission with a six-choice code. (In this section, for the rest of the description of the packet field, the field length is described before encoding with the six-choice combination code of FIG. 9.) In this preferred embodiment, the CRC is used. Is the CCITT standard algorithm (X ¹⁶ + X ¹² + X ⁵ +1).

The system ID is now preferably 32 bit fields. The other 16 bits of the 48-bit system ID are included in the CRC calculation but are not sent as a partial f packet (Fig. 29).

The link address field is 48 bit fields. If this field is all zeros, the packet is interpreted as a system-wide broadcast acted on by all cells. For example, the probe packet has an all-zero field for the link address. The group address is included in the link address. In the group address, the first 38 bits are zero and the remaining 10 bits contain the group address. (Described above, cell ID numbers assigned at the factory ranging from 1024 2 ^48. The reason is that the address of 2 ¹⁰ is because is reserved for groups.) If there is link address It is the address of an individual cell. (For example, when a cell has a repeater or listener task assigned to it.) The contention timer has a 10-bit field, and the CRC field (or other checksum) used to verify the 10-bit timer field. Has an additional 6 bits for Each cell that repeats the packet acts on this field, given that the cell has to wait to send the packet. Given that the packet is being sent by another cell, one cell must wait to send its packet. The time it waits is indicated by counting down the contention timer field. The rate at which this field is counted down can be programmed in the cell, which rate is a function of the type of network. The field starts with a constant that can be selected according to the type of network. Each cell that is repeating a packet counts down from the number in the field when it receives the packet. Therefore,
If a packet is repeated 4 times and each of the 4 included cells is waiting for transmission, the number in the contention field is a constant sum of the number of waiting times (eg all zeros). Reflect what is subtracted from. When the contention timer fields reach all zeros, the cell waiting to transmit a packet discards it rather than sending it. This prevents older packets from reaching,
Interpreted as a new packet.

As mentioned, the contention timer has its own 6-bit CRC field. Given that the packet CRC contains a contention timer field, the packet CRC cannot be calculated until the packet can actually be sent.
This requires a lot of computation in the final microseconds before transmission. To avoid this problem, separate CRC fields are used for contention timer fields. If the contention timer field cannot be checked by its 6-bit CRC, then the packet is discarded.

The hop count field records the number of hops or retransmissions a packet takes before it reaches its destination. The 4-bit field is the maximum number of retransmissions allowed for a particular packet, starting with a number that is reduced by each cell that repeats the packet. For example, in a packet initiated by a group announcer, the starting "hop" count is the maximum number of retransmissions the packet must make to reach all the cells in the group. Therefore, 16 hops or retransmissions is the limit of what is currently realized.

The link control field supplies the link protocol, 8
Composed of bits. This field is described in subsequent sections covering other layers of the protocol.

The random number field / pseudo-random number field contains an 8-bit random number generated for each packet by the cell that first sends the packet. The number is not regenerated when the packet is repeated. The number is used as described in connection with FIG. 8 to limit rebroadcast of the probe packet. It can also be used in connection with encryption, which encrypts the entire packet.

The network control field (4 bits) indicates the type of routing or the type of packet, eg, network control, group message, probe message, etc.

The source address field (variable size) is, for example,
Contains the 48-bit ID number of the cell that generated the packet. In the case of a probe packet, this field contains the announcer's ID number. For acknowledgments, the field contains the listener's ID. For packets addressed to the group, this field contains the group number of the source cell group.

The destination list will be described with reference to FIG.

The message field is of variable length and contains the particular message sent by the packet. A typical message is included in Appendix B. In the case of a probe packet, the field contains the routing. That is, each repeating cell contains its ID number for this field. Once the flock is formed, the message is used by announcer 60 to tell listeners 65, for example, to turn on a light.

The crypto field, when used, contains 16 bits which are used to verify the authenticity of the encrypted packet. This part of the packet is typically unchanged when the packet is repeated. Well-known encryption techniques can be used.

The bracket 99 in FIG. 6 represents the portion of the packet that remains unchanged when the packet is repeated.
The fields are used to control the repeat, as described with reference to FIG.

The destination list field of the packet of FIG. 6 is shown in FIG. The destination field begins with a 4-bit field that indicates the number of components in the group that were instructed to receive the message in the packet. Therefore, the packet can be directed to up to 16 members of the group. Then the number of each component in the group is sent to the next 8-bit field. The group number contained in the link address and the component number contained in the destination list are used to carry the message once the group is formed. Assuming a destination number of zero, the packet will be addressed to all members of the group. For some packet types, this field is
Contains the ID (see Appendix A).

E. Mechanism for Preventing Rebroadcast of Certain Packets As described above, the probe packet is repeated only once by each cell after the packet is broadcast. A special mechanism programmed into each cell allows the cell to recognize recently repeated packets.

First, when each cell sends a packet, or sends it again,
Remember to calculate the packet CRC field that precedes the ending flag. In the case of a repeated packet, a new CRC is needed because at least the hop count changes and a new packet CRC field is needed for that packet. This CRC field is different from the CRC field described in the next section.

When each packet requesting repeat is received, the sixth
The repeater CRC number is calculated for the field extending from the beginning of the link control to the end of the destination list, as indicated by the bracket 99 in the figure. As the cell broadcasts the packet, it stores the 16-bit CRC result in a circular list of such components if the same number is not already stored. But the field 99
The packet is repeated only if the circular list does not contain the repeater CRC result calculated for.

Therefore, the CRC is calculated for field 99 as each packet is received for repeat. This is indicated by block 73a in FIG. This number is compared to a list of eight numbers stored in the RAM contained within the cell as indicated by block 73b. If the number is not found in the stored numbers, the new repeater CRC result is stored, as indicated by block 73c, and the bucket is repeated. On the other hand, if the number is found, the packet will not repeat. As realized here,
Eight numbers are stored in the circular list. That is, the oldest number is discarded as a new number is calculated.

With the use of repeater CRC calculations related to field 99,
The use of a circular list prevents the repeat of previously rebroadcast packets. For example, even if the announcer constantly rebroadcasts the same message train, as happens with a continuous blinking light, the cell designated as the repeater rebroadcasts the same message. The reason is that the packets containing the message appear different. This is true. This is because the random numbers sent in each same message are probably different. However, if you receive the same message (same random number) contained in the same field 99, the packet and its message will not be rebroadcast. This is especially true for probe packets. Therefore,
For the above group settings, the broadcast probe packet will rapidly "die" in the network. In other cases, they will reverberate for a period of time, causing unnecessary traffic during network work.

F. Six-choice combination coding In many networks that use synchronous transmission of digital data, coding is used to embed timing information in the data stream. One widely used encoding method is Mantiester encoding. Muncher or other encoding is used to encode the packet, but the encoding described above is now preferred.

In the preferred embodiment, six-choice combinatorial coding is used to transmit the data. All data is grouped into 4 bit nibbles and 6 bits are sent for each such nibble. The 6 bits have 3 1's and 3 0's. By transmitting 3 1's and 3 0's in some combination out of every 6 bits, the input circuit of the cell can be quickly synchronized (bit synchronized) and byte synchronized. To be This will be described later in relation to the I / O section. Also, once synchronized (from the open select mode), transitions in the incoming bitstream are used to maintain synchronization.

The right hand column of FIG. 9 shows 20 possible combinations of 6 bit patterns, three of which are ones and three of which are zeros. The left column shows the corresponding 4-bit pattern assigned to the alternative pattern. For example, if the cell sends nibble 0111,
It is converted to bit segment 010011 before it is sent. Similarly, 0000 is converted to 011010 before being sent.
When a cell receives a 6-bit pattern, it converts them back into the corresponding 4-bit pattern.

There are 20 six-choice patterns and only 16 possible 4-bit combinations. Therefore, the four six-choice patterns do not have corresponding 4-bit pattern assignments. The six-choice pattern 010101 is used as a preamble for all packets. Since the preamble and flag patterns repeat the transition at the basic data rate, they are particularly good for use by the input circuitry to provide data synchronization. Two unassigned three-choice patterns can be used for special conditions and special commands.

Therefore, the cell generally prepares a packet in integer bytes and each nibble is assigned a 6-bit pattern before transmission. Then the preamble and flag are added. Four
To convert from bit patterns to 6 bit patterns,
And vice versa, a circuit for converting a 6-bit pattern to a 4-bit pattern is shown in FIGS.

III Communication and control cells A. Cell overview Referring to Figure 10, each cell is a multiprocessor 100,
It includes input / output units 107-110, a memory 115, and a timing generator 111. Also shown is the voltage pump 116 used in the memory 115. This cell is realized by a usual integrated circuit. For example, multi-processor 100 can be manufactured using gate array technology, as described in US Pat. No. 4,642,487. The preferred embodiment of the cell is CMOS
Including use of technology. The entire cell of FIG. 10 is manufactured as an integrated circuit on a single silicon substrate. (Multiprocessor 100 is sometimes referred to as a singular item, but as will be explained later, it is a large number of processors, especially 4 processors.) Multiprocessor 100 is a stack-oriented processor. Arithmetic Logic Unit (ALU) with a set of registers 101
Supply input to 102. ALU 102 has two separate ALUs in this preferred embodiment.

Memory 115 is a total of 64 KB in this preferred embodiment.
Supply storage device. Of course, this particular size is not important. One portion of memory is used to store instructions (ROM code 115a). The next part of the memory is a random access memory 115b, which is unique to a number of normal static memory cells (which can use dynamic cells). The third portion of the memory is an electrically erasable and electrically programmable read only memory (EEPR).
OM) 115c. In this preferred embodiment, EEPR
The OM115c adopts a storage device having a floating gate. These devices require higher voltages (above normal operating voltage) for programming and erasing. A higher voltage is provided by an "on-chip" voltage pump 116.
The entire address space of memory 115 is addressed via ALU 102a, which is a part of ALU 102.

ROM 115a stores the routines used to implement the various layers of the protocol discussed in this application.
This ROM also stores the routines needed to program EPROM 115c. The application program for the cell is stored in ROM 115a. The routine is generally one that acts as a "state machine" driven by variables in EEPROM 115c and RAM 115b. RAM115
b stores communication variables, messages, application variables, and "state machine" descriptors. The cell ID, system ID, communication parameters, and application parameters (eg, group signal, component number, announcer / listener / repeater assignment) are stored in EEPROM 115c. The portion of the EEPROM 115c that stores the cell ID is "write protected", that is, once programmed with the cell ID, it cannot be reprogrammed.

The input / output part of the cell has four sub parts 107, 108, 109, 110. Three of these sub-portions 107,108,109 are leads 103,104,10 for communicating with the network and with at least one of the control and detection devices connected to the cell.
Have 5 each. The remaining sub-portion 110 has one selection pin 10
Having 6. This select pin can be used to read commands such as those used to determine the cell's ID. As currently implemented, sub-portion 110 is primarily used for timing and counting. The inputs / outputs are addressed by the processor through a dedicated address space, and thus actually appear to the processor as a memory space. Each I / O subsection can be coupled to each subprocessor. This feature, along with the multiprocessor architecture of processor 100, allows the processor to operate continuously (uninterrupted). The I / O part can be manufactured from a known circuit.
The presently preferred embodiment is shown in FIGS.

The cell of FIG. 10 also includes an oscillator 112 and a timing generator 111. The latter provides the timing signals specifically needed to perform the pipelining shown in FIG. First
Operation at 16 mHz for Phases 1-4 in FIG. 13 is presently preferred, thus providing a low instruction cycle rate of 4 mHz. Other known lines (eg, power) associated with the cell of Figure 10 are not shown.

All cell elements associated with FIG. 10 are, in the preferred embodiment, incorporated on a single semiconductor chip as described.

B. Processor A presently preferred embodiment of processor 100 is shown in FIG. 12 and includes a plurality of registers in communication with two ALUs 102a and 102b. (Those with "register" based devices, and other ALUs and other processor architectures such as memory devices can be used.) Address ALU 102a
Supplies an address to the memory 115 to access the I / O subsection. The data ALU 102b supplies the data to the memory and the I / O unit. The memory output terminal is coupled to the processor register via register 146 and DBUS 223.

The 16-bit ABUS 220 supplies one input to the address ALU 102a. A base pointer register 118, an effective address register 119 and an instruction pointer register 120 are coupled to this bus. (In the lower right corner of the symbols used to refer to those registers, there is an arrow labeled "X4". This is, for example, a base pointer register depth of 4. More specifically, The base pointer register has four 16-bit registers, one 16-bit register for each processor.
The same is true for the effective address register and the instruction pointer register. ) BBUS221 accepts inputs up to 12 bits for ALU10
Input to register 2a or input up to 8 bits.
To the data ALU 102b via. Stack top register 122 with depth 4 and stack pointer register 1
23, the return pointer register 124, and the instruction register 125 are coupled to BBUS.

CBUS222 inputs the other 8-bit input to ALU1 via register 143.
Supply to 02. The CBUS is coupled to an instruction pointer register 120, a stack top register 122 with a depth of 4, four carry flags 129, a CRC register 130 with a depth of 4 and a next register 131 with a depth of 4. To be done.

The MBUS coupled to the output terminal of the memory can receive data from the output terminal of the ALU 102b via the register 145b or from the memory or the I / O unit (107-110). This bus provides input via registers 146 and DBUS 223 to registers 118, 119, 120, 122, 123, 124, 125, 130, 131 and carry flag 129.

There is a 16-bit path from the output terminal of the address ALU 102a to the register 120. The ALU 102b includes a circuit that performs CRC calculation.
This circuit is directly connected to the CRC register 130 via the bidirectional line 133. The stack top register 130 is connected via line 138 to the next register 131. The lines can move the contents of register 122 to register 131, or the contents of register 131 to register 122. No bidirectional (simultaneous) exchange of data between these registers is realized as is currently realized. Four bits of data from the output terminal of the memory are sent directly to the instruction pointer register 120 or to the instruction register 12 via line 139.
Can be directly returned to 5.

Data and address pipelining (registers 141, 142, 143, 145, 146) between registers, ALUs, memories and their respective buses will be described with reference to FIG.

The data in any one of the stack pointer registers 123 or the data in any one of the return pointer registers 124 can be incremented or decremented directly via circuit 127.

The ALUs 102a and 102b can feed their inputs to their output terminals, multiply, and add their inputs. In addition to addition, the ALU102b also subtracts, shifts, sets the carry flag 124 (if appropriate),
Performs an AND operation, an OR operation, an exclusive OR operation, and one's complement arithmetic. The ALU102b has the following contents of register 131 and CRC.
The contents of the registers can also be combined in one step (via paths 222 and 133) and the stack top register 12
Combine it with the contents of one of the two to provide the next number used in the CRC calculation. The ALU 102b also provides a special nibble feature that allows standard shifts to shift low 4 bits to high 4 bits and high 4 bits to low 4 bits. Also, ALU102b
Performs the six-choice encoding or decoding described in Section F.

In the preferred embodiment where there is one semiconductor chip per cell, the basic contact pads on the die for power and ground, all I / O pins A, B, and "read only". There is a pin 106 (subparts 107, 108, 109, 110, 12th
Figure). The contact pads are used to attach to the package pins for the basic cheap package.

In addition to the basic contact pads, in this preferred embodiment additional pads are provided to connect to the ADBUS 224 and MBUS 225 of FIG. One control contact pad is provided to disable the internal memory. Activating the control contacts disables the internal memory and the data on ADBUS and MBUS is used by the processor. This allows the memory outside the cell to be used. Additional contact pads may not be available when the cell is packaged in a cheap package. These additional contacts are wafer probe contacts,
Or it can be accessed from pins in a package that has more than the minimum number of pins.

The manufactured cell requires an initialization program. At the wafer probe time, external memory is used for several purposes. To test one or a cell. Another application is to provide a program that writes cell I / Os to EEPROM during the manufacturing process. EEPROM required to allow power-up boot when the cell is later used
Instructions can be added at this time. Initialization programs and test programs are well known in the art.

C. Processor Operation In general, memory fetch occurs when the ALU 102a supplies a memory address. Memory address is in register 118
, The effective address register 119 or the instruction pointer register 120, which is typically the base address on the ABUS, such as the stack pointer register 123, the return pointer register 124, It is associated with the offset on the BBUS from the stack top register 122, or the instruction register 125.

The calculation in the ALU102b is based on the stack top register 122
(BBUS) and one of the following registers 131 (CBUS), or most typically, contains data that may be part of an instruction from one of the instruction registers 125.

In the preferred embodiment, the DBU is registered via register 146.
The processor operates on the output of the memory coupled to S, but it is also possible to implement a data processor directly coupled to the ALU 102b. Also, the effective address register 119
Functions performed by some other registers, such as, can be performed by other registers. However, the use of an effective address register, and for example a CRC register, improves the operation of the processor.

Generally, for memory addressing, the base pointer is provided by one of the registers 118, 119 or 120 and the offset is provided by one of the registers 122, 123, 124 or 125. Address ALU 120a supplies those addresses. Also, in general, the ALU 120b operates on the contents of the stack top register and the next register. There are exceptions, for example the instruction register AL
Can be supplied to U120b. Specific addressing and other instructions are described below.

D. Operation of multiprocessor A processor is effectively a multiprocessor (four processors). The reason is that it uses a large number of registers and pipelining. About them thirteenth
It will be described with reference to the drawings. As explained, one advantage of the operation of this multiprocessor is that it does not require interrupts, especially for handling input and output signals. Multiprocessor operation is performed without using a separate ALU for each processor. In this preferred embodiment, two ALUs, (102a and 102a
Economical design is achieved by using b), but only one ALU operates at any given time. (Note that the BBUS supplies the inputs to both ALUs.) Thus, the multiprocessor operation of the present invention can be performed using one ALU.

This processor has four processors that share an address ALU, a data ALU, and a memory. The basic small cycle takes four clock cycles for each processor. 1 small cycle for each processor
It is offset by a clock cycle, allowing each processor to access the memory and ALU once for each basic minor cycle. Since each processor sets its own register, it can run independently at its normal rate. Therefore, this device pipelines four processors in parallel.

One of four register groups is associated with each register in FIG. Each group facilitates the operation of a multiprocessor to which the processors (1-4) of Figure 13 are associated. Four
Each group has one base pointer register, effective address register, instruction pointer register, stack top register, stack pointer register, return pointer register, instruction register, CRC register, and next register. , Carry flag and. Each associated register group corresponds to one of four processors.
Each processor executes instructions in a short cycle. Each small cycle consists of 4 clock cycles. During the first clock cycle, the processor gates the appropriate registers on ABUS, BBUS and CBUS. In the next clock cycle, the ALU operates and generates data from the ALU, ABUS, BBUS, and CBUS ALU inputs. During the third clock cycle, the memory or I / O is active and the address sends from the ALU 102a and the data comes from the memory or ALU 102b.
The fourth clock cycle and the last cycle gate the result provided from memory or ALU 102b via DBUS to the appropriate register.

The processor can be viewed as a wave of data transmitted through the above sequence. At each step, the intermediate result is clocked into a set of pipeline registers. By using those pipeline registers, it is possible to separate individual steps in the sequence,
Therefore, it is possible to have four steps that execute simultaneously. Although the four processors share the ALU, memory, I / O, and many control circuits, they can operate without interfering with each other.

The control of the processor, including the pipelining, is best understood from Figure 11. Each processor has a 3-bit counter and instruction register. These are the counters 137a shown in FIG.
Shown as ~ 137d. One of the instruction registers 125a to 125d is associated with each counter. Each instruction register is loaded via DBUS. Once loaded into the instruction register, the instruction is bound to PLA 212. This PLA
Determines from the instruction the number of subcycles required to execute the instruction, and then the counter 113a or 113b or 113c associated with the loaded instruction register 125a, or 125b, or 125c or 125d. Alternatively, 113d is loaded with a 3-bit binary number. For example, loaded into instruction register 125c. In the case of the CALL instruction, the binary number 010 (indicating three small cycles) is loaded into the counter 137c. (Eight small cycles can be used for a given instruction, but in the preferred embodiment, only six small cycles are used for any instruction.) To fetch a new instruction The count value "000" is used.

The count in the counter (eg, 3 bits) and the instruction in the instruction register associated with it (eg, 3 bits)
12-bit) is from the 15-bit input to PLA136.
The 15-bit inputs from each of the four sets of count registers and four sets of instruction registers are sequentially coupled to PLA136. This will be described later. The PLA output controls the operation of the processor. More specifically, line 213 is ABUS, BBU
Controls data flow on S, CBUS, line 214 is ALU102
Line 215 controls the memory (and I / O operations of sub-portions 107, 108, 109, 220 as described below) and line
216 controls the flow of data on the DBUS. The particular output provided by PLA 136 for a given instruction is best understood from the instruction set. The operations performed by the processor to execute each instruction are described by the instruction set.

The output provided by PLA on line 213 is directly connected to the device that controls the flow of data on ABUS, BBUS, CBUS. The signals that combine the ALUs are combined through a 1-clock phase delay register 217 before being combined through line 214. Since all registers are clocked at the same rate, register 217 provides a delay function as described below. The signal from PLA 136 used for memory control is coupled through the two stages of delay register 217 before it is coupled to the memory, so that the signal on line 215 is better than the signal on line 213. Two
It is delayed by the clock phase. The control signal for DBUS is delayed by three clock phases from the signal on line 213 as it exits PLA 136 and is coupled to line 216 through three sets of delay registers 217. Since register 217 is clocked at a rate of 6 mHz, PLA 136 provides output control signals for a given instruction (eg, the contents of instruction register 125a). The control signals are coupled to line 213 during the first clock phase, coupled to line 214 during the second clock phase, and coupled to line 215 during the third clock phase,
Coupled to line 216 during the fourth clock phase. During the first clock phase of each instruction cycle, the contents of counter 137a and instruction register 125a are coupled to PLA 136. Second
During the clock cycle of, the contents of counter 137b and the contents of instruction register 125b are combined into PLA 136, and so on for the third and fourth clock phases.

Now the instructions are loaded into instruction registers 125a-125d,
Assume that counters 137a-137d are loaded with the corresponding binary counts for the small cycles required to execute each instruction. For example, assume register 125a is loaded with a CALL instruction and 010 is loaded into counter 137a.

On the first instruction minor cycle, 010, a 12-bit instruction to CALL is coupled to PLA 136. PLA1 from this 15-bit input
36 supplies to its output all the control signals needed to complete the first small cycle (eg, 4 clock phases) of the CALL instruction for ABUS, BBUS, CBUS, ALU, memory and DBUS. . Since this device uses pipelining muxing, the control signal on line 213 is used to execute the first clock phase of the CALL instruction which is the input to the ALU. (During this first clock phase, for the various instructions in the pipeline, the other control lines are ALU
And the memory and the DBUS of other processors. )
During Phase 2, the count in the counter for 137b and
The instructions in register 125b are coupled to PLA 136. During phase 2, the signal on line 213 is the ALU for the second processor.
It now controls the ABUS, BBUS, and CBUS inputs to and executes the instructions contained in register 125b. During this second clock phase, the signal on line 214 controls the first processor and the ALU and is contained in register 125a.
Performs the functions required to implement the second clock phase of the ALL instruction. (A delay equal to one phase is
It should be noted that it was added by. ) Similarly,
During the third phase, the signal on line 213 controls ABUS, BBUS, CBUS to the third processor to execute the instructions contained in register 125c. The signal on line 214 controls the ALU to execute the instructions contained in register 125b,
The above signal is memory controlled to execute the instruction in register 125a for the first processor. And finally, during the fourth clock cycle, the instruction from register 125d is coupled to PLA 136 along with the count in counter 137d. The signal on line 213 controls ABUS, BBUS, CBUS to execute the instruction contained in register 125d for the fourth processor, and the signal on line 214 controls the ALU, Execute the instruction in register 125c for the processor, line 21
The signal on 5 controls the memory to execute the instruction in register 125b for the second processor, and the signal on line 216 is D
Control BUS to register 125 for the first processor
Execute the instructions in a.

After 4 cycles of 16mHz clock, the count in register 137a is decremented to 001. Each clock cycle is PLA13
Each register is decremented on the clock cycle following the use of the contents of the counter contained by 6. Therefore, the input to PLA 136 changes even if the instruction in register 125a is the same. This allows the new signal required for the second small cycle of the CALL instruction to be provided. As mentioned above, those control signals are
It is rippled by the control via 3, 214, 215 and 216. When the count in count reaches 000, this is interpreted as an instruction fetch to the associated processor.

Therefore, each of the four processors can simultaneously execute instructions with a different number of cycles. The control signals that reach the virtual line for any given clock cycle represent four types of control signals and four types of processor control signals. For example, the control signal associated with the first processor appears on line 213 during the first cycle, on line 214 during the second cycle, on line 215 during the third cycle, and on the fourth cycle. The inside appears on line 216. The control signals required by the second processor follow. The control signals required by the third and fourth processors follow those used by the second processor.

The signal pipelining is shown in FIG. 10th
The multiprocessor operation of the illustrated processor 100 is shown in FIG. 13 as four processors, namely processors 1, 2, 3, and 4. One processor is associated with each one of the registers. The four phases of one instruction cycle are shown at the top of FIG. In Figure 13, the contents from the specific register called by the instruction
Register to indicate that it is placed on ABUS, BBUS, CBUS
101 is used. These registers are 118 and 119 on ABUS and 122, 123, 124, 125 on BBUS.
And 120, 122, 129, 130, 131 in CBUS.

During the first phase, the signals previously stored in the Group 1 registers (eg, two of them) are gated from those registers to ABUS, BBUS, CBUS. While this is happening, the signals associated with the Group 2 registers are
Gates 1, 142, 143 to ALUs 102a and 102b. This is shown in FIG. 13 as processor 2 under the first phase column. Simultaneous signals are gated from registers 145a and 145b into the memory for group 3 for processor 3. And finally, during this first phase, the signals associated with the Group 4 registers are gated from register 146 to DBUS. During the second phase, the signals associated with the Group 1 registers are coupled from the ALU to registers 145. The signals associated with the Group 1 registers are coupled from the ALU to registers 145. The data associated with the Group 2 registers is coupled to memory. The data associated with the Group 3 registers is coupled from register 146 to DBUS. Those related to Group 1 registers are ABUS and BBUS
And gated to CBUS. And, similarly, during the third and fourth phases of each instruction cycle, this pipelining is continued as shown in FIG. 13 to effectively provide four processors.

E. Processor Instructions This section describes each processor instruction along with specific register operations and specific memory operations. Lowercase letters are used below to indicate register contents. For example, the contents of the instruction register are shown as "ip". The registers and their flags are described along with their correlation to Figure 12 and their flags.

Although the top element of the return stack is physically located in RAM, it is also addressable as a register.

For each instruction, the operation, encoding, and timing are described below in standard C language notation.

CALL call procedure operation: ^* rp ++ == lowbyte (ip); ^* rp ++ = hibyte (ip); ip = dest; Encoding: intra-segment: laaa aaaa aaaa dest = ip + a + 1; / ^* displacement a is alway
s negative ^* / inter-segment: 0000 LLLL LLLL 0000 HHHH HHHH dest = H: L; ^* 16bit absolute address ^* / library: 0000 aaaa aaaa dest = 0x8000 + ^* (0x8001 + a); / ^* table lookup c
all ^* / BR Always branch operation: ip = dest; Encoding: 0010 1aaa aaaa dest = ip + a + 1; / ^* displacement a is sign ex
tended ^* / BRC carrier branch operation: if (CF) ip = dest; else ip ++; Encoding: 0010 01aa aaaa dest = ip + a1; / ^* a is sign extended ^* / BRZ TOS == 0 branch operation: if (tos == 0, tos = next, next = ^* (++ sp)) ip = des
t; else ＋＋ ip; Encoding: 0010 00aaa aaaa dest ＝ ip ＋ a ＋ 1; / ^* displacement a is sign ex
tended ^* / Move LDR register to TOS (including some indirect, indexed memory reference) Operation: ^* (sp −−) = next; if (reg) {next = tos; tos = reg} else {next = bp + TOS or next = (bp + 2p) + TOS} encoding 0101 0100 rrrr reg = r / ^* see table ^* / Store STR TOS in register (includes some indirect, indexed memory reference) Operation: if (reg) {reg = tos; tos = next;} else {bp + TOS = next or (bp + 2p) + TOS = next} next = ^* (++ sp); Encoding: 0101 0101 rrrr reg = r / ^* see table ^* / RPOP pop Return stack operation: ^* (sp −−) = next; next = tos; tos = ^* rp−−; Encoding: 0101 0100 1110 RPUSH tos pushes back to stack Operation: ^* (++ rp) = tos; tos = next; next = ^* (++ sp); Encoding: 0101 0101 1110 Operation to move IN I / O register to TOS: ^* (sp −−) ＝ next; next ＝ tos; tos ＝ reg; Encoding: 0100 00rr rrrr Operation to store OUT TOS in I / O register: reg = tos; tos = next; next = ^* (++ sp); Encoding: 0100 01rr rrrr LDC (to TOS) Operation to store constant: ^* sp −− == next; next = tos; tos = constant; Encoding: 0101 111H bbbb if (H == 0) constant = 0000: bbbb; else constant = bbbb : 0000 LD (bp + 2) Operation to load from base page: ^* sp −− == next next = tos tos = ^* (bp + source); Encoding: 0100 10aa aaaa source = aa aaaa LD (bp + p) + a Indirect load (TOS where byte is addressed by pointer at bp + offset and then indexed by TOS) Operation: ^* sp −− == next; next = tos tos = ^* ( ^* (bp + 2p) + offset ); Encoding: 011p p0aa aaaa offset = aa aaaa ST (bp + a) Operation stored in base page: ^* (bp + dest) = tos tos = next; next = ^* (++ sp) Encoding: 0100 11aa aaaa dest = aa aaaa ST (bp + p) + a Store indirectly (TOS into the byte addressed by the pointer in bp + 2p offset by a) TOS operation: ^* ( ^* (bp + 2p) + offset) = tos; tos = next; next = ^* (++ sp) Encoding: 011p plaa aaaa offset = aa aaaa [ALU group] Operation: if (r == 1) {hibyte (ip) = ^* rp −−; lobyte (ip)
＝ ^* rp−− ；} pipe ＝ tos; ／ ^* internal processor pipeline ^* ／ tos ＝ tos op next; switch (s) {cace 0: next ＝ next; ／ ^* typical una
ry op ^* / case 1: next ＝ ^* (＋＋ sp); / ^* typical bin
ary op ^* /} encoding: 0101 00rf ffff op = fffff / ^* s equal to high order f bi
t ^* / s = (1 == unary op), (0 == binary op) SWAP Special Case The exchange of TOS and NEXT is a special case of ALU ops that uses a direct data path between TOS and NEXT. The NEXT register receives cc of TOS via the pipeline register before loading the contents of NEXT to TOS (non-simultaneous transfer).

NOP operation: ++ ip; Encoding: Short 0010 1000 0000 Long 0101 0001 1101 RET Return from subroutine Operation: hibyte (ip) = ^* rp−−lobyte (ip) = ^* rp −− +++ ip; Encoding: 0101 0011 1101 [LITERAL Group] Operation: tos = tos op constant; Encoding: 0101 1ffH cccc op = ff if (H == 0) constant = 0000: cccc else constant = cccc: 0000 Op Table: Code operation Carry state 00 tos + constant arith Carry 01 tos-constant arith borrow 00 tos AND constant 11 constant (see LDC) F. Six-choice circuit As mentioned above, means for encoding 4 bit nibbles into 6 bit words for transmission (Fig. 14). Coder) and means for decoding 6-bit words into 4-bit nibbles (decoder in FIG. 15)
And ALU 102b includes. The encoder and decoder use hard-wired logic that allows the conversion to be very fast in both directions. In addition, a circuit to confirm that the 6-bit word received by the cell is actually a six-choice code, that is, three is 0 and three is 1 (Fig. 9).
As shown in the figure.

Referring to FIG. 14, register 142 is shown. Four bits of the register contain data D0-D3. If the ALU were commanded to encode this data, the resulting 6 bits will be coupled to the latch register 145b.
To perform the conversion shown in FIG. 9, the D ₀ bit is directly connected to the first stage of register 145b to E ₀ , the encoded bit. Bit D ₃ is directly connected to the register and becomes E ₅ . Each of the remaining bits E _{1 to} E ₄ is a logic circuit 153.
~ 150 each supplied. Each of those logic circuits is coupled to receive D ₀ , D ₁ , D ₂ , D ₃ . Each logic circuit includes a normal gate. The gates implement the equations shown in their respective blocks. These expressions are standard "C" language ("&" = logical AND,
"!" = Logical notation, "|" = logical OR). These equations can be realized by a normal gate.

The decoder of Figure 15 is shown in a similar format.
At this time, 6 bits of encoded data are in the register 14
Shown in 2. The four decoded bits of data are shown in register 145. To implement the pattern assignment shown in FIG. 19, the E ₀ bit is directly connected to register 145 to become D ₀ . E ₅ bits is D ₃ is directly connected to the register 145. Logic circuits 154 and 155 have bits D ₂ and D ₁
Supply each. Circuit 154 shows bits E ₀ , E ₃ , E ₄ , E ₅
Combined to receive, circuit 155 receives E ₀ , E ₁ , E ₃ , E ₅ (E ₂ is not used to provide D _{0 to} D ₃ bits.) With a 6-bit pattern Is not used and the others are used for synchronization, so no conversion to data nibbles is necessary. ) Circuits 154 and 155 are composed of conventional logic gates and implement the equations shown. The symbol "^" represents the exclusive OR function in the formula.

The circuit shown in FIG. 16 receives 3 bits of 6-bit words as described above.
Make sure it contains two zeros and three ones. The encoded word is shown coupled from the stack top register 122 to two full adders 157 and 158. These adder stages are included in ALU 102b. Each adder receives an X, Y and carry input and provides a sum and carry output. The conventional adder stages are each coupled to receive a bit of the encoded word, as shown. (Any coupling to the input terminals of either bit 157 and 158 of each bit can be used.) The carry output terminals of adders 157 and 158 are coupled to exclusive OR gate 159. The sum output terminals of adders 157 and 158 are coupled to an exclusive OR gate 160. The output terminals of gates 159 and 160 are AND gate 161.
Is connected to the input terminal of. Assuming the output of this AND gate is in its high state, the word in register 102 will be 3
Contains one 1 and three 0s. In the other case, the output of gate 161 is in its low state (aport state). Incoming packets are examined to determine if each 6-bit word is valid. Meanwhile it is decoded into 4 bit nibbles.

IV Input / Output Section A. General The I / O section contains multiple circuit elements such as ramp generator, counter, comparator, etc. The circuit elements are interconnected in various configurations under software control. Examples of this are shown below for analog-digital (A-D) and digital-analog (DA) operation. The devices and their software-configurable interconnects provide the cells with great flexibility and allow the cells to perform many tasks. The entire I / O section is preferably manufactured on the same "chip" that contains the processor.

B. Buffer Section As shown in FIG. 10 and, as mentioned above, each cell contains four input / output subsections. 3 out of 10 sub-parts
7, 108, 109 each have a pair of leads, shown as Pin A and Pin B. Fourth sub-portion 110 is 1
It has a "read only" pin 106 of the book. Any of the four sub-parts can communicate with any of the four sub-processors. First
As shown in Fig. 12, this can be easily realized by connecting the address bus (ADBUS) and the memory bus (MBUS) to the four I / O sub-units. The use of MBUS to DBUS via register 146 enables the I / O subsection to communicate with the processor register.

Each pin A / B can receive and supply a TTL level signal, and is set to three states. In the presently preferred embodiment, each pin receives and can deliver about 40 milliamps (pin 106).
except for). All pins A can be programmed to provide an analog output signal and three I / O subsections 107, 108, 109 include digital to analog converters to provide an analog output to pin B. The analog input signal at any pin B can be converted to a digital count. The reason is that the three I / O subsections are connected to their pins by A-
This is because the D converter is included. Each pin pair (Pin A and Pin B) has a differential amplifier for the input signal, a differential receiver,
It can operate as a differential transmitter and a differential voltage comparator. The I / O subsection can be used to perform many different functions, from simple switching to, for example, having two pairs of pins coupled to drive the windings of a stepping motor.

The circuit shown in FIGS. 17-23 is repeated in subsections 107, 108, 109. The circuit associated with Pin A and Pin B (such as the buffer section in Figure 17) is the I / O subsection 1
Not fully included in 10. Only sufficient buffering is needed to allow the data to be read at pin 106.

With reference to the I / O buffer section of FIG. 17, the outgoing data is coupled to pin A via buffer 163. Similarly, if the data is I
After passing through the I / O control switch 165, the output data is buffer 1
Connected to pin B via 64. This outgoing data is coupled to pin A, for example, from register 206 of FIG. 23 through gate 208 of FIG. A control switch 165 is used to enable output to pin A through buffer 163 when enable A (EN.A) is high (line 166). Furthermore, the switch has a high enable B (EN.B) (line
167) When enabling output to pin B, enable RS-4
When 85 is high (line 168A), it allows output to both pins (the output to pin B is inverted). The outgoing analog signal to pin A is provided through switch 175 when the enable analog output signal is high.

The incoming signal on pin A is coupled to one input terminal of differential amplifier 169. The other terminal of this signal receives a reference potential (eg 2.5 volts). The amplifier also includes a hysteresis mode that is commonly used to prevent the detection of noise. The mode is activated when the enable hysteresis (Pin A) signal coupled to amplifier 169 is high. The output terminal of amplifier 169 is coupled to transition detection circuit 171. The transition detection circuit is for each transition, 0 to 1
, Or 1 to 0 is simply detected.

The input to pin B is coupled to one terminal of differential amplifier 170. The differential amplifier can be the same as amplifier 169. Amplifier 170 receives the enable hysteresis (Pin B) signal. The other input to amplifier 170 (line 176) can be combined to receive one of several signals. It can receive a DC signal used for voltage comparison, a ramp as described below, a signal on pin A for difference detection, or a reference potential (eg 2.5 volts). For some modes of operation, the output of amplifier 170 can be inverted through exclusive OR gate 177. The input on pin B is combined with the transition detector 172 to detect the 0 to 1 or 1 to 0 transition again.

CI / O counting / timing Each cell contains a timing generator (RC oscillator) to provide a 16 mHz signal. This signal is coupled to the rate multiplier 178 included in the I / O section. This multiplier 178 supplies the output frequency to each I / O subsection. This multiplier 178 supplies the output frequency to each I / O subsection.

This multiplier Supply a frequency f ₀ equal to The value loaded is the 16-bit word loaded into the register to the rate multiplier 178. The rate multiplier has four 16-bit registers and one 16-bit counter chain. Four types of output signals can be selected by four logic circuits, one for each sub-unit. 16-bit rate multiplier using 2 bus cycles (8 bits each)
Used to load 178 registers. As can be seen from the above equation, a relatively wide range of frequencies can be generated. As will be explained later, those frequencies are used for many kinds of functions including bit synchronization.

The output of multiplier 178 in each subsection is coupled to an 8-pin counter 179. The counter can first be loaded from the counter load register 180 from the processor's data bus. This register can receive data from a program, for example. The count in the counter is coupled to register 181 and comparator 182. The contents of this register are also loaded from the processor's data bus. When the comparator 182 detects that the contents of the counter and the contents of the register 183 match; it supplies an event signal to the state machine 19 of FIG. 19 (input to multiplexers 190 and 191). Signals from the state machine (No.
The contents of the counter 179 can be held in the register 181 when receiving the output of the execution register 198 in FIG. 19).
The same run register 198 can be loaded by the counter 179 from register 180. When the counter reaches full count (end count), the signal is coupled to the state machine of FIG. 19 (input to multiplexers 190 and 191).

DI / O Control and State Machine Referring to Figure 19, the processor MBUS is a register 185, 186.
Communicate with. Both registers perform a masking function. Three bits of register 185 control the selection of one of the five lines coupled to multiplexer 190. Similarly, 3 bits of register 186 control the selection of one of the five lines coupled to multiplexer 191. The output terminals of masking registers 185 and 186 are multiplexers 187.
Be combined with. Five bits from multiplexer 187 are coupled to register 198. Each of those bits defines a different function that is actually performed by the state machine. Especially, those bits are load counter, latch count, enable lamp switch, pulse pin A,
Control the pulse pin B.

The multiplexers 190 and 191 receive the termination count signal from the counter 179 and the comparison signal from the comparator 182 in FIG.
The ramp start signal from the ramp generator 200 and the first
It receives respective transition A and transition B signals from the transition detectors 171 and 172 of FIG. The one bit output from each multiplexer 190 and 191 is coupled to an OR gate 188. When the outputs from both multiplexers 190 and 191 occur simultaneously, the priority of the output of multiplexer 190 is multiplexer 1
Control 87 with the signal shown as "which event".
This signal is 3x3 first in, first out (FIFO) buffer 199
Also stored in. This signal indicates which of MUX 190 and 191 received the event and this data is available on Pin A and Pin B (17th
It is stored in FIFO199 together with the input to (Fig.).

The state machine for each I / O subsection has four D-type flip flops connected in series as shown inside dashed line 189 in FIG. Flip Flop 194 and 196 are 8m
Upon receiving the Hz signal, flip-flops 193 and 195 receive the complement of this timing signal. The clocking signal (CLK) is available at the Q output of flip-flop 194 and is coupled to register 198 and a FIFO. The clear signal received from the Q terminal of flip-flop 169 is coupled to register 198.

In operation, masking registers 185 and 186 are loaded under software control. For example, a bit from register 185 causes one of the input lines to multiplexer 190, eg, the termination count, to be selected. Then wait for the circuit signal termination count in FIG. When the signal termination count occurs, the state machine begins operation and the 5 bits of data from register 185 are connected to register 198 via multiplexer 187. The state machine produces an output on one of the lines from register 198, pulsing pin A, for example. Similarly, the word in register 186 is again used to load the counter, for example.

The flip flops 203 and 204 are clocked by the output of register 198. The output signal can be controlled by these flip flops. OR gate 208 allows the data from shift register 206 of FIG. 23 to be coupled to pin A. This register will be described later.

The lower 6 bits of ADBUS are the I / O sub-units 107, 108, 10 in FIG.
Input to the decoder in 9, 110. Two of the bits are used to select a particular I / O element, the rest are decoded to control the operation. The PLA 136 of FIG. 11 has a generalized output terminal 215. This output terminal is used by all I / O sub-units 107, 10 to select the ABUS clock cycle to use the data to control the operation of the I / O sub-unit.
Connected in parallel to 8, 109, 110.

E. Analog-to-Digital and Digital-to-Analog Conversion Referring first to Figure 20, the I / O subsection includes a ramp generator 200 that continuously generates ramps of known period.
The output of this ramp generator is buffered via buffer 201 and selected by switch 202. The switch is selected at a certain time (time) following the start of each lamp, as described below, thereby coupling the same potential to capacitor 203. This capacitor is charged and the potential is coupled to pin A through buffer 204 when switch 175 is closed. (Switch 175 is shown in FIG. 17). Switch 202, capacitor 203, buffer 204 and act as sample and hold means.

Explain how digital-to-analog conversion is performed, and use software by the I / O controller and state machine of FIG. 19 to perform various functions. To show how we can reconfigure
In FIG. 21, some of the circuit elements described above are drawn again.

The appropriate frequency (f ₀ ) is selected from the rate amplifier 178 or counter 179 of FIG. 18 for analog-to-digital conversion. It corresponds to the period of the ramp generated by the ramp generator 200 (Fig. 21). Register 183 is loaded with the digital value corresponding to the desired output analog value.
When the ramp is started, the ramp start signal is coupled via state machine 189 of FIG. 19 (eg, multiplexer 190 and flip-flop). Then the f ₀ signal is the counter
Counted within 179. Then the comparator 182 is the counter
Compare the contents of 179 with the contents of register 183. If the two words are the same, a compare signal is applied through multiplexer 191 to reactivate the state machine as indicated by "SM ₁ " and to activate the sample and hold means 18
Close switch 9 and switch 202. The ramp switch 202 is closed (eg, for 500 nanoseconds) for each lamp produced by the ramp generator, causing the capacitor 203 to charge to a DC voltage corresponding to the digital number placed in the resistor 183.

One way in which A-D conversion can be done is shown in FIG. Input analog signal is 1 of differential amplifier 170
It is added to two input terminals. A lamp is added to the other terminal of amplifier 170. First, when the lamp is started, the state machine 189 loads registers 180 to counter 179 (eg, all zeros). The counter is clocked at a frequency (f ₀ ) appropriate for the lamp period. When transition detect 172 detects that the potential at pin B and the ramp have the same potential, state machine 189 causes latch 181 to hold the count in counter 179. The digital word in latch 181 corresponds to the DC potential at pin B, thereby providing an analog-to-digital conversion.

FI / O Communication As described above with reference to FIG. 1, for example, each cell can send data via a communication line or other link. The cells in the sub-channel send data at the same rate typically determined by the communication link employed, eg, 10K BPS in noisy environments such as for power lines. In the presently preferred embodiment, the cell does not have a crystal oscillator and utilizes an RC oscillator. The latter is not particularly stable, with frequency variations occurring as a result of temperature variations and process variations. In addition, there is no synchronization between cells, so each cell must be synchronized with the incoming data in order to properly read the data. One feature of all cells is that when they detect and store the frequency of the incoming data and acknowledge the packet, they can send them at the frequency at which the original packet was sent. . This reduces the burden on the cell to synchronize when it receives the acknowledgment packet.

Referring to FIG. 23, the I / O sub-unit hunts data during the hunting mode. During this mode, the rate multiplier supplies the frequency (f ₀ ) to the counter 179 and a number from MBUS is loaded into register 183. A match occurs and is detected by the comparator 182 at a frequency corresponding to the expected incoming data rate. In particular, the terminal count of counter 179 is synchronized with the transition. As indicated by the dashed line, the processor constantly seeks transitions from the transition detectors 171 and 172 of FIG. When a transition occurs, the processor determines whether the transition occurred before or after the termination count, and then adjusts the frequency (f ₀ ) until the termination count is detected at the same time the transition is detected. . This frequency is the shift speed of shift register 206. (The process performed by the processor is illustrated by blocks 210 and 211 in FIG. 23.) Register 18
The number loaded into 3 is the time at which the transition occurs and register 206
It shifts the phase to and from the ideal time to shift the data within. This prevents shifting of data during transitions. Note that counter 179 is reloaded (eg, all zeros) each time counter 179 reaches the terminal count.

When bit synchronization is performed, the rate required for synchronization (16 bit words) is stored in the processor memory, and is used to set the transmission frequency when the packet for which the rate is generated is acknowledged. This stored bit rate is used in a competitive backoff algorithm that allows the slot period (M) to match the last bit rate received, as will be explained later.

The output of the comparator is used as the shift speed for the 6 shift register 206. During hunting mode, the data from pin B is continuously shifted in register 206. As shown in FIG. 9, the packet preamble (010101-bit synchronization) is shifted along the shift register 206, and the shift is adjusted so as to be synchronized. When the packet start flag appears (Nibble Sync-101010), the register
The last two stages of 206 contain a 1, which is detected by Andgate. A binary one at the output of gate 207 ends the hunting mode and causes nibble synchronization. When this happens, data is clocked into the data latch 235 from the shift register (6 bits) from which data can be clocked into the processor and converted into 4 bit nibbles. Additional circuit means are provided to detect all zeros in shift register 206. When this happens, the processor and shift register return to hunt mode.
The number loaded into register 183 is the time at which the transition occurs,
The phase is shifted to and from the ideal time to shift the data in the register 206. This prevents shifting of data during transitions.

The data to be transmitted is transferred to the data register 205.
(Only 6 bits representing 4 bit nibbles are data registers.
Note the transfer to 205. ) Then those 6 bits are transferred to the shift register 206 and shifted out at the shift speed for output. As described above, assuming that the packet output by the digit shift represents the confirmation response, the digit shift speed corresponds to the rate of the incoming data. On the other hand, if the output packet is to be sent to several cells, the shift rate is the nominal shift rate for transmitting cells.

(Note that FIG. 23 shows how the data leaving the register is only sent to pin A. In differential mode, the complement of pin A is driven to pin B. and Other variants are possible.) GI / O registers and resource sharing Each I / O sub-part has several registers to which the MBUS is bidirectionally connected. These registers are the I / O sub-part 1 of Figure 12.
It is located at 07, 108, 109, 110. Reading and writing these registers under the control of the processor program configures the I / O subsection for proper operation. FIG. 12 shows four I / O sub-units 107, 108, 109, 110, and MBUs.
Shows the connection to the lower 8 bits of S and the lower 6 bits of ADBUS. Two ADBUS bits select one of the four I / O units and the remaining four bits are decoded to select one of its sub-I / O control and status registers (described below) . In order to control the operation of the I / O subsection, P
There are two lines from LA136. One line is "read" and the other line is "write". If appropriate, these lines are active in phase 3 of the clock cycle.

The I / O registers, functions, and bit definitions are listed below.

Write register: (controlled by the "write" line).

Event 0 Configuration Register: Register, Masking, 185th 19th
Figure: Bit 0: Toggle pin A when an event occurs Bit 1: Toggle pin B when an event occurs Bit 2: When event occurs 8 bit count latches 3: Event occurs Close lamp switch (temporarily on) Bit 4: Load 8 bit count when event occurs Bits 5-7: Input Multiplexer: MUX190, Figure 19.

000 Transition on pin A 001 Transition on pin B 010 Terminal count event 011 Count comparison event 100 Ramp start event 101 Pin B comparison event Event 1 Configuration register: Masking register 186, 19th
Figure: Bit 0: Toggle pin A when an event occurs Bit 1: Toggle pin B when an event occurs Bit 2: When event occurs 8 bit count latches 3: Event occurs Close lamp switch (temporarily on) Bit 4: Load 8 bit count when event occurs Bits 5-7: Input Mux: MUX191, FIG.

000 Fiber at pin A 001 Fiber at pin B 010 Terminal count event 011 Count comparison event 100 Lamp start event 101 Pin B comparison event I / O register and resource sharing 8 bit Counter load register: Counter load register 180; Figure 18 Bit 0 ~ 7 = count Write communication data output register: data register 205,
FIG. 23; Bits 0-7 = Data Write Communication Configuration Register: (not shown) (loaded from MBUS) Used to configure communication sub-units for transmit and receive functions.

Bit 0: 0 = Receive, 1 = Transmit Bit 1: NOP Bit 2: NOP Bit 3: Shift Register Rice 1 Bull Bit 4: Enter Hunting Mode Bit 5: NOP Bit 6: NOP Bit 7: NOP Output Configuration Register 0: (Not shown) (loaded from MBUS) Used for analog and digital pin configuration.

Bit 0: Enable pin A analog output Bit 1: Enable pin A digital output Bit 2: Enable pin A raised bit 3: Enable pin A lowered bit 4: Enable pin B inverted bit 5: Enable pin B digital output bit 6: Enable pin B raised bit 7: Enable pin B Down Output Configuration Register 1: (now shown) (loaded from MBUS) Used for enable and compare functions.

Bit 0: 8 Bit counter enable Bit 1: Compare pin B with TTL reference Bit 2: Compare pin B with adjustable DC reference Bit 3: Compare pin B with lamp voltage Bit 4: Compare pin B with pin A Compare Bit 5: Enable RS-485 Driver Bit 6: Enable Input Hysteresis at Pin A Bit 7: Enable Input Hysteresis at Pin B Output Configuration Register 2: (not shown) (Load from MBUS) Used to set the pin logic level.

Bit 0: Execute, load the value in the 8-bit counter load register to the 8-bit counter Bit 1: Set pin A to logic level 1 Bit 2: Set pin A to logic level 0 Bit 3: Pin B to logic level Set to 1 Bit 4: Set pin B to logic level 0 Lower half of rate multiplier: rate multiplier 178, Fig. 18 Lower byte of rate multiplier Upper half of rate multiplier: rate multiplier 178, Fig. 18 Bit comparison load register: Load register 183 comparison, 1st
Fig. 8 Byte for comparison Read register: (controlled by "read"line); Event read FIFO: FIFO199, Fig. 19 Bit 0: 0 = Event 1 occurred 1 = Event 0 occurred Bit 1: Event is occurring Pin A level bit 2: Pin B level I / O condition register during event read: I / O status: bit 0: input pin A bit 1: input pin B bit 2: 1 = lamp comparison bit 3: NOP bit 4 : NOP bit 5: 1 = FIFO has data 0-FIFO empty 8 bit Counter lamp: Register 181, Figure 18 Count byte communication data: Data register 235, Figure 23 Data byte Communication status: (not shown) ( Read to MBUS) Bit 0: Receive mode: 1 = Data available in shift register Transmit mode: 0 = Transmit register ready bit 1: From 23rd to hunt mode Resource sharing: Processor in the presently preferred embodiment. Shared between There are five resources. They are EEPROM and four I / O subsections. Hardware "Signal (Semaphore) register"
Five words in (SR) and RAM are used to control resource sharing. Figure 30 shows how multiprocessors share common resources. SR95 in FIG. 12 reads and writes bit 0 of MBUS.

Each RAM word has one state; Idle, Proc. # 1, Proc. #
2, Proc. # 3 or Proc. # 4. Processors can query RAM locations before allocating resources to see if a resource is in use. If the resource is not allocated, it will access the signal register as follows. (Alternatively, the processor skips the first RAM query and checks the RAM location after accessing the signal register.) If the resource is already in use, the processor clears the signal register to "0" and tries again. wait. If the resource is "idle", the processor allocates the resource by changing the state of the RAM register from "idle" to "Proc. # X" and then clears the signal register to "0". When the processor finishes its resources, it clears the RAM location to "idle".

SR is a 1-bit hardware register. During phase 3 of its respective cycle, each processor can access the SR upon request. In the time series,
This means that the processor can access SR295 once in one of four consecutive clock cycles (eg phase). SR295 is normally set to "0". In FIG. 30, processors # 1 and # 3 do not require the use of SR295. At the beginning of the cycle it is "0"
If you know that nothing is currently allocated or cleared, set the proper RAM location, and it contains "idle", the processor will insert its Proc. #. Allocate resources and then "clear" SR to "0". If a processor discovers that another processor is using a shared resource, it will not allocate its Proc. # Or will "clear" its SR to "0". In this event it must wait and try again.

Since some operations, such as those in EEPROM, can take up many clock cycles, the processor must "allocate" RAM registers, but must free SR295 while using shared resources. RAM allocated
When the processor is doing its work using the location, it will re-access the SR until it finds a "0". Then they "clear" the RAM location to "idle" and the SR295 to "0". When the processor accesses SR295 and finds "1", it is S
You must always leave R295 in the '1' state and wait for retries.

In the example shown in FIG. 30, Proc. # 4 is shown as requiring shared resources. It queries the SR to see if the SR is free.
The processor performs a "test and set" operation and the SR295
Is already "1", the test and set operations will leave "1" in the register. It has to wait and try again now. It keeps trying until it accesses SR295 and discovers that the resource in the RAM word is "idle".

V Protocol A. Contention General In a typical application, the communication network between cells is lightly loaded and the cells experience little or no contention delay. In the case of heavy traffic, the network can become saturated. Heavy loads can cause collisions and therefore need to be retransmitted. If retransmissions continue to collide, the network can probably saturate. The contention backoff algorithm used in this network scales the traffic quickly over longer time intervals, allowing the system to recover from saturation. If the troughhook does not expand over a long time interval, the system will not saturate and will not recover from saturation.

Access to the subchannels under race conditions is coordinated by two mechanisms: deferral and backoff. Postponement is a collision avoidance technique used in group acknowledgments. Backoff is a technique for balancing traffic, that is, load.

Postponement consists of counting free slots. When the number of free slots seen by the cell equals the deferral count, the cell sends its packet at the next available slot.

When backing off, the cell increases the waiting time before retransmitting a collided packet. The length of the increase is a function of the number of collisions or retransmissions. Algorithms that realize this function are called backoff algorithms or competition algorithms.

This network uses a carrier detect multiple access method that solves the general contention for communication channels. When the cell is ready to transmit, it first listens to the communication channel. If you hear another cell transmitting, that cell waits for an empty channel. When detecting an empty channel, the cell may be delayed before transmission. The method of determining the delay is determined by the competition algorithm.

The time in the channel is measured in slots. Each slot is the M bit at the most recently detected receive baud rate (ie, shift rate). If the cell is delayed before transmission, it waits an integer multiple of slot. When the cell detects a free channel, it may be delayed, and then when it is ready to transmit, it will attempt to transmit on slot boundaries. If a cell is transmitting a packet that has collided, it is delayed by the time interval determined by the backoff algorithm. The backoff delay is randomized uniformly across the N slots. N is adjusted by the backoff algorithm.
It has a minimum value of 2 and is adjusted upward by the backoff algorithm before each retransmission of the packet. Its maximum value is 2 ¹⁰ .

B. Group Acknowledgment Packet Competition A packet from a group announcer to a group of listeners causes each of those listeners to send an acknowledgment to the announcer. Without a way to arbitrate the general conflict between those acknowledgments, those acknowledgments will always collide. To avoid this problem, an embedded reservation device for group acknowledgment is used. The listener cell uses its group component number to determine which slot the listener cell uses for its acknowledgment. Group component 5 is
Following receipt of the original packet, send its acknowledgment in the fifth free slot. The result is that group component 1 sends its acknowledgment in the first slot following the original packet. Group component 2 sends its acknowledgment on the first slot following the first group component. This process continues until the last group member responds to the original packet. If a group component does not respond, thus leaving its response slot empty, the next group component will respond with the next slot.

The conflict and I / O phase diagram is shown in Figure 24. The following table shows the conditions and their description.

C. Collision Detection Collision detection is not used in the presently preferred embodiment. Normal circuitry can be used to provide this feature when the cell is responding, as described in IEEE 802.3. When a collision is detected, the cell can send a jamming signal for one slot time to ensure that all cells on the channel detect the collision. Then it can stop sending and execute the backoff algorithm. The backoff algorithm adjusts the contention randomization interval.
IEEE 802.3, uses the number of collisions experienced by the packet to calculate the backoff interval. Since the cell network does not always perform collision detection, the cell backoff algorithm can use the protocol inferred collisions to calculate the backoff interval. If the cell detects a collision, it will detect a collision in the same slot as it occurred and try to transmit again (after the backoff interval).

In the case of a cell that has a collision but does not detect a collision, the cell will discover it when the protocol timeout period has expired. Assuming the cell is sending packets to multiple destinations (the normal case), when the protocol times out, if there is no response from any of the destinations, the cell infers a collision. Even if one response is received, if there is no collision at the transmission point, retransmission is performed without an increase in delay due to backoff. The cell then performs the backoff algorithm with the estimated collision count, much like it does collision detection. After the backoff interval, the cell sends a packet.

Therefore, the difference between collision detection and collision speculation lies in the length of time required for a cell to discover that a collision has occurred.

D. Backoff Algorithm The backoff algorithm used in the presently preferred embodiment is described in the IEEE 802.3 standard, which is a truncated binary exponential backoff. The backoff interval is an exponential function of the number of collisions (detailed or inferred) since the last successful transmission. The exponential backoff algorithm gives the system the stability it needs to recover from saturation. By exponentially spreading the load on the system being saturated, the algorithm allows the system to recover. R = backoff interval in slot = R as if it is a random number linearly distributed over the backoff interval: 0 <R <2EXP [min (10, n)] where n = number of collisions.

If the cell has two transceivers attached, it will send any packet through both transceivers. Since transceivers access different sub-channels, they experience different load conditions. Each transceiver is treated as a separate sub-channel and has its own backoff parameters (collision count and backoff interval). The backoff parameters are "held" by the cell, one set for each transmission.

Random numbers for the backoff algorithm are generated in one of two ways. 1. By a pseudo-random number seeded with a 48-bit cell ID (which is guaranteed to be unique as explained below), 2. When a counter is activated and an external event is detected By holding lower bits.

The duration of the slot is equal to the bit rate of the last data received. Note: If each cell uses its internal bit rate, the slot duration will vary from cell to cell.

E. Contention Timer Packets with multiple routes to their destination experience longer contention delays when traversing one route and shorter delays when traversing another route simultaneously. If the contention delay is allowed to be too long, a later packet may arrive after the destination's received sequence number cycles back to the same sequence number in the packet. Therefore, a packet can be reached out of its order without the ARQ protocol detecting it. To avoid this kind of error, each packet uses a contention timer field (FIG. 6) that is reduced by the number of slots the packet waits for contention at each hop in the multi-hop path. When the count reaches 0, the packet is discarded.

F.ARQ Protocol Cell uses a sliding window protocol. The window has a size of 1 and is Modulo 2 serial numbering (stop and wait protocol). The link control mechanism is very similar to HDLC synchronous balanced mode. The main difference is that instead of acknowledging the packet, every information packet must have an acknowledgment, with a 1-bit serial numbering.

Before the ARQ mechanism can work, a connection must be made between the two communication devices (cell or network controller). The connection process is described in the "Connection" section later in this application. The ARQ mechanism only works when the cell is in the connected state. The ARQ state can be considered as a substate of the connected state.

When a cell sends a message, it waits for a response from the destination. If the cell does not receive an acknowledgment within the predetermined timeout period, it assumes that the message has been lost and retransmits the message.

Two types of packets can be used to carry the acknowledgment, either the acknowledgment only packet or the information packet. The acknowledgment is carried in the packet's received sequence number. Only acknowledgment packets have no message field and are identified by the ACK command in the link command field. The information packet contains a message field and is identified by the INFO command in the link command field.

FIG. 25 is a link level ARQ state diagram which defines various ARQ states with the table below.

The cell stores a transmission sequence number for each address it communicates with. The address can be a cell, a group, or a controller. For reception, the source from which it must retain the receive sequence number of each source it receives can be a cell, a group, or a controller. When a cell receives a message, it has a CRC about the message.
To inspect. If the CRC is not valid, the cell will not respond to that message. If the sequence number indicates that this is a duplicated packet, the cell acknowledges receipt of the packet to the sender but does not send the packet to the application software.

Used by the bit ARQ protocol which means "this is a retransmission by the sender". If the message does not have its retransmission bit, the recipient will not acknowledge the duplicate message. The cell holds a sequence number for its last received message for each group that is a listener for the last received message. It has a separate 1-bit transmit sequence number and 1-bit receive sequence number for messages addressed by the cell address (used when communicating with the controller).

Communication between cells takes place via the group address. In those cases the cell communicates with a clustering device or network controller. Since a cell is prepared to store only one set of those serial numbers, a cell can have only one conversation using the cell address at any given time.

When a controller wants to communicate with a cell, it initiates communication by sending a packet with a connect command in the link control field. The command initializes the sequence number. After receiving that command, the cell will not receive any messages addressed to it (via the cell address) by another controller until the end of the conversation. The conversation ends when the controller sends a disconnect command.

The time the cell waits for a message acknowledgment depends on the type of route used. In general, a cell allows sufficient time for the packet to reach its destination, plus the protocol processing time at the destination cell plus the time for the return packet to carry the acknowledgment.

The protocol timeout period for multi-hop packets is also affected by the collision count. Even in a very noisy environment, the reason why a packet cannot reach its destination in time is often contention rather than transmission error. When the packet is retried, it is assumed that the collision count indicates the system load and the expected contention delay for the multi-hop packet. The delay time for the multi-hop packet is adjusted upwards as a function of collision count. Therefore, the time-out period is a function of the transmission pow rate, the number of hops, and the collision count.

G. Link control command The link control command controls the operation of the ARQ protocol and the link connection process (see the next section). The link command field of the packet always contains the link command.

ARQ protocol command INFO Information packet (acknowledgement required) ACK Acknowledgement only packet (acknowledgement not required) Connection control command CONN Connection DISC Disconnection SI initialization setting XND Network data exchange Response to connection control command CMDR Command removal RD Request Detachment RI Request Initialization UA Only packets that have unacknowledged acknowledgment ACKs and commands and INFO commands use sequence numbering. The INFO packet has two serial numbers, a transmit serial number, and the serial number of the last received packet. The ACK packet has both sequence number fields, but the transmit sequence number is ignored by the destination.

Packets with commands other than ACK or INFO are called unnumbered packets. Packets that cannot be numbered are acknowledged at the stop and wait for a fashion via the UA command. Non-numbered packets do not include message fields.

H. Connection Control Before a controller can communicate with a cell, it must connect to the cell. Making a connection initializes a sequence number and
It consists of putting the controller and the cell in a known state. The procedures for establishing and maintaining the connection are governed by the implementation of the state machine in software.

The announcer cell must connect to the listener cells in its group. The announcer can communicate with the listener only when the connection is made. The connection is controlled by a subset of link control commands. Orders are issued by the main station. The second station receives the command and sends a response to the Lord. The listener is second. When communicating with a cell that is a network controller, the controller is the primary and that cell is secondary. The link control command and its response are shown below. INFO and ACK commands are ARQ protocol commands,
The rest are connection control commands.

The connection state diagrams of FIGS. 26 and 27 show the main station and the second station. The main station controls the connection. The second can request that the connection state change, but the second cannot do unless commanded by the main station to change the connection.

Note: Retry: The response can be retried N times. Retry N + 1
The event to be performed is defined as a fatal error and causes initialization. The cell keeps one retry count and either INFO or
The count is decremented when any response other than ACK is retried. The retry count is always cleared when a non-retry response is sent to the main cell.

I. Add Sequence A cell sending a packet can send that packet by sending an add sequence instead of continuing to send the packet. The add sequence is a group of at least 12 packets sent sequentially and the receiving cell is the 16th
Identify the adder from the code identifier in the figure. The receiving packet treats any violation of the six-choice sign as an append. One result of this is the link idle condition, which is an export. If the link is idle (no transition) for more than the bit time, the result is a code violation. When a cell receiving a packet detects an add sequence, it discards the portion of the packet that was clocked in and begins searching for a new packet preamble. The add sequence is also used to jam after detection of a collision.

J. System ID See Figure 29, which shows how to use a 48-bit system ID in a packet. A 32 bit system ID, shown as field 251, is placed directly in the packet, as shown by field 255. The remaining 16 bits are used to calculate the packet CRC. Initially, at the beginning of the CRC calculation, the CRC register starts with all 1's as indicated by field 252. Then 1
A 16-bit field 250 system ID is used in the CRC calculation to provide a 6-bit field 253.
Field 253 is stored in EEPROM and is used as the preset CRC field each time the packet CRC is calculated.

Once the preset field is stored and the packet is sent, the stored CRC field is stored in the CRC register. A 16-bit packet CRC field is calculated using this current field, and another field in the packet is used to calculate the packet CRC. (All fields are used except the contention timer field.) Another 32 bits of system ID are sent in the packet.

When a packet is received, the processor calculates the CRC for the received packet by first placing the CRC preset field stored in its CRC register (again, the contention timer field is not used).
If the newly calculated CRC field does not match the field in the packet, then the packet was sent improperly, or the sent packet was received correctly,
They are considered to have different system IDs and should therefore be discarded.

VI Clustering Device The clustering device can take various forms and can be realized by commercially available hardware such as a personal computer.
The computers can be easily programmed to perform the various functions described in this application that are performed by the clustering device. For example, they can be easily programmed to get the packets needed to communicate with the cells for grouping. Other functions, such as the generation of random numbers used in packets, can be generated by well known programs.

For example, an Apple II computer can be used as the grouping device. A 48-bit system ID can be stored on the disk. Alternatively, a printed circuit card can be provided that is inserted into one of the slots of the Apple II computer. The card may include a system ID obtained from a cell such as cell 232 in FIG. Once the group is formed, the assigned group number, component number, etc. can be stored on the disk or in an EEPROM on the card.

The elements of this preferred grouping device are shown in FIG.
CPU226 is contained in the number etc. of those elements. That cpu
Can be composed of ordinary multiplexers. The CPU communicates with the memory. The memory can include RAM 227, ROM 228, and storage 229 for storing the system ID. If the Frotpy disk is used,
The system ID and program (other than those stored in ROM 228) are stored on disk and the program is transferred to RAM for execution.

Display means 230, such as a conventional monitor, is coupled to the CPU for displaying to the user. For example, a display device can be used to display a list of groups with the ASCII name of the group. A keyboard 231 is used to enable input of commands to the CPU.

The CPU is shown coupled to cell 232. The cell is coupled to the network via transceiver 233. Cell 232 is part of the grouping device and is the I
D is used as a system ID by the grouping device. A typical message sent to the cell by the computer is shown in Appendix B. For example, the message that assigns the destination cell to the announcer in the group is the message generated by the grouping device. The grouping device may be directly coupled to the cell via one of three pairs of leads coupled to the I / O subsection, or may read a message from the CPU 226 into the fourth I / O subsection. It is coupled to the cell via a select pin that allows it.

The network having distributed intelligence and performing detection, communication and control has been described above. Although a simple example of using the cell in a home environment is described in this application, it will be apparent to those skilled in the art that the disclosed invention can be used in numerous other applications. Appendix C of this application contains a table of some other applications in which the present invention may be used.

Appendix A. Packet Examples Routing Type Examples for Packet Examples 1. Fully Addressed 2. Open Flooding 3. Restricted Flooding 4 . Group Flooding Note: The packet size is a cell memory bit (before six-choice coding). The packet on the communication subchannel is 50% larger after the six-choice coding conversion.

Single-hop packet format: preamble, 16-bit flag, 4-bit destination cell address, 48-bit contention timer, 10-bit contention timer checksum, 6-bit hop count, 4-bit random number generator, 8-bit link control retransmission flag, 1 Bits Rcv Seq, 1 Bit XmtSeq, 1 Bit Not used, 1 Bit Command, 4 Bit Network Control, Routing Type, 4 Bits = 1 (Completely Addressed) Source Cell Address, 48 Bit Message, 16 ~ 512 bit message type, 8 bit message content, 8 to 511 bit encryption check, 16 bit CRC, 16 bit flag, 4 bit single hop response format: preamble, 16 bit flag, 4 bit system ID, 32 bit destination cell address, 48-bit contention timer, 10-bit contention timer M checksum, 6 bit hop count, 4 bit random number generator, 8 bit link control Retransmit flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit not used, 1 bit command, 4 bit network control Routing type 4 bits = 1 (completely addressed) Source cell address, 48 bits Encryption check, 16 bits CRC, 16 bits flat, 4 bits Multihop full address packet format: preamble, 16 bits flat, 4 bits System ID, 32 bits Next cell address, 48 bits Contention timer, 10 bits Contention timer checksum, 6 bit Hop count, 4 bit random number generator, 8 bit Link control Retransmit flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 Bit not used, 1 bit command, 4 bit network control, routing type, Bit = 1 (completely addressed) Cell Address List Address Count, 4 Bit Address, 48 to 768 Bit Source Cell Address, 48 Bit Message, 16 to 512 Bit Message Type, 8 Bit Message Content, 8 to 511 Bit Code Check, 16-bit CRC, 16-bit flag, 4-bit multi-hop full address response format: preamble, 16-bit flag, 4-bit system ID, 32-bit destination cell address, 48-bit conflict timer, 10-bit conflict timer, check total, 6 Bit Hop Count, 4 Bit Random Number Generator, 8 Bit Link Control Retransmit Flag, 1 Bit Rcv Seq, 1 Bit XmtSeq, 1 Bit Do Not Use, 1 Bit Command, 4 Bit Network Control, Routing Type, 4 Bit = 1 (Completely addressed) Cell address list Store address count, 4 bit address, 48 to 768 bit source cell address, 48 bit encryption check, 16 bit CRC, 16 bit flat flag, 4 bit open flooding packet format: preamble, 16 bit flat flag, 4 bit system ID , 32 bits Broadcast address, 48 bits = all 0 Contention timer, 10 bit Contention timer checksum, 6 bit Hop count, 4 bit random number generator, 8 bit Link control Retransmit flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit Not used 1 bit command, 4 bit network control type of routing, 4 bit = 1 (open flooding) destination cell address, 48 bit source cell address, 48 bit message type, 16 to 512 bit message type, 8 bit Message content, 8 to 511 bit encryption check, 16-bit CRC, 32-bit flag, 4-bit open flooding Response format: preamble, 16-bit flag, 4-bit system ID, 32-bit broadcast address, 48-bit = all 0 contention timer, 10-bit contention timer check total, 6-bit hop Count, 4 bits Random number generator, 8 bits Link control Retransmission flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit Not used, 1 bit command, 4 bit network control Routing type, 4 bit = 1 (complete Destination cell address, 48-bit source cell address, 48-bit encryption check, 16-bit CRC, 16-bit flag, 4-bit constrained flooding packet format: preamble, 16-bit flag, 4-bit system. ID, 32 bits Broadcast address, 48 bits = Part 0 Contention timer, 10 bits Contention timer checksum, 6 bits Hop count, 4 bits Randomizer, 8 bits Link control Retransmit flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit Not used, 1 bit Command, 4 bits Bit network control Routing type, 4 bits = 1 (controlled flooding) Destination cell address, 48 bits Source cell address, 48 bits message type, 16 to 512 bits message type, 8 bits message content, 8 to 511 bits code Check, 16 bit CRC, 16 bit flag, 4 bit constrained flooding response format: preamble, 16 bit flag, 4 bit system ID, 32 bit broadcast address, 48 bit = all 0 contention timer, 10 bit contention timer inspection total , 6 bits Hop count, 4 bits Random number generator, 8 bits Link control Retransmit flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit Not used, 1 bit command, 4 bit network control Routing type, 4 bit = 1 (constrained flooding) Destination cell address, 48-bit source cell address, 48-bit encryption check, 16-bit CRC, 16-bit flag, 4-bit group announcement packet packet format: preamble, 16-bit flag, 4-bit system ID, 32-bit group address, 48-bit contention timer , 10 bits Contention timer check total, 6 bits Hop count, 4 bits Random number generator, 8 bits Link control Retransmit flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit Not used, 1 bit command, 4 bit network control Type of routing, 4 bits = 1 (group flats) Source component No., 8 bits Destination component number, 8 bits, (0 = broadcast) message, 16-512 bits Message type, 8 bits Message content, 8-511 bits Encryption check, 16 bits CRC, 16 bits Flag, 4 bits group Announcement Response Format: Preamble, 16 bit flag, 4 bit system ID, 32 bit group address, 48 bit contention timer, 10 bitlot contention timer checksum, 6 bit hop count, 4 bit randomizer, 8 bit link control retransmit flag. 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit Not used, 1 bit command, 4 bit network control Routing type, 4 bit = 1 (group flooding) Source component number, 8 bit destination component number, 8 bits, (0 = broadcast) encryption check, 16 bits CRC, 16 bits flag, 4 Tool probe packet format: preamble, 16 bit flag, 4 bit system ID, 32 bit broadcast address, 48 bit = all 0 contention timer, 10 bit contention timer checksum, 6 bit hop count, 4 bit random number, 8 bit Link Control Retransmit Flag, 1 Bit Rcv Seq, 1 Bit XmtSeq, 1 Bit Not Used, 1 Bit Command, 4 Bit Network Control, Routing Type, 4 Bits = 1 (Restricted Flooding) Destination Cell Address, 48 Bit Source cell address, 48 bit message, 49-769 bit message type, 8 bit message content, 48-768 bit (route list) encryption check, 16 bit CRC, 16 bit flag, 4 bit probe response format: preamble, 16 Bit Flag, 4 Bit System ID, 32 Bit Broadcast address, 48 bits = all 0 contention timer, 10 bit contention timer checksum, 6 bit hop count, 4 bit random number generator, 8 bit link control retransmission flag, 1 bit Rcv Seq, 1 bit XmtSeq, 1 bit use No, 1-bit command, 4-bit network control, routing type, 4-bit = 1 (constrained flooding) Destination cell address, 48-bit source cell address, 48-bit message field, 8-bit message type, 8-bit message content, route list cipher Check, 16-bit CRC, 16-bit flag, 4-bit probe packet format: preamble, 16-bit flag, 4-bit system ID, 32-bit broadcast address, 48-bit = all 0 conflict timer, 10-bit conflict timer check total, 6-bit hop count, 4-bit random number , 8 bit link control retransmission flag, 1 bit Rcv Seq, 1 bit Xmtseq, 1 bit not used, 1 bit command, 4 bit network control routing type, 4 bit = 3 (constrained flooding) or 2 (Open Frat Reading) Source Address, 48 Bit Message Type, 8 Bit Message Content, 8 to 511 Bit Encryption Check, 16 Bit CRC, 16 Bit Flag, 4 Bit Broadcast Command Response Format: No Response Appendix B. Message Type Probe Function: Determines the best route from announcer to listener.

Source: Group announcer Address type: cell Routing method: constrained flooding Message type: 2 (number for 8 bit fields) Message content: address count (1 byte),
(Number of cell IDs in probe packet-this is the number of packets rebroadcast) Address List Probe Result Function: Report the address list in the first probe packet received by the destination cell.

Source: Cell previously addressed by the probe message.

Address type: cell Routing method: constrained flooding Message type: 3 (number for 8 bit fields) Message content: address count (1 byte), address list group announcer assignment Function: group with destination cell specified Assign to be an announcer within.

Source: Grouping device Destination: Cell Address type: Cell or group component Routing method: Constrained flatting or group flatting Message type: 4 Message content: Group number, component number Group announcer deallocation function: Understand that the destination cell acts as an announcer within the designated group.

Source: Grouping device Destination: Announcer Cell Address type: Cell or group component Routing method: Constrained flatting or group flatting Message type: 5 Message content: None Group listener assignment function: Destination cell specified Assign to be a listener in the group.

Source: Grouping device Destination: Cell Address type: Cell or group component Routing method: Constrained flattening or group flatting Message type: 6 Message content: Group number, component number Group listener deallocator Function: Releases the destination cell from acting as a listener in the specified group.

Source: Grouping device Destination: Listener cell Address type: Cell or group component Routing method: Constrained flooding or group flooding Message type: 7 Message content: None Group repeater assignment Function: Destination cell specified Assign to be a repeater in the group.

Source: Grouping device Destination: Cell Address type: Cell or group component Routing method: Constrained flattening or group flatting Message type: 8 Message content: Group number, component number Group repeater deallocation function: Releases the destination cell from acting as a repeater in the specified group.

Source: Grouping device Destination: Group repeater Cell Address type: Cell or group component Routing method: Constrained flatting or group flatting Message type: 9 Message content: None Repeater assignment function: Function cell as repeater Assign to do so.
Cells that are not normally allowed to be repeaters, ie cells that have one transceiver on a non-radiating medium,
Used to assign

Source: Controller Destination: Cell Address Type: Cell Routing Method: Fully Addressed, Open Bladed, Constrained Flooding Message Type: 10 Message Content: None Closed Function: Command to Resume Broadcast a message telling all cells to stop transmitting until.

Source: Controller Destination: Cell Address type: Broadcast or cell Routing method: Open flooding, constrained flooding Message type: 11 Message content: None Report your input Function: Report cell input To the cell.

Source: Cell or controller Destination: Cell Address type: Any Routing method: Any Message type: 12 Message content: Number of inputs (bytes) Report your output Function: Report the output of the cell Command to.

Source: Cell or control device Destination: Cell Address type: Any Routing method: Any Message type: 13 Message content: Number of outputs (bytes) Download function: Download data or code.

Source: Controller Destination: Cell Address type: Optional Routing method: Optional Message type: 14 Message content: Address, length, code Communication parameter setting Function: Set communication parameters in the cell.

Source: Controller Destination: Cell Address type: Optional Routing method: Optional Message type: 15 Message content: Number of parameters, value Announcement function: Sensor data announcement Source: Group Destination: Group Address type: Group, Broadcast Routing Method: Group Flats Message Type: 16 Message Content: 0-255 (1 byte)

Continuation of the front page (56) References JP-A 61-148564 (JP, A) JP-A 61-151773 (JP, A) US Patent 3916383 (US, A) US Patent 4630195 (US, A) "The X -10 Powerhouse Universal Interface ", Technical Note, Preliminary Nov. 20, 1986, by Dave Rye. "Homenet: A Control Network for Commercer Applications", IEEE Transactions on Consumer Electronics, Olelectric Co. Jun. 9, 1983, J. Franc is, F.F. Gutzwiller, E .; Howell, and W.W. Kruesi. “Home Information and Stsndardization of Home Bus”, IEEE Transactions on Consumer Electronics, Vol. CE-32, No. 3, Aug. 1986, Hatari, Mukuno Lida Ochiai and Horizon. "A Local Network For or Supplement Support", National Electrics Conference, 356, 1982, 356, 1982. A. Davis, A .; V. Pohn, S .; M. Christiansen and d.G. D. Bridges.

Claims (2)

[Claims] 1. In a network including a plurality of cells for performing detection, communication and control, the cell comprises a processor and an input / output (I / O) unit for coupling between the processor and the network. The I / O section includes state machine means for supplying a control signal to the I / O section, event detection means for detecting a predetermined electrical change, and a measurement value of a time interval for the state machine. A plurality of circuit elements comprising a multiplexer directing means and a circuit element coupled to receive signals from the processor, the circuit elements being automated based on signals from the processor to provide a plurality of I / O functions. And electrically configured,
Or a first register means for modifying it and a second register means for storing I / O state information and coupled to the processor for supplying two pieces of information to the processor and coupled to the timing means. And the state machine means is coupled to the event detection means and at least one of the first and second registers so that the I / O unit performs a plurality of I / O functions. A cell characterized by being capable of being configured or modified to do so. 2. In a network for detecting, communicating, controlling, a plurality of first register means for storing digital signals, and for receiving the contents of said register means as an input to an arithmetic logic unit (ALU). At least one ALU coupled to the first register and an output terminal of the ALU, the output of which is coupled to the first register means, and includes a random access memory portion and an electrically programmable memory portion. A memory having, a plurality of input / output units, and a signal register; each of the plurality of first register means performs a plurality of different processes by the first register means, the logic unit and the memory. As with the memory, the AL
Associated with a plurality of different processes performed by U, each of the plurality of inputs / outputs couples each input / output to perform one of the sensing, communication and control functions. At least one lead for connecting the input / output to the ALU and the first register means by a bus, each input / output being selected by a signal on the bus and having its input / Output section has a plurality of input / output registers for receiving signals from the bus and for coupling signals to the bus, the input / output registers receiving signals for controlling the input / output sections and A signal received via a lead is communicated to the bus; the signal register is coupled to the bus to control the sharing of resources within a cell shared by the process; Cells, characterized in that; has an electrically programmable memory unit.