JPH0782073B2 - Self-testable integrated circuit device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a self-testable integrated circuit device capable of testing an internal logic circuit.

[Conventional technology]

Generally, an integrated circuit device includes a plurality of circuit elements that can be classified into combinational circuits such as AND gates and OR gates, and sequential circuits such as flip-flops, registers and memories.

The integrated circuit uses the circuit elements described above to perform the required processing operations on the input data. The number of these circuit elements tends to increase significantly with the progress of integrated circuit technology.
Under such circumstances, it is necessary to accurately assure the quality of the integrated circuit and to locate the defective position when the integrated circuit device has a defect. Therefore, the inspection of the integrated circuit is performed in order to diagnose the integrated circuit device when designing and manufacturing the integrated circuit. Also, such inspections are often performed on the final product used by the customer.

Japanese Unexamined Patent Publication No. 60-68,624 proposes a self-testable integrated circuit device having an internal logic circuit operable as a gate array and a test circuit for diagnosing the internal logic circuit. With this structure, an internal logic circuit can be easily evaluated and tested by using a test circuit.

Specifically, the self-testable integrated circuit device can selectively operate in the normal mode and the test mode, and in the normal mode, the internal logic circuit processes the input data signal in response to the control signal. On the other hand, in the test mode, instead of the input data signal, the internal test pattern signal is processed in response to the internal timing signal determined for each control signal.

As described above, in the test mode, external signals such as input data signals and control signals are not applied from the external circuit to the self-testable integrated circuit device. In any case, in the test mode, each processing operation can be performed in the self-testable integrated circuit by using the internal timing signal and the internal test pattern signal. As a result, the internal logic circuit can be diagnosed and evaluated for each processing operation,
The defect position of the internal logic circuit can be located with high reliability.

[Problems to be solved by the invention]

However, no consideration has been given to an integrated circuit device capable of self-inspection including a complicated sequential circuit element.
This means that a complete test cannot be expected when the complex sequential circuit device is included in a self-testable integrated circuit device. Here, the internal logic circuit has, as a sequential circuit element, an internal memory that stores a data signal, and a certain processing operation is executed using both the stored data signal and the next input data signal. I assume. Further, it is assumed that the self-testable integrated circuit device is tested by using the internal test pattern signal and the internal timing signal in the above-mentioned method. In this case, when the input data signal and the internal timing signal are generated in the test circuit of the self-testable integrated circuit device, no data signal is fixed in the internal memory. Therefore, it is difficult to completely predict the output data signal to be generated from the self-testable integrated circuit device in response to the input data signal or the internal timing signal.

On the other hand, by treating the sequential circuit element as a shift register, the sequential circuit element can be diagnosed. However, such sequential circuit elements have not been tested in relation to the control signals defined for the processing operations of the internal logic circuits.

[Means for solving problems]

According to the present invention, in the self-testable integrated circuit device capable of selectively operating in the normal mode and the test mode, an internal logic including sequential circuit elements and performing a processing operation in response to an internal input signal and an internal timing signal. A circuit, a data input terminal for receiving an input data signal, a control terminal for receiving a control signal representing the processing operation, and a mode signal terminal for receiving a mode signal representing one of a normal mode and a test mode Test pattern generating means for generating first and second test pattern signals respectively defined for the sequential circuit element and the internal logic circuit in response to the mode signal, the data input terminal and the test And a pattern generating means for connecting the input data signal and the test signal in the normal mode and the test mode. First selection means for selecting each of the second test pattern signals, generating a first selection signal, and transmitting the first selection signal to the internal logic circuit as the internal input signal; and the mode signal. In response to the test signal, the timing signal generating means for generating the first and second timing signals defined in relation to the sequential circuit element and the control signal, respectively. Coupled to the control terminal and the timing signal generating means, selects the control signal and the second timing signal in the normal mode and the test mode, respectively, generates a second selection signal, and outputs the second selection signal. And a second selecting means for sending to the internal logic circuit as the internal timing signal,
A self-testable integrated circuit device in which an assigning unit that responds to the first timing signal in the test mode and assigns the first test pattern signal to the sequential circuit element is provided in the internal logic circuit. Is obtained.

〔Example〕

Referring to FIG. 1, a self-testable integrated circuit device according to an embodiment of the present invention can operate in a normal mode and a test mode and has an internal logic circuit 11. In FIG. 1, only a single flip-flop combined with a gate circuit 13, which will be described in detail later, is shown as a representative of the circuit elements, but the internal logic circuit 11 is a combinational circuit element or a sequential circuit element. It contains a large number of circuit elements.

In the normal mode, the internal logic circuit executes a predetermined processing operation. The processing operation may be, for example, addition, subtraction, multiplication, division, read operation, and write operation.

The write operation and the read operation are performed in association with a sequential circuit element, for example, a memory included in the internal logic circuit 11. In any case, each processing operation is executed by accessing the sequential circuit element in response to the internal input signal INI and the internal timing signal INT. The internal input signal INI in the normal mode is the input data signal ID supplied from the external circuit (not shown) through the data input terminal 15, while the internal timing signal INT is the control signal CONT supplied from the external circuit through the control terminal 16. . This control signal CONT is a signal defined for the processing operation.

In the test mode, the circuit device shown can test the sequential circuit elements and the combinational circuit elements of the internal logic circuit 11 in the manner described below. In order to enable inspection of sequential circuit elements, a gate circuit as shown in FIG.
13 includes each sequential circuit element, that is, a flip-flop 12
Are connected.

In the test mode, the sequential circuit elements are tested by forming a series of shift registers or scan paths and sequentially storing the shift register test pattern signals in the series of shift registers according to a clock pulse train. The test pattern signal is the first test pattern signal FP
On the other hand, the scan timing signal will be called the first timing signal FT. First test pattern signal
The FP is composed of a number of bit signals determined by the sequential circuit elements.

Referring to FIG. 2 together with FIG. 1, the internal logic circuit 11 has a test pattern input terminal 21 and a test control terminal 22. In the test mode, the test pattern input terminal 21 and the test control terminal 22 are supplied with the first test pattern signal and the first timing signal FT, respectively.

In FIG. 2, the gate circuit 13 is a first AND gate 2
6, second AND gate 27, OR gate 28, and inverter
29 and. The first test pattern signal FP and the first timing signal FT are applied to the first AND gate 26, while the second AND gate 27 is applied the first timing signal via the inverter 29, and the result signal RE Is also given. The result signal RE represents the result of the processing in the combinational circuit element connected to the gate circuit 13 in question. When testing sequential circuits, the first timing signal
Since FT takes the logic level "1", the first test pattern signal FP is sent to the flip-flop 12 through the first AND gate 26 and the OR gate 28. When testing the sequential circuit device, the flip-flop 12 is connected in series to the gate circuit of the next stage through a connection (not shown) between the flip-flop 12 and the gate circuit 13 to form a scan path. Under this situation, the first test pattern signal FP is sequentially shifted to the flip-flop (not shown) at the next stage.

Thus, when the sequential circuit element is tested by the internal logic circuit 11, the internal logic circuit 11 operates in the scan path mode. The gate circuit 13 and the connection between the gate circuit 13 and the next-stage flip-flop 12 serve to assign the first test pattern signal FP to each flip-flop.
In this sense, the connecting portion constitutes a transmission path for transmitting the first test pattern signal FP.

On the other hand, when the first timing signal FT takes the logic level "0", the result signal RE is stored in the flip-flop 12 through the second AND gate 27 and the OR gate 28.

Referring again to FIG. 1, the circuit device shown has a mode signal terminal 31 for receiving a test command signal TC, and the test command signal indicates either a normal mode or a test mode, and is called a mode signal. .

In the illustrated example, when the test mode is instructed, the test command signal, that is, the mode signal TC takes the logic level "1", and takes the logic level "0" in the normal mode.

The self-testable integrated circuit device has an output terminal 32 for supplying an output data signal OUT to an external circuit.
Is transmitted as a calculation result in the internal logic circuit 11.

In FIG. 1, the mode signal is a test pattern generation circuit having first and second test pattern generators 36 and 37.
Each of the test pattern generators 36 and 37 is provided with a pseudo random number generator in which a plurality of exclusive OR gates and a plurality of flip-flops are connected by a known method. The first test pattern generator 36 has the same number of bits as the number of sequential circuit elements and generates a first test pattern signal determined for the shift register. The first test pattern signal FP is given to the internal logic circuit 11 through the test pattern input terminal 21 and sequentially accumulated in the sequential circuit elements through the scan path in the scan path mode.

Since the operation in such a scan path mode is known, its explanation is omitted here.

The second test pattern generator 37 generates a second test pattern signal SP defined for the internal logic circuit 11, especially for the combinational circuit elements of the internal logic circuit.

As described above, the first and second test pattern generators 36
Since and 37 are composed of pseudo-random number generators,
First, if the structure of each generator and the initial state of each generator are determined
And the second test pattern signals FP and SP can be predicted and reproduced in advance, respectively. This means that the output data signal OUT appearing in response to the first and second test pattern signals FP and SP can be predicted.

If the initial state is determined in the test mode, the first and second test pattern signals FP and SP may be continuously generated in the normal mode.

The second test pattern signal SP is transmitted to the data selector 39 to which the input data signal ID is supplied through the data input terminal 15. This data selector 39 may be called a first selector.

In the illustrated example, the mode signal TC is given to the data selector 39 through the mode signal terminal 31, and the data selector 39 selects either the input data signal ID or the second test pattern signal SP according to the mode signal TC. One is selected as the first selection signal. Specifically, the mode signal
When TC takes the logic level "0" and represents the normal mode, the input data signal ID is selected by the data selector 39 and supplied to the internal logic circuit as the first selection signal. On the other hand, when the mode signal TC represents the test mode,
The second test pattern signal SP is selected by the data selector 39 and supplied to the internal logic circuit 11 as a first selection signal. In either case, the first selection signal is sent to the internal logic circuit as the internal input signal INI.

The connection between the data selector 39 and the internal logic circuit is the first
Serves as a supply circuit for supplying the selection signal of 1 to the internal logic circuit 11 as the internal input signal INI. 1 and 3
The timing signal generator 41 in the figure is the first mode signal.
The timing signal generator 41 is activated when instructed by the logic level "1" of TC, while the timing signal generator 41 is inactivated when instructed in the normal mode.

Timing controller 42 in this test mode
First sends the _first enable signal EA ₁ to the first signal generating circuit 43. In response to the _first enable signal EA ₁ ,
The first signal generation circuit 43 supplies the first timing signal FT to the internal logic circuit 11. The first enable signal EA ₁ is sent from the timing controller 42 to the first signal generation circuit 43.
, The first timing signal FT takes the logic level "1". As a result, the internal logic circuit 11 is placed in the scan path mode, and the first test pattern signal FP is sequentially stored bit by bit in the sequential circuit elements in synchronization with the clock pulse train. The timing controller 42 monitors a predetermined time after receiving the mode signal TC of logic "1", and when this time elapses, sends the second enable signal IA ₂ to the second signal generation circuit 44. Therefore, the predetermined time is determined in relation to the length of the scan path.

In response to the second enable signal EA ₂ , the second signal generating circuit 44 generates the second timing signal ST which is determined in relation to the processing operation of the internal logic circuit 11. Therefore, the second timing signal ST can be associated with the control signal CONT and includes various control signals sequentially sent one by one from the second signal generation circuit 44. Such a second signal generation circuit 44 is a counter and a read only memory (ROM).
Can be configured by a combination of.

In FIG. 1, the control selector 46 has a control signal.
CONT, the second timing signal ST and the mode signal TC are supplied, and either the control signal CONT or the second timing signal ST is selected as the second selection signal according to the mode signal TC. Specifically, in the normal mode, the control signal is
While CONT is selected as the second selection signal, the second timing signal ST is selected as the second selection signal in the test mode. The second selection signal is supplied as an internal timing signal to the internal logic circuit 11 through the connection between the internal logic circuit 11 and the control selector 46. Therefore, this connection portion may be called a supply circuit that supplies the second selection signal as an internal timing signal to the internal logic circuit 11. In this way, after the first test pattern signal FP is stored in the sequential circuit element in the scan path mode, the internal logic circuit 11 can operate according to the control signal in the normal mode, while the internal logic circuit 11 can operate in the second mode in the test mode. It becomes operable according to the timing signal. From this, the test mode can be separated from the scan pass mode and the subsequent modes, and the subsequent mode can be called the non-scan pass mode or the logic test mode.

In either the normal mode or the logic test mode, the output data signal OUT is sent to the output terminal 32 and the output compression circuit 48. It should be noted that the output compression circuit 48 is activated only in the test mode, and the output compression circuit 48 is composed of a signature chair register including a plurality of flip-flops and a plurality of exclusive OR gates, and the first and second test patterns. It serves to generate a specific pattern in response to the signals FP and SP. The signature chair register 48 is a known circuit and will not be described in detail here.

The operation of the self-inspecting integrated circuit device will be described below.

In the normal mode, the input data signal ID is the internal input signal INI
Is supplied from the data input terminal 15 to the internal logic circuit through the data selector 39. The control signal CONT is supplied as an internal timing signal INI from the control terminal 16 to the internal logic circuit 11 through the controller selector 46. The internal logic circuit 11 continuously executes the processing operation indicated by the control signal CONT to process the input data signal ID.
As a result, the output data signal OUT is sent to the output terminal 32.

In test mode, mode signal TC is at logic level "1"
Then, the first test pattern generator 36 is initialized. At the same time, the timing signal generator 41 sets the first timing signal FT to the logic level "1". Logical level "1"
The data selector 39 cuts off the input data signal ID and selects the second test pattern signal SP in accordance with the mode signal TC. Similarly, the control selector 46 uses the control signal CONT
Is cut off and the second timing signal ST is selected.

Under this circumstance, the sequential circuit element of the internal logic circuit 11 forms a scan path by a known method and becomes operable as a shift register. First test pattern signal FP
Are sequentially accumulated in the sequential circuit through the scan path.
After the first test pattern is stored in the sequential circuit element, the first timing signal FT is set to the logic "0" level,
The internal logic circuit is operated in the same logic test mode in the normal mode.

In the logic test mode, the scan paths are separated into individual sequential circuit elements in the manner described in connection with FIG. 2 to perform the unique operation of the individual sequential circuit elements.
In this way, the sequential circuit elements are separated from each other into individual elements. In this case, the second test pattern signal SP and the second test signal ST are given to the internal logic circuit 11 through the data selector 39 and the control selector 16 as the internal input signal INI and the internal timing signal INT, respectively.

As described above, the internal logic circuit 11 is placed in the same logic test mode as the normal mode, and the second timing signal ST is determined in relation to the control signal CONT. Therefore, in the logic test mode, the internal logic circuit 11 simulates the processing operation executed according to the control signal CONT. Each processing operation can be changed by changing each control pulse of the second timing signal SP. The resulting output data signal OUT is sent to the output terminal 32.

If the output data signal OUT is used directly to diagnose the internal logic circuit 11, the output data signal OUT is compared with the expected value determined for that output data signal. In this way, it is determined whether the internal logic circuit 11 is normal.

If the output data signal OUT is formed by multiple digital signals, the output compression circuit 48 will
Transform T into a limited data signal with a specific pattern,
Diagnose limited data signals. That is, the judgment is made depending on whether or not the particular patterns match.

If no defect is found as a result of diagnosis, the mode signal
TC becomes logic level 0, and causes the data selector 39 and the control selector 46 to select the input data signal ID and the control signal CONT, respectively.

The data selector 39 and the control selector 46 are controlled by the mode signal TC in the illustrated device,
These selectors 39 and 46 may be controlled by the timing signal circuit 41.

Similar operations are sequentially executed in the self-testable integrated circuit device. For example, as soon as the diagnosis of the internal logic circuit is completed by the first and second test pattern signals FP and SP, the first test pattern signal FP is changed to a new test pattern signal and the internal logic circuit 11 is changed to the first test pattern signal FP. A similar operation is performed by a new signal replacing the test pattern signal FP. In other words, the first test pattern signal FP
And the similar processing operations may be repeated many times. In this case, when the contents previously stored in the sequential circuit element are not valid, the sequential circuit element, particularly the register content, can be rewritten or refreshed. This allows a valid diagnosis.

Although only the preferred embodiment of the present invention has been described above, various modifications can be made.

For example, the first test pattern signal FP may be stored in the sequential circuit element without forming a scan path. For example, assign a series of addresses to sequential circuit elements,
The first test pattern signal FP may be stored in the sequential circuit element by designating an address at which the first test pattern signal should be stored. For this purpose,
The address may be given from the timing signal circuit 41 instead of the first timing signal FT, while the first test pattern signal FP may be given to all the sequential circuit elements in common.

[Brief description of drawings]

1 is a block diagram showing a self-testable integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a gate circuit used in the internal logic circuit shown in FIG.
3 and FIG. 3 are block diagrams for explaining the structure of the timing signal circuit shown in FIG. Explanation of symbols 11 …… Internal logic circuit, 12 …… Sequential circuit element (flip-flop), 13 …… Gate circuit, 35 …… Pattern generation circuit, 3
9 …… Data selector, 41 …… Timing signal generator, 4
6 ... Control selector.

Claims (4)

[Claims] 1. A self-testable integrated circuit device capable of selectively operating in a normal mode and a test mode, including an internal logic circuit and performing a processing operation in response to an internal input signal and an internal timing signal. A data input terminal for receiving an input data signal, a control terminal for receiving a control signal representing the processing operation, and a mode signal terminal for receiving a mode signal representing one of a normal mode and a test mode. A first test pattern generator for generating a first test pattern signal for the sequential circuit element in response to the mode signal, and a second test pattern signal for generating a second test pattern signal for the internal logic circuit. Of the test pattern generator, the data input terminal and the second test pattern generator, In a test mode, selecting the input data signal and the second test pattern signal, respectively, generating a first selection signal, and transmitting the first selection signal to the internal logic circuit as the internal input signal. And a first timing signal defined in relation to the sequential circuit element and the control signal when the mode signal represents the test mode in response to the mode signal. Timing signal generating means for generating respectively, coupled to the control terminal and the timing signal generating means, selecting the control signal and the second timing signal in the normal mode and the test mode, respectively, and selecting a second selection signal. Generate the second
Second selection means for sending the selection signal of No. 1 to the internal logic circuit as the internal timing signal, and in the internal logic circuit, in response to the first timing signal in the test mode, An integrated circuit device capable of self-inspection, comprising: an assigning unit that assigns one test pattern signal to the sequential circuit element. 2. A self-testable integrated circuit device according to claim 1, wherein said timing signal generating means is responsive to said mode signal, and said mode signal represents said test mode. Enable signal generating means for generating a first enable signal and a second enable signal subsequent to the first enable signal, and a first generating means for generating the first timing signal in response to the first enable signal. A self-testable integrated circuit device comprising: means and second generating means for generating the second timing signal in response to the second enable signal. 3. The self-testable integrated circuit device according to claim 1, wherein the assigning means is the first
Means for sending the first test pattern signal to the sequential circuit element only in the presence of the first timing signal in response to the test pattern signal and the first timing signal. Means for sequentially transferring a test pattern signal to the sequential circuit element and allocating the first test pattern signal to each sequential circuit element. 4. The self-testable integrated circuit device according to claim 1, wherein each of the sequential circuit elements is provided with a unique address, and the first test pattern generator is configured to output the mode signal. When the test mode is instructed by, the first test pattern is commonly sent to each sequential circuit element via the assigning means, and the address is designated by the first timing signal.
An integrated circuit device capable of self-inspection, wherein a first test pattern is stored in a predetermined sequential circuit element.