JPH0782074B2 - Logic verification device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device for a logic circuit, and more particularly to a logic circuit represented by a hardware description in a hardware description language of a function level and a gate level hardware. The present invention relates to a logic verification device for detecting a logic match or a logic mismatch between a logic circuit represented by a hardware description in a description language and the same logic circuit as described above.

[Conventional technology]

Based on the design specifications of one logic circuit, its function is described by using a hardware level description language, and further by using a gate level hardware description language. Conventionally, verification of agreement and inconsistency has been performed. In the past, as a device for performing this type of logic verification, (1) the hardware description related to the logic circuits of both levels was simulated by using sufficient test patterns, and the output values were compared. Method (eg, T. Sasaki et al. “Logic Design Verification Usin
g Automated Test Generation "1984.Int'l Test Confe
Rence.pp 88-94) adopted device.

(2) The function level hardware description is thoroughly converted into a Boolean expression (FB), and between the Boolean expression (GB) converted by the gate level hardware description, F = FB.
▼ ＋ ▲ ▼ ・ A device that adopts the method to prove GB≡0.

Is proposed.

[Problems to be Solved by the Invention]

The former logic verification device among the above-mentioned conventional devices exponentially increases the number of test patterns necessary for verifying the circuit as the number of input signals in the combinational circuit increases, as the circuit scale increases. However, there is a drawback that the simulation time of the circuit becomes long and the verification time significantly increases.

Further, the latter logic verification device converts all the hardware description at the function level into a Boolean expression, so that the obtained Boolean expression tends to be complicated and is equivalent to the Boolean expression corresponding to the gate level logic circuit. It becomes difficult to prove that. That is, logic verification tends to be difficult. In particular, if a high-level arithmetic function is written in a function-level hardware description, the logic verification often becomes difficult because it cannot be easily converted into a Boolean expression. It also has the drawback of consuming resources.

The present invention has solved such a conventional drawback,
The purpose is easy by dividing which of the logic verification by Boolean expression comparison and the logic verification by comparison simulation using a test pattern to be used for each partial circuit obtained by dividing the logic circuit. Another object of the present invention is to provide a logic verification device capable of verifying logic.

[Means for Solving the Problems]

In order to achieve the above object, the present invention has a hardware description written in a functional level hardware description language and a hardware description written in a gate level hardware description language for the same logic circuit. In this case, in the logic verification device for verifying the logic equivalence of the logic circuit of the function level and the logic circuit of the gate level expressed by both the description, the logic circuit of the function level and the logic circuit of the gate level are A dividing means for dividing into a plurality of partial circuits in the same range, a partial circuit of the functional level partial circuits obtained by the dividing means, which is easy to convert into a Boolean expression, and a corresponding gate level partial circuit, A first verification means for verifying logic by a comparison method, and conversion into a Boolean expression of a partial circuit of a functional level obtained by the dividing means may be provided. And a second verifying means for verifying logical in the method according to the partial circuit of the functional level does not easily compared simulation using a test pattern and a partial circuit of a gate level corresponding thereto.

[Action]

In the logic verification device of the present invention, the dividing means divides the functional level logic circuit and the gate level logic circuit into a plurality of partial circuits in the same range, and the first verifying means is obtained by the dividing means. Of the functional level sub-circuits, the partial circuit that is easy to convert into a Boolean expression and the corresponding gate-level sub-circuit are verified in logic by the Boolean expression comparison method,
The second logic verification means uses a test pattern for a functional level partial circuit which is not easy to convert into a Boolean expression among the functional level partial circuits obtained by the dividing means and a corresponding gate level partial circuit. The logic is verified by the method using the comparative simulation.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a logic verification device 1 according to an embodiment of the present invention describes a same logic circuit in a hardware description 21 written in a function-level hardware description language and a gate-level hardware description language. The hardware description 22 and the processed hardware description 22 are input and processed, and in the process, the functional level partial circuit group 23, the gate level partial circuit group 24, the partial circuit group 25 that is not easy to convert into a Boolean expression, and the easy conversion to a Boolean expression A sub-circuit group 26, a sub-circuit Boolean expression 27, a sub-circuit Boolean expression 28, and a test pattern 29 are sequentially generated and used, and the function-level hardware description 21 and the gate-level hardware description 22 are used. The logic equivalence of the logic circuit of the function level and the logic circuit of the gate level expressed by the above description is verified, and the judgment results 30 and 31 are output to the outside. As shown in FIG. 1, the logic verification device 1 includes a function level circuit dividing means 11, a gate level circuit dividing means 12, a function level classifying means 13, a gate level Boolean expression converting means 14, a function level Boolean expression converting means 15, It is composed of a Boolean comparison verification means 16, an automatic test pattern generation means 17 and a comparison simulation means 18. Each means performs the following processing.

○ Function level circuit dividing means 11 The logic circuit represented by the hardware description 21 of the function level is focused on the input signals and output signals of the logic circuit and the internal flip-flops, and each is described by the hardware description of the function level. It is divided into a plurality of expressed partial circuits and is output as a functional level partial circuit group 23. Various contents can be considered as the content of the division processing. For example, a predetermined output signal is headed and traced in the fan-in direction until the immediately preceding predetermined input signal or a predetermined flip-flop appears, and the traced range is set to one. A method of forming a partial circuit can be adopted.

○ Gate level circuit dividing means 12 The logic circuit represented by the gate level hardware description 22 is focused on the input signal, the output signal and the internal flip-flop of the logic circuit, and each is described by the gate level hardware description. It is divided into a plurality of partial circuits which are expressed and correspond one-to-one with the partial circuits obtained by the function level circuit dividing means 11 and output as a gate level partial circuit group 24. The gate-level hardware description 22 is created based on the specifications related to the same logic circuit as the function-level hardware description 21, and has the same input signal, output signal, and flip-flop. A method is adopted in which the same output signal as that of the circuit dividing means 11 is traced in the fan-in direction until the immediately preceding predetermined input signal or predetermined flip-flop appears, and the traced range is made into one partial circuit. This makes it possible to obtain a partial circuit in the same range as the functional level circuit dividing unit 11.

Function level classification means 13 Inputs a functional level subcircuit group 23 and classifies a plurality of subcircuits included in the subcircuit group into a subcircuit that can be easily converted into a Boolean expression and another subcircuit other than the subcircuit. Is output as a partial circuit group 26 that is easy to convert into a Boolean expression, and the latter is output as a partial circuit group 25 that is not easy to convert into a Boolean expression.

Gate level Boolean expression conversion means 14 Inputs the gate level partial circuit group 24 and converts all the partial circuits included therein into a Boolean expression to generate a partial circuit Boolean expression 27. Specifically, among the partial circuits included in the gate-level partial circuit group 24, a gate-level partial circuit corresponding to a functional-level partial circuit classified as easy to convert into a Boolean expression by the functional-level classifying unit 13, and a Boolean Converting the gate-level sub-circuits corresponding to the functional-level sub-circuits classified as not easy to expression to Boolean expressions, and outputting the former as sub-circuit Boolean expression 27b and the latter as sub-circuit Boolean expression 27a To do.

Function level Boolean expression conversion means 15 Inputs a partial circuit group 26 that can be easily converted into a Boolean expression, converts each partial circuit therein into a Boolean expression, and outputs it as a Boolean expression 28 of the partial circuit.

○ Boolean expression comparison verification means 16 Input the Boolean expression 28 of the partial circuit and the Boolean expression 27b of the partial circuit, and compare the structures of the Boolean expressions to see if the Boolean expressions of the corresponding partial circuits represent the same logic. Then, the result is output as the determination result 30.

Automatic test pattern generation means 17 A Boolean expression 27a of a partial circuit, that is, a logic of the partial circuit from a Boolean expression applied to a gate level partial circuit corresponding to a functional level partial circuit in the partial circuit group 25 that is not easily converted into a Boolean expression. A test pattern for verification is generated and this is output as a test pattern 29.

○ Comparison simulation means 18 By using the corresponding test pattern in the test pattern 29, the partial circuit of the functional level in the partial circuit group 25 that is not easily converted into the Boolean expression and the partial circuit corresponding to the converted into the Boolean expression 27a of the partial circuit By simulating a gate level partial circuit and comparing both simulation results, it is determined whether or not the logics of both partial circuits are the same, and the determination result 31 is output.

FIG. 2 shows an example of each of the functional level logic circuit represented by the functional level hardware description 21 and the gate level logic circuit represented by the gate level hardware description 22. The operation of this embodiment will be described below with reference to the example of FIG.

When the logic verification device 1 is activated by giving the hardware description 21 of the function level and the hardware description 22 of the gate level, first, the function level circuit dividing means 11 causes the hardware description 21 of the function level representing the entire logic circuit. Is input and analyzed to cut out partial circuits C1f and C2f as shown in FIG. 2 (a) separated by an input signal or an output signal or a flip-flop. That is, the circuit is divided into a plurality of partial circuits, and these are output as the functional level partial circuit group 23. In FIG. 2A, A, B, E and F are input signals or outputs from the flip-flops, and D and G are output signals or inputs to the flip-flops. Also partial circuit C1
The description of the function level of f is D = AB, and the partial circuit C2f
The functional level description of G is E = ADD.F. here,
"." Represents logical product and ".ADD." Represents binary addition.

On the other hand, the gate level circuit dividing means 12 inputs the gate level hardware description 22 and, for example, every time one partial circuit is cut out by the function level circuit dividing means 11, the corresponding gate level partial circuit is generated by the hardware. Description 22
Cut out from. That is, that is, as shown in FIG. 2B, from the hardware description 22 at the gate level, a partial circuit C1g separated by an input signal or an output signal or a flip-flop (this corresponds to the partial circuit C1f), The partial circuit C2g (this corresponds to the partial circuit C2f) is cut out and output as a gate-level partial circuit group 24. In addition, in FIG. 2B, each partial circuit C1g, C2g
Are respectively represented by AND gates and OR gates which are logic circuit expressions.

When the division processing in the function level circuit dividing means 11 is completed, the function level classifying means 13 is activated next, and the partial circuits included in the functional level partial circuit group 23 are easily converted into a Boolean expression. It is classified into a partial circuit group 25 that is not easily converted into an expression. In FIG. 2, since the partial circuit C1f can be easily converted into the Boolean expression D = A∧B, it is classified into the partial circuit group 26 side. Since the partial circuit C2f cannot be easily converted into the Boolean expression, the partial circuit group 25 side is included. being classified.

On the other hand, the gate-level Boolean expression conversion means 14 converts each partial circuit included in the gate-level partial circuit group 24 into a Boolean expression, and based on the classification result of the function level classification means 13, the partial circuit Boolean expression 27a. Then, the Boolean expression 27b of the partial circuit is divided and output. In FIG. 2, the partial circuit C1g is d = a∧
C2g is converted to b on the Boolean expression 27b side and g = e∧∨
It is converted into ∧f and output to the Boolean expression 27a side.

When the classification processing of the function level classification means 13 is completed, the function level Boolean expression conversion means 15 and the automatic test pattern generation means 17 are activated.

When the function level Boolean expression conversion means 15 is activated, it converts the partial circuits of each function level included in the partial circuit group 26 that can be easily converted into a Boolean expression into a Boolean expression, and the Boolean expression of the partial circuit is converted.
Generates 28. Then, the Boolean expression comparison verification means 16 is activated. In addition, the activated automatic test pattern generation means 17
After the conversion process of the gate level Boolean expression conversion means 14 is completed, the Boolean expression 27a of the partial circuit is input to generate a test pattern (test input pattern) that activates all logics by using a D-algorithm or the like. To do. For example, in the partial circuit C2g in FIG. 2, (e, f) = (0,0), (0,1), (1,
Four patterns 0) and (1, 1) are generated and output to the test pattern 29 as test patterns for the partial circuits. Then, after the test pattern generation processing is completed, the comparison simulation means 18 is activated.

When the Boolean expression comparison / verification means 16 is activated, the Boolean expression of the partial circuit of each functional level included in the Boolean expression 28 of the partial circuit and the Boolean expression of the corresponding partial circuit of the gate level included in the Boolean expression 27b of the partial circuit. Compare with the expression. For example, in the case of the partial circuits C1f and C1g shown in FIG. 2, this comparison is D∧∨
It is to check whether ∧d is always 0. The above formula is And A = a and B = b, so when expanded, (A∧B
∧∨A∧B∧) ∨ (∧A∧B∨∧A∧B), and A∧ = 0, B∧ = 0, so (0∧B∨0∧A) ∨
(0∧B∨0∧A), and the value of this Boolean expression is 0. If this value is 0, it is determined to be a logical match, and if it is another value or a Boolean expression, it is determined to be a logical mismatch and the determination result
Outputs 30.

On the other hand, the comparison simulation means 18 includes a functional level partial circuit included in the partial circuit group 25 which is not easily converted into a Boolean expression, and a gate level partial circuit represented by a Boolean expression corresponding to the partial circuit in the Boolean expression 27a. On the other hand, a simulation is performed using the corresponding test pattern in the test pattern 29, and both simulation results are compared,
The determination result 31 is output based on the result. For example, the above test pattern (e, f) = (0,0), (0,1), (1,
0) and (1,1), the partial circuit C2f and the partial circuit C of FIG. 2 are used.
When both 2g are simulated, the simulation result of the partial circuit C2f is G = (0), (1), (1),
(0) (excluding carry), and the simulation result of the partial circuit C2g is g = (0), (1), (1),
Since it is (0) and both match, it is determined that the logics of the partial circuit C2f and the partial circuit C2g are the same. If the output values of G and g are different, it is determined that the logics of both partial circuits are not equal.

〔The invention's effect〕

As described above, in the logic verification device of the present invention, the logic circuit based on the hardware description of the function level and the logic circuit based on the hardware description of the gate level are divided into a plurality of partial circuits in the same range, and Of the partial circuits, the partial circuits that are easy to convert into Boolean expressions and the corresponding gate-level partial circuits are the logical level verification method by the comparison method of Boolean expressions, and the partial circuits of the functional level that are not easy to convert into Boolean expressions. The following effects can be obtained by verifying the logic of the corresponding gate-level partial circuit by a method of comparison simulation using a test pattern.

(1) When all the logic circuits of the function level are converted into Boolean expressions, the logic verification becomes difficult when it is difficult to convert to Boolean expressions, or a lot of machine resources are spent on conversion to Boolean expressions. Although it is easy, in the present invention, since the logic is verified by the comparison simulation for the partial circuit which is not easily converted into the Boolean expression, such a problem is solved.

(2) In the logic verification only by the comparative simulation, the number of test patterns increases exponentially as the circuit scale increases, but in the present invention, the functional level partial circuit that is not easily converted into the Boolean expression and the partial circuit corresponding thereto are dealt with. Since the method based on the comparison simulation is used only for verifying the logic with the gate-level partial circuit, it is possible to prevent an increase in the number of test patterns and shorten the time required for verification.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part of one embodiment of the present invention, and FIG. 2 is a functional level logic circuit represented by a functional level hardware description 21 and a gate represented by a gate level hardware description 22. It is a figure which shows the example with a logic circuit of a level. In the figure, 1 ... Logic verification device 11 ... Function level circuit dividing means 12 ... Gate level circuit dividing means 13 ... Function level classifying means 14 ... Gate level Boolean conversion means 15 ... Function level Boolean conversion means 16 …… Boolean comparison verification means 17 …… Automatic test pattern generation means 18 …… Comparison simulation means 21 …… Function level hardware description 22 …… Gate level hardware description 23 …… Function level subcircuit group 24 …… Gate-level subcircuits 25 …… Subcircuits that are not easily converted to Boolean expressions 26 …… Subcircuits that are easily converted to gate expressions 27 …… Subcircuit Boolean expressions 28 …… Subcircuit Boolean expressions 29… … Test pattern 30,31 …… Judgment result

Claims (1)

[Claims] 1. When there is a hardware description written in a function-level hardware description language and a hardware description written in a gate-level hardware description language for the same logic circuit, both of them are described. In a logic verification device for verifying logic equivalence between a logic circuit of a functional level and a logic circuit of a gate level, a logic circuit of the functional level and a logic circuit of the gate level have a plurality of partial circuits in the same range. And a gate level partial circuit corresponding to the partial circuit which is easily converted into a Boolean expression among the partial circuits of the function level obtained by the dividing means and the logic verification is performed by a Boolean comparison method. A first verifying unit to perform, and a functional level unit that is not easily converted into a Boolean expression among functional level partial circuits obtained by the dividing unit. Logic verification apparatus characterized by comprising a second verifying means for verifying logical in the method according to the circuit and compared simulation using a test pattern and a partial circuit of a gate level corresponding thereto.