JPH0782079B2 - Test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device, and more particularly to a test circuit for switching an internal circuit to a test mode in a test circuit of a peripheral device including a semiconductor integrated circuit.

[Conventional technology]

Conventionally, when switching the internal circuit to the test mode, the first
As for the configuration, one extra pin is provided for testing,
A signal is input to the pin (hereinafter referred to as a test pin) when the user wants to switch to the test mode. In the second configuration, an inverter having a threshold voltage outside the normal operating voltage range (hereinafter referred to as an inverter having a different operating voltage) is connected in parallel to one of the signal input parts, and when it is desired to switch to the test mode, The configuration is such that the input voltage is raised or lowered to a voltage that is not used in normal operation.

[Problems to be Solved by the Invention] The former of the above-described conventional configurations has a drawback in that it requires pins that are not used at all in normal operation.

In addition, the latter configuration has a drawback that the process of making inverters having different operating voltages is troublesome.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a test apparatus which does not require a special inverter without increasing the number of pins.

[Means for solving problems]

According to the configuration of the present invention, a plurality of signal lines for exchanging data are connected to the internal circuit via the input / output port circuit, and the input / output port circuit is controlled by the output of the decoder to which the plurality of control signal lines are connected. In the test device, while controlling the input / output port so that the data transfer is not performed when the logic levels input to the plurality of control signal lines are in a combination that cannot be in a normal operation state, The decoder is provided with a function of generating a clock signal, and the input / output port circuit is provided with a plurality of latches that use the clock signal as a clock input and each of the plurality of signal lines as a data input, and output of the plurality of latches. It is characterized in that means for combining the signals to obtain a test mode signal is provided.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit showing a test apparatus according to an embodiment of the present invention. In the figure, the contents of the input / output port circuits 24, 25, and 26 of each block surrounded by broken lines are the same as the circuit diagram shown in the input / output port circuit 24 of the uppermost block, and the number of blocks is the data. Is equal to the number of signal lines for sending and receiving. First
In the figure, only the input / output port circuit 24 of the uppermost block is shown.

Input signal to the data read signal line 1 (hereinafter ▲ ▼
Is input to the AND gates 11 and 13 via the inverter 7. The input signal (hereinafter referred to as ▲ ▼) to the data write signal line 2 is passed through the inverter 8 and the AND gate 1
Input to 2,13. An input signal (hereinafter referred to as ▲ ▼) to the chip enable signal line 3 is transmitted via the inverter 9.
It is input to the AND gates 11 and 12 and the inverter 10, and the output of the inverter 10 is input to the AND gate 13. Inverter
A decoder is composed of 7,8,9,10 and AND gates 11,12,13. When the output of the AND gate 11 is the logic level of "0", the buffer 14 is in the high impedance state and the buffer 14
The reading of data from the signal line 18 to the signal line 4 via the is stopped. Further, when the output of the AND gate 12 is the logic level of "0", the buffer 15 is in a high impedance state, and the writing of data from the signal line 4 to the signal line 18 via the buffer 15 is stopped. The signal lines 4 and 18 are signal lines for exchanging data with the input / output port circuit 24.
Is input / output port circuit 25, signal lines 6 and 22 are input / output port circuit 2
6 is a signal line for exchanging data. Also, AND gate 13
The output of flip-flop 17 (hereinafter referred to as F / F17)
It is used as a clock signal. The data of the signal line 4 is read by the clock signal and output to the signal line 19 as an output signal of the F / F 17 (hereinafter referred to as a test signal). The blocks 25 and 26 read the data on the signal lines 5 and 6 by the clock and output them to the signal lines 21 and 23, respectively. Reset signal 16 is a system reset signal.

Next, the operation of this embodiment will be described.

The logic levels of the three control signals ▲ ▼, ▲ ▼, ▲ ▼ and the state of the circuit are shown in FIG. The operation of the circuit in the cases (1) to (4) of FIG. 2 will be described in order.

When the control signals ▲ ▼, ▲ ▼, and ▲ ▼ are “0”, “1”, and “0”, the outputs of the inverters 7, 8, 9, and 10 are “1” and “0”, respectively. , “1”, “0” logic levels, and the outputs of the AND gates 11, 12, 13 become “1”, “0”, “0” logic levels, respectively. Therefore,
No test signal is output from F / F17 and the internal circuit does not enter the test mode. Further, since the buffer 15 is in a high impedance state, it is in a data read state.

When the control signals ▲ ▼, ▲ ▼, and ▲ ▼ are “1”, “0”, and “0” in the item (2), the outputs of the inverters 7, 8, 9, and 10 are “0” and “1”, respectively. , “1”, “0” logic levels, and the outputs of the AND gates 11, 12, 13 become “0”, “1”, “0” logic levels, respectively. Therefore,
No test signal is output from F / F17 and the internal circuit does not enter the test mode. Further, since the buffer 14 is in the high impedance state, it is in the data writing state.

When the control signals ▲ ▼, ▲ ▼, and ▲ ▼ are "1", "1", and "0" in the same way as in the above (1) and (2), AND The outputs of the gates 11, 12, and 13 are logic levels of "0", "0", and "0", respectively. Therefore, the test signal is not output from the F / F17 and the internal circuit does not enter the test mode. Also, buffers 14,15
Since both are in a high impedance state, data reading / writing is stopped. The above items (1) to (3) are combinations of logic levels of control signals that exist when the circuit is operating normally.

When the control signals ▲ ▼, ▲ ▼, and ▲ ▼ are “0”, “0”, and “1”, the outputs of the inverters 7, 8, 9, and 10 are “1” and “1”, respectively. , “0”, “1” logic levels, and the outputs of the AND gates 11, 12 become “0”, “0” logic levels, respectively, so that the buffers 14, 1
Both 5 are in the high impedance state, and reading / writing of data is stopped. Further, since the output of the AND gate 13 becomes the logic level of "1", the data on the signal line 4 is read into the F / F 17, and the F / F 17 outputs the data as a test signal.

As described above, according to the present embodiment, it is possible to generate the test signal and switch the internal circuit to the test mode by the combination of the logic levels of the control signals that do not exist in the normal operation state of the circuit.

The circuit operation in the input / output port circuits 25 and 26 surrounded by the broken line is the same as that described above.

〔The invention's effect〕

As described above, according to the present invention, the internal circuits are configured by combining the logic levels input to the plurality of control signal lines with respect to the signal line for exchanging data such that the normal operation cannot be performed. It is possible to switch to the test mode, so there is no need to provide test pins as in the past, and the pins that were used as test pins in the past can be used for other functions, which limits the number of pins. In an integrated circuit that is used, it is extremely effective, and it is not necessary to make inverters having different operating voltages, and it is possible to obtain effects such as facilitating manufacturing in terms of process. In particular, the first embodiment of the present invention
Referring to the figure, in order to obtain the test mode signal, it is sufficient to prepare the inverter 10, the AND gate 13, and the flip-flop 17, which has the effect of adding an extremely small number of elements.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a test apparatus according to an embodiment of the present invention,
FIG. 2 is a diagram showing an operating state of the test apparatus of FIG. In the figure, 1 ... data read signal line, 2 ... data write signal line, 3 ... chip enable signal line, 4,5,6,18,2
0,22 …… Signal line for sending and receiving data, 7,8,9,10 …… Inverter, 11,12,13 …… AND gate, 14,15 …… Buffer,
16 …… Reset signal, 17 …… Flip flop (F /
F), 19,21,23 …… Test signal line, 24,25,26 …… I / O port circuit.

Claims (1)

[Claims] 1. A test for controlling a plurality of signal lines for exchanging data, which are connected to an internal circuit via an input / output port circuit, and which controls the input / output port circuit by outputs of a decoder to which a plurality of control signal lines are connected. In the device, the input / output port is controlled so that the data transfer is not performed when the logic levels input to the plurality of control signal lines are in a combination that cannot be in a normal operation state, and a clock is provided. The decoder is provided with a function of generating a signal, and the input / output port circuit is provided with a plurality of latches that use the clock signal as a clock input and each of the plurality of signal lines as a data input, and output signals of the plurality of latches. And a means for obtaining a test mode signal by combining the above.