JPH0782309B2 - Synchronous control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a character / character capable of displaying characters and figures in an overlapping manner.
The present invention relates to a synchronous control circuit suitable for synchronously operating a plurality of controlled systems having different operating speeds such as a graphic display device.

[Conventional technology]

Corresponding 1-bit information stored in the memory to 1 pixel,
A graphic screen displaying a graphic as a group of pixels and a character corresponding to a code (for example, a character code defined in JIS C 6226-1983), and the code forming a character by a character generator. In a character / graphics display device that is adapted to be displayed by superimposing it on a character screen on which characters are displayed after being converted into a collection of characters, a display timing control circuit (hereinafter referred to as CRTC) for controlling the display of the graphic screen,
A CRTC for controlling the display of the character screen is provided, and the graphic and the character may be displayed in an overlapping manner by operating both in sync.

Since the processing word length of a drawing processor or a central processing unit (hereinafter referred to as CPU) for controlling the drawing of a graphic screen is often configured in units of 8 to 16 bits, the display control of the graphic screen is also 8 pixels, or It is often done in units of 16 pixels.

On the other hand, in character screen display control, for example, JIS
In order to display the 24-dot character form specified in C 6234-1983, if the width of a character is 24 pixels and the space between characters is 4 pixels, 28 pixels for full-width characters and 14 pixels for half-width characters are used. Must be a unit. As a result, two CRTCs, one that controls the graphic screen and one that controls the character screen
And it is necessary to drive the two CRTCs using clocks with different frequencies.

FIG. 4 is a block diagram showing a general configuration of the display device as described above. 1 is a CPU for writing graphics and character codes, 2 is a CRTC for controlling display of a graphic screen, and 3 is a character. CRTC which controls the display of the screen, 4 is an oscillation circuit which generates a dot clock C corresponding to the display time of one pixel, and 5 is a clock Cn which corresponds to the display time corresponding to the width of one character (for example, the width of one character is If there are 14 pixels, a frequency dividing circuit for generating a clock having a frequency 1/14 of the dot clock C, 6 is a clock Cm corresponding to the display time corresponding to the number of bits of 1 word of the CPU 1 (for example, 1 If the word is 16 bits, a frequency divider circuit that generates a clock having a frequency 1/16 that of the dot clock C), 7 and 8 are selectors for switching between the address signal generated by the CPU 1 and 9 is a character code. Text VRAM, 10 is the display screen A graphic VRAM, 11 for displaying a graphic by storing the bit information indicating the brightness of the pixel above, and the corresponding character is constructed from the character code read from the text VRAM 9 under the control of CRTC3. A charactor generator (hereinafter referred to as CG), 12 that generates a pixel group that performs CG for the graphic information read from the graphic VRAM 10 under the control of CRTC2.
Delay circuit that delays by the time required to read 11, 13,
Reference numeral 14 is a parallel-serial conversion circuit that converts the output of the CG11 and graphic VRAM 10 in parallel and serially, and 15 is capable of overlapping display by switching the pixels representing the characters output from the parallel-serial conversion circuits 13 and 14 and the pixels representing the figure. Overlay control circuit, 16 is C
It is a display device such as RT.

In the figure, CRTC3 is supplied with horizontal and vertical synchronizing signals from the outside, and the character code is read from the text VRAM 9 in accordance with these synchronizing signals. When the frequency dividing ratio of the frequency dividing circuit 5 is n and the frequency dividing ratio of the frequency dividing circuit 6 is m, when the aforementioned 24-dot character display is performed, for example, m = 16 and n = 14 are set. Therefore, the cycle in which graphic information is read from the graphic VRAM 10 by CRTC2 and the text VRAM9 by CRTC3
Therefore, there will be a deviation from the period in which the character code is read. However, when CRTC2 and 3 are synchronized at the time of starting to display one screen on the CRT16, that is, at the same time when the one screen display by CRTC2 starts, the C
When the display of one screen by RTC3 is started, it is possible to display it in a superimposed manner.

This will be described with reference to FIG. FIG. 5 (a) shows an n division clock supplied to the CRTC3 from the division circuit 5 and a character output by the CG11 from the character code read by the CRTC3 based on the n division clock. It shows the relationship. Here, one character is displayed in one cycle of the clock divided by n. Further, FIG. 5B shows the relationship between the m division clock supplied from the frequency division circuit 6 to the CRTC2 and the figure read from the graphics VRAM 10 by the CRTC2 based on this m division clock. . Further, FIG. 5 (c) shows the phase relationship between the n-divided clock and the m-divided clock and how the characters and figures are superimposed.

As shown in FIG. 5 (c), if the display start time of the character and the display start time of the graphic match, the superimposed display of the character and the graphic is performed from the display start time. On the contrary,
If there is a deviation between the display start time of the character and the display start of the graphic, the display of the character and the graphic display will be misaligned at the start of the overlay display.

This is shown in FIG. 6A shows the case where the character display start time is earlier than the graphic display start time, and FIG. 6B shows the case where the character display start time is later than the graphic display start time. In FIG. 4, since the display timing on the CRT 16 is determined by the CRTC2 that controls the graphic display, as shown in FIG. 6 (a), when the character display starts too early, Part of the left side of the first character may not be displayed, and as shown in FIG. 6 (b), when the character display starts too late, an unnecessary space is left on the left side of the first character. May occur. Since the display period of one screen is constant, when displayed as shown in FIG. 6 (b), even if the first character is displayed correctly, the right part of the last character of one line is missing. Will be displayed.

In order to solve the problems described above, it is necessary to synchronize the m division clock and the n division clock at the display start time.

Conventionally, in order to realize this, immediately before the start of display, m
The frequency dividing circuit 6 for generating the frequency dividing clock and the frequency dividing circuit 5 for generating the n frequency dividing clock are reset in synchronism with each other.

FIG. 7 is a block diagram showing an example of a synchronization control circuit in a conventional display device based on the above idea.
Is a pulse generating circuit, and the parts corresponding to those in FIG. Further, FIG. 8 is a timing chart showing signals of respective parts in FIG.

The operation of the synchronization control in this conventional example will be described below.

CRTC2 generates a sync signal Sy before the start of display. This synchronization signal Sy is the CRTC3, the pulse generation circuit 17, and the CRT16 (fourth
Supplied). The sync signal Sy causes the CRTC 3 to start displaying the next screen, and the pulse generation circuit 17 generates a reset signal Rs having a predetermined time width after a predetermined time. This reset signal Rs is supplied to the frequency dividing circuits 5 and 6, and the frequency dividing circuits 5 and 6 are
Is reset and the frequency division operation of the dot clock C from the oscillation circuit 4 is performed from the initial point. As a result, the phases of the m-divided clock Cm and the n-divided clock Cn can be matched at the start of display.

[Problems to be solved by the invention]

In the prior art as described above, if there is a phase difference between the m-divided clock Cm and the n-divided clock Cn at the time when the reset signal Rs is generated, the frequency dividing operation is interrupted by the reset signal Rs. As a result, there is a problem that an abnormally short division clock is generated from the CRTCs 5 and 6, which may cause a malfunction.

The object of the present invention is to achieve stable operation of CRTC while maintaining two CR
It is to provide a synchronization control circuit that enables synchronization between TCs.

[Means for solving problems]

In order to achieve the above object, the present invention provides that a specific CRTC outputs a synchronization signal, and a pulse generation circuit forms a reset signal of a predetermined width, and the reset signal and the specific CR signal.
The output signal of the frequency dividing circuit that supplies the frequency dividing clock to CRTC other than TC is supplied to the gate circuit, and the reset signal of the frequency dividing circuit is controlled by the output signal of the gate circuit.

[Action]

As for the output signal of the gate circuit, when the frequency reset circuit resets after the reset signal is supplied, the frequency divider circuit is held in the reset state until the reset signal is not supplied. Therefore, the output signal of each frequency dividing circuit can be synchronized with the synchronizing signal in a predetermined phase relationship, and no short pulse is output from each frequency dividing circuit.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronous control circuit according to the present invention, in which 18 is a gate circuit, 19 is a reset timing circuit, and the same symbols are given to the portions corresponding to FIGS. 4 and 7. I am wearing it. Further, FIG. 2 is a timing chart showing signals of respective parts in FIG.

In FIG. 1, the synchronization signal Sy output from CRTC2 is CRTC.
3, supplied to the pulse generator 17 and CRT 16 (FIG. 4). The CRTC 3 starts the display operation of the next screen by the sync signal Sy, and the pulse generation circuit 17 generates the reset signal Rs of a constant width in synchronization with the sync signal Sy. This reset signal Rs
Is supplied to one input of the gate circuit 18, and the other input thereof is supplied with the output of the frequency dividing circuit 5, that is, the n frequency dividing clock Cn which is the operation clock of the CRTC3. The frequency dividing circuit 5 is caused to perform the reset operation only during the period of "H" and the n frequency dividing clock Cn from the frequency dividing circuit 5 is at the logic level "H". Frequency divider circuit 5
Keeps outputting the logic level "H" during the reset operation. Therefore, after the reset operation is started, the reset signal Rs
The output level is maintained at the logic level "H" until the reset is released until is released. Therefore, the reset signal Rs
Is set so as to be synchronized with the phase of the m-divided clock Cm output by the frequency dividing circuit 6, the n-frequency-divided clock Cn output by the frequency dividing circuit 5 and the frequency-divided circuit 6 output. m
It is possible to synchronize the phase with the division clock Cm.

FIG. 2 shows an example in which the n-divided clock Cn and the m-divided clock Cm fall at the same time when the reset signal Rs is released. However, by changing the width of the reset signal Rs, the n-divided clock is divided. The initial phases of the clock Cn and the clock m C divided by m can be arbitrarily set. That is, the reset signal
If the width of Rs is increased, the phase of the n-divided clock Cn is delayed with respect to the m-divided clock Cm. Conversely, if the width of the reset signal Rs is shortened, the phase of the n-divided clock Cn is divided by m. Black
You will proceed to Cm. By using this, it is possible to adjust the display position of the character and the display position of the figure in pixel units.

In the embodiment shown in FIG. 1 described above, a short pulse is not generated in the output of the frequency dividing circuit during the synchronous operation, and therefore the CR
It is possible to operate the TC stably. In addition, the number of parts required for this embodiment is small, and it can be implemented at low cost.

FIG. 3 is a block diagram showing another embodiment of the synchronization control circuit according to the present invention, in which 20 is a pulse width setting circuit rewritable by the CPU 1, and the portions corresponding to those in FIG. Is attached.

In FIG. 3, the pulse width setting circuit 20 controls the width of the reset signal Rs generated by the pulse generation circuit 17, and the CRTC2,3
Frequency dividing clock Cm generated by the frequency dividing circuit 6 during synchronous operation of
The initial phase of the n division clock Cn generated by the division circuit 5 is determined.

In this embodiment, the phase relationship between the n-divided clock Cn and the m-divided clock Cm at the start of display can be changed by the setting of the pulse width setting circuit 20. As a result, FIG. 6 (a), (b) It is possible to intentionally generate and adjust the deviation between the character display and the graphic display as shown in. Since CRTC2 controls the graphic display and generates the synchronization signal Sy, the deviation between the character display and the graphic display will be displayed with the display position of the character left and right relative to the entire display screen. . Since the shift amount of the display position of the character can be adjusted in the unit of one pixel, a smooth horizontal scroll display can be realized as compared with the horizontal scroll in the character unit which is usually performed.

〔The invention's effect〕

As described above, according to the present invention, when a plurality of CRTCs are synchronously operated at different frequencies, the display start position of each CRTC can be adjusted without causing instability of the operation, and it is necessary. The number of new parts is small, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization control circuit according to the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a block diagram showing another embodiment of the synchronization control circuit according to the present invention. FIG. 4 is a block diagram showing a general overlay display device, and FIGS. 5 and 6 are shown in FIG.
FIG. 7 is an explanatory diagram showing the relationship between the phase of the CRTC clock and the state of superimposed display, FIG. 7 is a block diagram showing an example of a conventional synchronous control circuit, and FIG. 8 is a timing chart showing its operation. 2,3 ...... Timing control circuit 4 ...... Oscillation circuit, 5, 6 ...... Dividing circuit 17 ...... Pulse generation circuit, 18 ...... Gate circuit 19 ...... Reset timing generation circuit 20 ...... Pulse width setting circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshiaki Kitazume Yoshiaki Kitazume 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd. Microelectronics Equipment Development Laboratory, Hitachi, Ltd. (72) Shigeru Murasaki 7 Narashino Higashi-Narashino, Chiba Prefecture 1-1-1, Narashino Plant, Hitachi, Ltd. (56) References JP-A-60-229094 (JP, A) JP-A-60-43691 (JP, A)

Claims (1)

[Claims] 1. A plurality of frequency dividing circuits having different frequency dividing ratios and dividing the same reference clock, and an output of the corresponding frequency dividing circuit provided for each frequency dividing circuit as an input clock. , A plurality of timing control circuits for controlling display timings of different screens, one of the timing control circuits is set as a specific timing control circuit, and the specific timing control circuit is phase-synchronized with an input clock. The generated synchronization signal is generated and supplied to other timing control circuits, and all the timing control circuits based on the synchronization signal have different screen display control systems provided corresponding to the input clock. In a synchronous control circuit that operates at mutually different operating speeds and in synchronization with each other, a reset is performed for each frequency dividing circuit corresponding to the other timing control circuit. A reset timing circuit, the reset timing circuit includes a pulse generation circuit that receives the synchronization signal as an input, forms a reset signal having a predetermined width in response to the synchronization signal, and outputs the reset signal; and a frequency divider circuit that corresponds to the reset signal. A synchronous control circuit comprising: a gate circuit having an output signal as an input, and resetting a corresponding frequency dividing circuit according to the output signal of the gate circuit.