JPH0782316B2 - CRT controller - Google Patents

Description

The present invention relates to a CRT controller, and more particularly to a CRT controller relating to arbitration of access to an image memory of a display control circuit and a drawing control circuit.

[Conventional technology]

Conventionally, this type of CRT controller is generally a CRT controller having both a display control function and a drawing control function, and the display control circuit and the drawing control circuit are generally configured to operate in synchronization with a single clock. Met.

However, this CRT controller increases the drawing speed as one indicator of its performance, and the drawing speed depends on the drawable time within one frame and the operating frequency, and various measures can be considered to improve the drawing speed. Has been. With the advent of dual port memory for images, it has been greatly improved in terms of the increase in the drawable time, and also in terms of speeding up the drawing system clock, the display control circuit and the drawing control circuit are operated asynchronously by independent clocks. The system is no longer restricted by the display system clock, which is determined by the display specifications.

In the above-mentioned technical tendency, arbitration of access for display and access for drawing to the image memory is performed uniquely in both the display / drawing synchronous clock system and the asynchronous clock system. It was

[Problems to be solved by the invention]

In the conventional CRT controller, when the display control circuit and the drawing control circuit operate asynchronously, it is necessary to synchronize the wait signal sent from the display control circuit to the drawing control circuit in order to prevent contention of access to the image memory. The overhead for synchronization reduces the period during which the drawing control circuit can access the image memory. As an advantage in the asynchronous case, the operation clock of the drawing control circuit can be optimally set according to the performance (access time etc.) of the image memory.

On the other hand, when the display control circuit and the drawing control circuit operate in synchronization with each other, the synchronization of the wait signal for preventing contention of access to the image memory is unnecessary and there is no overhead. However, in this case, it is necessary to synchronize the clock of the drawing control circuit with the clock of the display control circuit, which has a high priority for accessing the image memory, and use it without being able to bring out the performance of the image memory sufficiently in the access for drawing. May have to be.

In the access control of this kind of image memory, it is uncertain as to whether a higher drawing performance can be obtained by the synchronous method or the asynchronous method. For example, when the performance of the image memory is sufficiently high with respect to the display control clock, even if it is asynchronous with respect to the display control clock, it is possible to obtain higher rendering performance by setting the drawing control clock according to the performance of the image memory. This is because the effect of increasing the number of image accesses to the image memory by increasing the frequency of the drawing control clock is greater than the effect of decreasing the drawable period due to asynchronous overhead. On the contrary, if the performance of the image memory is suitable for the display control clock, it is possible to obtain higher drawing performance by synchronizing the drawing control clock with the display control clock of a lower frequency, even if there is some margin to access the image memory. To be This is because the effect of increasing the drawable period by synchronization is greater than the effect of decreasing the number of drawing accesses to the image memory due to the lowering of the frequency of the drawing control clock.

As described above, in the conventional technology, the superiority or inferiority of the drawing performance in the synchronous method and the drawing performance in the asynchronous method is the display control clock determined by the display specification of the display,
There is a problem that the best drawing performance is not always obtained because it depends on the performance of the image memory used.

According to the invention of the present application, the access from the display control circuit to the image memory and the access from the drawing control circuit are not fixed in the synchronous method and the asynchronous method, and in any method, access competition between the display control circuit and the drawing control circuit occurs. The conventional problem is solved by providing a control circuit for realizing the prevention processing with a minimum overhead.

[Means for solving problems]

CRT that controls display and drawing for image memory
In the controller, based on the control signal of the display control circuit generated for accessing the image memory for display or refreshing the image memory, it is activated four cycles before the display control clock and deactivated at the same timing. A control circuit that generates a first signal and a second signal that is activated three cycles before and deactivated two cycles before, and a mode in which the relationship between the display control and the drawing control is asynchronous operation or synchronous operation. And a multiplexer for selecting the first signal in the case of asynchronous operation and a second signal in the previous period in the case of synchronous operation based on the mode setting means, and an output of the multiplexer. A synchronizing circuit that synchronizes with the drawing control clock and sends it as a wait signal to the drawing control circuit, and the drawing control circuit outputs the synchronizing circuit. When the image memory access execution cycle for drawing is not entered in response to the wait signal, the availability of the image memory access for drawing is determined. Image memory access for
In the latter half of the access cycle, it is determined whether the next image memory can be accessed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, and FIGS. 2 and 3 show an example of operation timing of the first embodiment. In FIG. 1, the first embodiment is a CRT controller which has a display control function and a drawing control function of an image memory and enables the display control clock and the drawing control clock to be asynchronous, and a display control circuit. It has a 100 and a drawing control circuit 110. The display control circuit 100 has a display control function of an image memory, and the drawing control circuit 110 has a drawing control function of an image memory. These circuits are connected via a control circuit 120, a multiplexer 130, and a synchronization circuit 109. Further, the multiplexer 130 is connected to the register 108 having the information on whether the display control circuit 100 and the drawing control circuit 110 are the synchronous clock or the asynchronous clock.

The control circuit 120 includes four 1-clock delay circuits 102 to 105.
And consists of two AND gates 106 and 107,
The delay circuits 102 to 105 are connected in series and are connected so as to be supplied with clock signals φ _s1 and φ _s2 , respectively. The delay circuit 102 is a clock signal for the display control circuit 100.
BLK is connected to be supplied. AND gate 1
06 is supplied with the signal input to the delay circuit 102, that is, the signal BLK of the display control circuit 100 and the output signal of the delay circuit 105, sends out the timing signal 106a, and the AND gate 10
Reference numeral 7 is configured to be supplied with the output signals of the delay circuits 102 and 103 and to output the timing signal 107a.

The multiplexer 130 comprises two OR gates 131 and 132, one inverter 133 and an AND gate 134,
The OR gate 131 has one end connected to the AND gate 106, and the other end connected to the register 108 via the inverter 133, and the OR gate 131 has one end connected to the AND gate 107 and the other end connected to the register 108. The AND gate 134 is connected to the OR gates 131 and 132 on the input side and the synchronizing circuit 109 on the output side.
It is connected to the. The synchronizing circuit 109 is a one-clock delay circuit, to which clock signals φ ₁ and φ ₂ are supplied.
It is connected to supply the IT signal to the drawing control circuit 110.

Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the display control circuit is used for continuously displaying the image memory during the display period (when BLANK in FIG. 3 is Low).
As shown in FIG. 2, the drawing control circuit 110 operates in synchronism with the clock φ, and first, there is a drawing determination cycle of 1 clock. If it is determined that drawing is possible, it is premised that drawing execution (access of the image memory for drawing) is completed in the following two clocks. Generally, the drawing clock φ is restricted only by the speed of the image memory as an external factor, and the display clock φ _s is restricted by the display specifications in addition to the speed of the image memory. Inevitably, the relationship φ _s ≦ φ holds.

As shown in FIG. 3, the BLK signal output from the display control circuit 100 is a BLANK signal that is four clocks ahead of the clock φ _s . AND gate based on BLK signal 106,107
Which of the two systems of timing signals 106a and 107a is generated and which signal is transmitted to the next stage is selected by the output of the register 108. The register 108 indicates the relationship between φ and φ _s , and outputs High when φ ≠ φ _s and Low when φ = φ _s . When φ ≠ φ _s , the signal 106a of the AND gate 106
Is selected, and is synchronized with φ by the synchronizing circuit 109 to become the WAIT timing signal shown in FIG. The change point of the WAIT state is at least within the range a due to the relationship between φ and φ _s . When the drawing control clock φ and the display control clock φs are synchronized and are the same clock, the output of the register 108 is Low and the multiplexer 130 (OR gate 132,
The AND gate 134) selects the output signal 107a of the AND gate 107. Note that the signal 107a is a signal in which the falling edge of the BLANK signal is delayed by 2 clocks and the rising edge of the BLANK signal is delayed by 2 clocks with respect to the signal BLK which is 4 clocks ahead of the BLANK signal, that is, the falling edge is 3 times.
This is a signal in which the rising edge of the clock is two clocks ahead. Since the synchronizing circuit 109 at this time is φ = φs, it functions as a simple 1-clock delay circuit, and the WAIT signal is a signal obtained by delaying the signal 107a by 1 clock, that is, BLANK.
The falling edge of the signal is 2 clocks and the rising edge is 1 clock in advance.
Timing signal.

The drawing control circuit 110 makes a drawing judgment based on the WAIT signal. If WAIT is High during the drawing judgment cycle, the drawing control circuit 110 accesses the image memory for 2 clocks at the next φ. Therefore, if the timing of the WAIT signal is as shown in FIG. 3 with respect to the display period, the display cycle and the drawing cycle are required to access the image memory regardless of φ = φ _s and φ ≠ φ _s. Guaranteed to be completely non-overlapping.

FIG. 4 shows a second embodiment of the present invention, and FIG. 5 shows an example of its operation timing.

The second embodiment uses a dual port DR as an image memory.
It is applied to a CRT controller that has a display control function that supports AM, and a function that refreshes an image memory that uses DRAM in the horizontal synchronization period (HS), and operates the drawing control circuit and clock. The relationship between φ and φ _s is the same as in the first embodiment.

In the case of the second embodiment, the factors that make the drawing control circuit 410 inaccessible to the image memory are when the image memory is in the refresh period and when the dual port is used.
This is during the DRAM internal data transfer cycle (when the DT signal in FIG. 5 is active).

In FIG. 4, the second embodiment has a display control circuit 400 and a drawing control circuit 410 for controlling the image memory. The display control circuit 400 and the drawing control circuit 410 are connected via a control circuit 420, a multiplexer 430, and a synchronization circuit 416. The control circuit 420 has timing control circuits 422 to 427, and the multiplexer 430 has OR gates 431 to 436.
And an AND gate 437 connected to these.
The timing control circuits 422 to 427 are connected to one ends of the OR gates 431 to 436 of the multiplexer 430. The other ends of the OR gates 431, 433, 435 are directly connected to the register 414, while the other ends of the OR gates 432, 434, 436 are connected to the register 414 via the inverter 438.

The function of AND gate 437 is 4 pairs of OR gates 431 and 432.
AND logic as a multiplexer that selects one of the row active signals output from the pair of 33 and 434 and the pair of 435 and 436, and further, the selected four pairs of row active signals are combined into a single row. The AND logic for combining with the active signal 415 is expressed as one 6-input AND gate.

HS 'of the display control circuit 400 in FIG. 4 is a horizontal synchronizing signal H.
It is a signal that is earlier than S by 4 clock phases in the clock φ _s . The timing control circuit 422 determines φ = φ _s based on HS ′.
And the timing control circuit 423 generates the WAIT original signal due to the refresh when φ ≠ φ _s . The timing control circuits 424 and 425 generate a WAIT original signal due to DT at the start of display for φ = φ _s and φ ≠ φ _s . If the serial data register in the dual port RAM becomes empty during the display period, data transfer from the RAM cell array is required again, but the WAIT original signal corresponding to DT at that time is
= Φ _s and φ ≠ φ _s are generated at 426 and 427 which are composed of the decoder and the timing control circuit of the display address A0-7.

The register 414 functions similarly to the register 108 in the first embodiment. The signal 415 shown in FIG. 5 is a combination of the WAIT original signals generated by the timing control circuits 423, 425, 427 when φ ≠ φ _s , and the signal 415 is generated by the timing control circuits 422, 424, 426 when φ ≠ φ _s . The WAIT original signal is a composite signal. The operation after the synchronizing circuit 416 is the same as that of the first embodiment.

〔The invention's effect〕

As described above, the present invention provides a control circuit that performs optimum arbitration in each case regardless of whether the display control circuit and the drawing control circuit operate with a single clock or an asynchronous clock. With this, in the CRT controller to which the present invention is applied, the maximum drawing performance equivalent to that of the CRT controller configured only for the synchronization method can be obtained by the display / drawing synchronization method even if used.

In addition, the ability to freely select the synchronous method or the non-synchronous method is, for example, when the display control clock is close to the limit speed at which the image memory can be accessed, the number of drawing opportunities is increased by efficient arbitration in the synchronous method, and the synchronous method is selected. Therefore, there is an effect that it is possible to provide a highly flexible system design environment aiming at further improvement in drawing performance, such as enabling a trade-off with a decrease in drawing opportunities due to a slower drawing control clock.

Further, the present invention has an original content that the display control circuit and the drawing control circuit optimize the arbitration of access to the image memory on the basis of the information of whether the display control circuit performs the synchronous operation or the asynchronous operation.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing an operation example of a drawing control circuit, FIG. 3 is a diagram showing an operation timing example in the first embodiment, and FIG. Is the second of the present invention
FIG. 5 is a diagram showing an example of the operation timing, and FIG. 5 is a diagram showing an example of operation timing in the second example. 100,400 …… Display control circuit, 102,103,104,105 …… 1 clock delay circuit, 106,107,134 …… AND gate, 106
a, 107a, 415 …… timing signal, 108,414 …… register, 109,416 …… synchronization circuit, 110,410 …… drawing control circuit, 120,420 …… control circuit, 130,430 …… multiplexer, 131,132,431 to 436 …… OR gate, 133,438 …… Inverter, 422-427 …… Timing control circuit, 437 ……
And gate.

Claims (1)

[Claims] 1. A CRT controller that performs display control and drawing control on an image memory, based on a control signal of a display control circuit generated for accessing the image memory for display or refreshing the image memory, A control circuit that generates a first signal that is activated four cycles before the display control clock and is inactivated at the same timing, and a second signal that is activated three cycles ago and is inactivated two cycles ago. The display control and the drawing control have a means for setting a mode as to whether the asynchronous operation is a synchronous operation, and based on the mode setting means, in the case of the asynchronous operation, the first signal, and the synchronous operation In the case, a multiplexer for selecting the second signal in the first period and a wait signal for the drawing control circuit by synchronizing the output of the multiplexer with the drawing control clock. The drawing control circuit outputs the wait signal, which is the output of the synchronizing circuit, to the image for drawing when it is not in the access execution cycle of the image memory for drawing. Whether the memory can be accessed or not is determined. If the memory is accessible, the image memory for drawing is accessed in the next two cycles.
A CRT controller characterized in that in the latter half of the access cycle, it is determined whether or not the next image memory can be accessed.