JPH0782475B2 - Memory interlock control circuit - Google Patents

Description

The present invention relates to a memory interlock mechanism for controlling access to a main memory from a plurality of processors, and a memory interlock mechanism is used even when an error is detected in the contents of an interlock address register. For the purpose of realizing the means that can guarantee the contents of the above and continue the operation of the system, divide the contents of the interlock address register into multiple parts, and perform the error check for each divided partial value. For each partial value, a comparison circuit that compares with the value of the corresponding part of the address value for which access is requested, and when an error is detected in any partial value of the values of the interlock address register, the corresponding comparison circuit It is configured by providing a circuit that forces the output to the same state as when both comparison input values match.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interlock control circuit in a main memory control device that controls access to a main memory device from a plurality of processors, and particularly, in a memory interlock address register, an error occurs in an address value. The present invention relates to a memory interlock control circuit capable of guaranteeing the contents of the memory even when detected and continuing the operation without stopping the system.

[Prior Art] FIG. 2 is a diagram for explaining a memory interlock control. 51-1 to 51-n are processors, 52 is a main memory control device, 53 is a main memory device, and 54 is a memory interlock. It represents the mechanism.

In the figure, each of the plurality of processors 51-1 to 51-n can access the main storage control device 53 via the main storage control device 53.

However, when a certain processor (for example, 51-1) is accessing a certain address of the main memory device 53, if another processor that operates asynchronously accesses the same address and updates its content, the processor The processing content of 51-1 is not guaranteed at all.

In order to prevent such a situation, the main memory control device 53 is provided with a memory interlock mechanism 54.

The memory interlock mechanism 54 prevents another processor from accessing the same area when one processor is accessing a certain area of the main memory 53.
It is composed of a circuit that compares the address currently being accessed with the address of a new access request and, when they match, suppresses an access request generated later.

FIG. 3 is a diagram showing an example of a memory interlock control circuit that realizes such a memory interlock mechanism.
Are address registers, 56-1 to 56-4 are interlock address registers, 57-1 to 57-4 are comparison circuits,
Reference numeral 58 represents an OR circuit.

This circuit shows an example in which a plurality of interlock address registers are provided. These interlock address registers 56-1 to 56-4 are arbitrarily used when accessing from any of a plurality of processors which are access sources.

In the figure, when the processor makes an access request to the main memory, the address on the main memory to be accessed is stored in the address register 55.

Then, the contents of the address register 55 and the contents of the interlock address register are compared by the comparison circuits 57-1 to 57-4.

The comparator circuit outputs "1" when the value of the input address register and the value of the interlock address register match.

Therefore, when any of the address values stored in the address register 55 and the interlock address registers 56-1 to 56-4 matches, "1" is output from the corresponding comparison circuit. , The signal "1" is an OR circuit
It is output as a main memory access inhibition signal through 58.

On the other hand, the address value stored in the address register 55,
If there is no match with the value held in the interlock address register, the main memory access inhibition signal is not output and access to the corresponding address area on the main memory is permitted. At this time, the value stored in the address register is written in the vacant interlock address register.

[Problems to be Solved by the Invention] In the conventional memory interlock control circuit as described above, when an error is detected in the interlock address register, the address value held in the interlock address register is trusted. Because it is not possible, it is unknown whether the relevant area was protected surely,
Since the result of the instruction of the processor that locked the area is not guaranteed, the instruction or instruction sequence cannot be retried, and the instruction and the program that issued the instruction must be interrupted and abnormally terminated. There wasn't.

Further, in such a state, updating by a processor other than the processor that has locked the relevant area may not be guaranteed, so the system is normally down.

In view of the conventional problems as described above, the present invention, even when an error occurs in the interlock address register,
It is possible to guarantee the interlock of the corresponding area,
Therefore, an object of the present invention is to provide an interlock control circuit that can normally terminate an instruction being executed by a processor that has locked a corresponding area and can continue operation without bringing down the system. There is.

[Means for Solving the Problem] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention is
In the memory interlock control circuit for suppressing a request from another processor that accesses the same area while any processor refers to or updates an area of the main memory, the address requested by the access A means for dividing a value into N pieces to generate N partial values S1 to Sn, and a means for similarly dividing an interlocking address value into N pieces to generate N partial values T1 to Tn. , And the corresponding partial values (S1 T1), ..., (Sn Tn) are compared, and the comparison results W1 to Wn are output, and when the comparison results W1 to Wn all match, A means for suppressing an access request to the memory area is provided, a means for performing an error check for each partial value T1 to Tn related to the interlocked address value, and an error is detected in any one of the partial values Tk. In this case It said of partial value Tk (Sk
The memory interlock control circuit is provided with a means for forcibly replacing the comparison result Wk of (Tk) with one indicating a match.

[Operation] In the present invention, the interlock address register is divided into a plurality of parts, an error check is performed for each divided partial value, and the comparison with the address value for which an access is requested is also performed by the above partial value. It is configured to correspond to each case.

When an error is detected in any of the partial values read from the interlock address register, the partial value is forcibly "matched" regardless of whether the partial value matches the partial value of the address for which the access is requested. Signal is output.

This ensures that at least the address area held in the interlock address register is protected, so that the processor using the area can end the processing normally without interrupting the processing.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention.
1, 1-4 are interface registers with the main memory (hereinafter referred to as MSR
(Also called)). That is, the MSR is 1/4
It is divided into four parts of ~ 4/4. (M in the figure
SR2 / 4 and 3/4 are omitted in the drawing. Further, 2-1 and 2-4 represent a part of the interlock address register (hereinafter also referred to as LKR).

Like the MSR, the LKR is divided into four parts, 1/4 to 4/4. (LKR2 / 4, 3/4 are omitted in the drawing as in the case of MSR.) Furthermore, 3-1 to 3-4 are comparison circuits, 4-1 to 4-4 are error detection circuits, 5 Reference numerals -1 to 5-4 represent OR circuits (in the figure, the intermediate ones are omitted as in the case of MSR and LKR), and 6 is an AND circuit.

An access request to the main memory from each processor is selected in the priority circuit by the priority circuit and then set in the interface register (MSR) with the main memory to access the main memory.

At this time, the contents of MSR and LKR are compared, and if they match, the corresponding area is in use (locked), so access is suppressed by the main memory access suppression signal. It

In the present embodiment, the address structure is 4 bytes, which is divided into 4 by 1 byte and shown by 1-1 to 1-4 in FIG.
It is configured to be stored in each of MSR1 / 4 to MSR4 / 4.

The addresses stored in LKR1 / 4 to LKR4 / 4 are also the same.
Each part of R1 / 4 to LKR4 / 4 becomes a bit position corresponding to each part of MSR1 / 4 to MSR4 / 4.

A parity bit is attached to each of LKR1 / 4 to LKR4 / 4, and at the time of reading, the parity check is performed by the error detection circuits 4-1 to 4-4.

The contents of MSR and the contents of LKR are compared circuit 3 for each byte.
"-1" is output from the comparison circuit when any one of -1 to 3-4 compares and matches.

Therefore, when all the contents of MSR1 / 4 to MSR4 / 4 and all the contents of LKR1 / 4 to LKR4 / 4 match, the comparison result signal output from the AND circuit 6 becomes "1", and the signal is stored in the main memory. Used as an access inhibition signal.

If an error is detected by any of the error detection circuits 4-1 to 4-4, the output of the corresponding error detection circuit becomes "1" and the output of the corresponding comparison circuit is applicable. The OR circuit outputs "1", which becomes the input of the AND circuit 6.

Therefore, when an error occurs in any of LKR1 / 4 to LKR4 / 4, if the contents of the other LKR match the contents of the corresponding MSR, the output of AND circuit 6 becomes "1" and access to the main memory is made. Is suppressed.

In this case, the area where access is prohibited becomes wider than in the normal case, but the processing of the executing processor is surely protected.

The contents of the LKR are updated when they are no longer needed, so if the error is caused by noise or intermittent failures with low reproducibility, the range of the locked area is expanded. It does not significantly affect the processing capacity.

In particular, when the present invention is applied to a system configured to prepare a plurality of sets of LKR as shown in FIG. 3, the influence is further reduced.

In such a configuration, even if the LKR error is deterministic due to a hardware failure, by searching for a method of blocking the corresponding LKR, the processing capacity of the system is hardly affected, It is also possible to continue operating the system.

[Effects of the Invention] As described above, according to the present invention, while controlling access to the main memory from a plurality of processors and any one of the processors refers to or updates the contents of the main memory, In a main storage controller equipped with a memory interlock mechanism for suppressing the update of the contents of the same address area by another processor, even if an error occurs in the interlock address register, the interlock of the corresponding area Therefore, it is possible to normally terminate the executing instruction of the processor that has locked the relevant area, and to continue its operation without taking measures to bring down the system. There is an advantage to get.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram for explaining control of a memory interlock, and FIG. 3 is a diagram showing an example of a memory interlock control circuit. 1-1, 1-4 ... Interface register, 2-1, 2-4
...... Interlock address register, 3-1, 3-4 ......
Comparator circuit, 4-1-4-4 ... Error detection circuit, 5-1-5-
4 ... OR circuit, 6 ... AND circuit

Claims (1)

[Claims] 1. A memory interlock control circuit for suppressing a request from another processor for accessing the same area while any processor refers to or updates an area of the main memory, Divide the requested address value into N, and
The means for generating the partial values S1 to Sn and the interlocking address value are similarly divided into N,
Means for generating N partial values T1 to Tn and means for comparing the corresponding partial values (S1 T1), ..., (Sn Tn) and outputting the comparison results W1 to Wn, and a comparison result. When W1 to Wn all match, a means for suppressing the access request to the memory area is provided, and each partial value T1 of the interlocked address value
~ Means to perform error check for Tn, and when an error is detected in any of the partial values Tk, the comparison result Wk of the above (Sk Tk) related to this partial value Tk is forced to indicate a match. A memory interlock control circuit, comprising: means for replacing.