JPH0782755B2 - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0782755B2 JPH0782755B2 JP14192886A JP14192886A JPH0782755B2 JP H0782755 B2 JPH0782755 B2 JP H0782755B2 JP 14192886 A JP14192886 A JP 14192886A JP 14192886 A JP14192886 A JP 14192886A JP H0782755 B2 JPH0782755 B2 JP H0782755B2
- Authority
- JP
- Japan
- Prior art keywords
- storage element
- floating gate
- threshold voltage
- memory device
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、閾値電圧の変動により情報を記録する半導体
記憶装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that records information by changing a threshold voltage.
従来の技術 従来、閾値電圧の変動を利用した半導体記憶装置として
は、EPROM(Erasable and Programable Read Only Memo
ry)等に用いられる第4図に示した様な制御ゲート1と
基板2との間に浮遊ゲート3を有したいわゆる浮遊ゲー
ト型MOSFETがある。これらの素子は、ホット・エレクト
ロン注入やトンネル注入によりこの電荷蓄積層に電荷を
注入・捕獲することにより、閾値電圧を変動させ情報を
記録する。したがって書き込まれた情報は、閾値電圧の
大小あるいは、閾値電圧変動の有無に置き換えて記憶さ
れる。2. Description of the Related Art Conventionally, as a semiconductor memory device that uses a change in threshold voltage, EPROM (Erasable and Programmable Read Only Memo) is used.
There is a so-called floating gate type MOSFET having a floating gate 3 between a control gate 1 and a substrate 2 as shown in FIG. These devices record information by changing the threshold voltage by injecting and trapping charges in this charge storage layer by hot electron injection or tunnel injection. Therefore, the written information is replaced with the magnitude of the threshold voltage or the presence or absence of the threshold voltage fluctuation and stored.
発明が解決しようとする問題点 以上述べたように、従来の閾値電圧の変動を利用した半
導体記憶装置では、情報の記録を閾値電圧変動の有無等
に置き換えて記憶させるため1素子当たり1ビットの情
報量した記憶させることができないといった問題があっ
た。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, in the conventional semiconductor memory device utilizing the fluctuation of the threshold voltage, one bit per element is used to store information by replacing the recording of information with the presence or absence of the threshold voltage fluctuation. There was a problem that the amount of information could not be stored.
本発明は、かかる点を解決するためになされたもので1
素子当たりの情報の記録量を複数ビット以上とする大容
量高密度記憶装置を実現することを目的としている。The present invention has been made to solve the above problems.
It is an object of the present invention to realize a large-capacity, high-density storage device in which the amount of information recorded per element is a plurality of bits or more.
問題点を解決するための手段 本発明は、上記問題点を解決する為、電荷注入素子と記
録素子とを分けることにより電荷蓄積層への電荷の注入
量を制御よくコントロールし記憶素子の閾値電圧または
ドレイン電流を任意の値に設定する回路と、この閾値電
圧またはドレイン電流の変動量を読み取る回路とを備え
従来の単に閾値電圧の変動の有無による記憶法に替えて
閾値電圧またはドレイン電流の変動量として情報を記録
することにより、1素子当たりの情報の記録量を複数ビ
ット以上とする大容量高密度記憶装置を可能とするもの
である。Means for Solving the Problems In order to solve the above problems, the present invention separately controls a charge injection amount into a charge storage layer by separately dividing a charge injection element and a recording element to control a threshold voltage of a storage element. Alternatively, a circuit for setting the drain current to an arbitrary value and a circuit for reading the fluctuation amount of the threshold voltage or the drain current are provided, and the threshold voltage or the drain current is changed instead of the conventional storage method simply by the presence or absence of the change of the threshold voltage. By recording information as the amount, it is possible to realize a large-capacity high-density storage device in which the recording amount of information per element is a plurality of bits or more.
作用 本発明は、上記した構成により、電荷蓄積層への電荷注
入量を制御しMOSFETの閾値電圧またはドレイン電流を任
意の値に変化させその値および変動量により情報を記録
する。このため、従来行なわれていた閾値電圧変動の有
無による記録に比べ1素子当たりに記録できる情報の量
が格段に増大する。例えば、閾値電圧変動を100mVおき
に認識できる様に注入量制御回路および読み取り回路を
設計すれば変動幅1.6Vで1素子4bitの記憶が可能とな
る。Action The present invention has the above-described configuration to control the amount of charge injection into the charge storage layer, change the threshold voltage or drain current of the MOSFET to an arbitrary value, and record information according to the value and the amount of change. For this reason, the amount of information that can be recorded per element is significantly increased as compared with the conventional recording based on the presence or absence of fluctuations in threshold voltage. For example, if the injection amount control circuit and the reading circuit are designed so that the threshold voltage fluctuation can be recognized every 100 mV, one element can store 4 bits with a fluctuation width of 1.6V.
実施例 本発明に係る実施例を第1図を用いて説明する。Embodiment An embodiment according to the present invention will be described with reference to FIG.
7は記憶素子すなわち記憶用浮遊ゲート型MOSFETで、電
荷注入素子すなわちホット・キャリア注入用浮遊ゲート
MOSFET10とソース及び浮遊ゲート20で接続されている。
11は電流電圧変換器、12は演算増幅器、13は比較器であ
る。Reference numeral 7 is a storage element, that is, a floating gate MOSFET for storage, which is a charge injection element, that is, a floating gate for hot carrier injection.
It is connected to the MOSFET 10 by a source and a floating gate 20.
11 is a current-voltage converter, 12 is an operational amplifier, and 13 is a comparator.
ホットキャリア注入用素子10にはトランスファーゲート
スウィチ9を通しホットエレクトロン注入可能なドレイ
ン電圧(たとえば21V)が加わっている。この状態で浮
遊ゲート型MOSFET10の浮遊ゲートには、チャンネルを流
れるドレイン電流が、ドレイン接合近傍の高電界領域で
加速されホットエレクトロンとなりゲート酸化膜を通し
注入される。これにより浮遊ゲートどうしが電気的につ
ながった記憶用浮遊ゲート型MOSFETのI−V特性は、第
2図に示す様にその特性がゲート電圧軸方向に平行移動
する(つまり、閾値電圧が変化する)。ゲート端子15に
は、常にMOSFET7に一定のドレイン電流が流れる様に演
算増幅器12により制御された電圧がかけられる為、この
電圧も浮遊ゲート注入された電荷量にみあっただけ変化
する。このゲート電圧を記憶したい情報に相当する電圧
(端子18に加えられた電圧)になるまで比較器13によ
り、モニターしつつホットエレクトロン注入を続け所定
の電圧にゲート端子15の電圧がなかったことを比較器13
で検知しトランスファーゲート9をoffし浮遊ゲート型M
OSFET10のゲート,ドレイン端子への印加を終了すれば
記憶したい情報に相当する閾値電圧を有するMOSFETが得
られる。A drain voltage (for example, 21V) capable of injecting hot electrons is applied to the hot carrier injection element 10 through the transfer gate switch 9. In this state, the drain current flowing through the channel is accelerated in the high electric field region near the drain junction into hot electrons in the floating gate of the floating gate type MOSFET 10 to become hot electrons and injected through the gate oxide film. As a result, the IV characteristics of the floating gate type MOSFET for storage in which the floating gates are electrically connected to each other move in parallel in the gate voltage axis direction as shown in FIG. 2 (that is, the threshold voltage changes). ). Since a voltage controlled by the operational amplifier 12 is applied to the gate terminal 15 so that a constant drain current always flows through the MOSFET 7, this voltage also changes as much as the amount of charges injected into the floating gate. The hot electron injection is continued while monitoring by the comparator 13 until the gate voltage becomes a voltage (voltage applied to the terminal 18) corresponding to the information to be stored. Comparator 13
Detected by, transfer gate 9 is turned off and floating gate type M
When the application to the gate and drain terminals of OSFET 10 is completed, a MOSFET having a threshold voltage corresponding to the information to be stored can be obtained.
また、読み出しするときは、ゲートにドレイン電流が所
定の値になるように電圧を印加し、その時のゲート電圧
を読み取り時の閾値電圧とする。When reading, a voltage is applied to the gate so that the drain current has a predetermined value, and the gate voltage at that time is set as the threshold voltage for reading.
以上、特許請求の範囲第1項に係わる実施例について述
べた。The embodiments according to claim 1 have been described above.
次に特許請求の範囲第2項に係わる実施例を第3図に従
って説明す。前述の実施例は、閾値電圧の値を変化させ
る事により情報の記録を行なったものであったが、本実
施例では、ゲート電極15にある電圧を印加した時に流れ
るドレイン電流量により情報の記録を行なおうとするも
のである。書き込み,読み出しは、前述の実施例が一定
ドレイン電流で行なわれるのに対し、本実施例では、一
定ゲート電圧下のドレイン電流量で行なう点が異なり、
前述の実施例に比べ回路構成が簡単になる。Next, an embodiment according to claim 2 will be described with reference to FIG. In the above-described embodiment, the information is recorded by changing the threshold voltage value. However, in the present embodiment, the information is recorded by the drain current amount flowing when the voltage applied to the gate electrode 15 is applied. Is to do. Writing and reading are performed with a constant drain current in the above-described embodiment, whereas this embodiment is different in that a drain current amount under a constant gate voltage is used.
The circuit configuration is simpler than that of the above-described embodiment.
また、読み出しにおいて、閾値電圧やドレイン電流の変
動量を求める際に記憶素子として用いた素子で同形状の
素子を比較用素子とし、この素子の特性との差によりそ
れぞれの変動量を求めることにより温度変化等の影響を
受けにくい記憶装置とする事ができる。Also, in reading, the element used as a storage element when obtaining the variation of the threshold voltage or drain current is used as a comparison element, and the variation of each is obtained by the difference with the characteristics of this element. A memory device that is not easily affected by temperature changes and the like can be provided.
発明の効果 以上述べた様に、本発明によれば、情報をMOSFETの閾値
電圧の変動量あるいはドレイン電流の変動量におきかえ
て記録する為、アナログ情報をそのまま記録または、デ
ジタル情報であれば1素子当たり複数のビット記録がで
きる。電荷注入素子と記憶素子を分けたことにより書き
込み時及び読み出し時に同じドレイン電圧を用いる事が
できる。また電荷注入素子と記憶素子が異なるため注入
による記録素子特性の劣化(たとえば界面準位発生によ
るgmの劣化等)が無視できる。したがって同一素子で注
入・記録する場合に比べより正確な閾値電圧及びドレイ
ン電流の制御が可能となる。EFFECTS OF THE INVENTION As described above, according to the present invention, since the information is recorded instead of the variation of the threshold voltage of the MOSFET or the variation of the drain current, the analog information is recorded as it is or 1 Multiple bits can be recorded per element. By dividing the charge injection element and the storage element, the same drain voltage can be used during writing and reading. Further, since the charge injection element and the storage element are different, the deterioration of the recording element characteristics due to the injection (for example, the deterioration of gm due to the generation of the interface state) can be ignored. Therefore, the threshold voltage and the drain current can be controlled more accurately than in the case where the same element is used for the injection / recording.
第1図は本発明の一実施例の半導体記憶装置の構成図、
第2図は浮遊ゲート型MOSFETのホットエレクトロン注入
による特性変動を示す図、第3図は別の実施例を示す為
の半導体記憶装置の構成図、第4図は従来例を説明する
為の半導体記憶装置の一部概略断面図である。 7,10……浮遊ゲート型MOSFET、9……トランスファーゲ
ート、11……電流電圧変換器、12……演算増幅器、13…
…比較器。FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention,
FIG. 2 is a diagram showing characteristic fluctuations of a floating gate type MOSFET due to hot electron injection, FIG. 3 is a configuration diagram of a semiconductor memory device for showing another embodiment, and FIG. 4 is a semiconductor for explaining a conventional example. It is a partial schematic sectional drawing of a memory | storage device. 7,10 Floating gate MOSFET, 9 Transfer gate, 11 Current / voltage converter, 12 Operational amplifier, 13
... comparator.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/792 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/792
Claims (2)
注入・蓄積することによって閾値電圧を変化させ情報を
記憶する半導体記憶装置であって、浮遊ゲートを有し各
々の浮遊ゲート同士が電気的に接続されている記憶素子
及び電荷注入素子と、前記記憶素子の閾値電圧を読み取
って予め与えられた所定の電圧との比較を行う比較手段
とを有し、前記記憶素子の閾値電圧が予め与えられた所
定の電圧に到達するまでは前記記憶素子に電荷を注入
し、前記記憶素子の閾値電圧が所定の電圧に到達した時
点で電荷の注入を完了することを特徴とする半導体記憶
装置。1. A semiconductor memory device for storing information by changing a threshold voltage by injecting / accumulating charges into a floating gate of a floating gate type MOSFET, the floating gate having floating gates, wherein each floating gate is electrically connected to each other. A storage element and a charge injection element connected to the storage element, and a comparison means for reading a threshold voltage of the storage element and comparing the storage element with a predetermined voltage. A semiconductor memory device, wherein charges are injected into the storage element until the predetermined voltage is reached, and the injection of charges is completed when the threshold voltage of the storage element reaches a predetermined voltage.
注入・蓄積することによって閾値電圧を変化させ情報を
記憶する半導体記憶装置であって、浮遊ゲートを有し各
々の浮遊ゲート同士が電気的に接続されている記憶素子
及び電荷注入素子と、前記記憶素子のドレイン電流を読
み取って予め与えられた所定の電流との比較を行う比較
手段とを有し、前記記憶素子のドレイン電流が予め与え
られた所定の電流に到達するまでは前記記憶素子に電荷
を注入し、前記記憶素子のドレイン電流が所定の電流に
到達した時点で電荷の注入を完了することを特徴とする
半導体記憶装置。2. A semiconductor memory device for storing information by changing a threshold voltage by injecting / accumulating charges into a floating gate of a floating gate type MOSFET, the floating gate having floating gates, and each floating gate being electrically connected to each other. A storage element and a charge injection element connected to the storage element, and a comparing means for reading a drain current of the storage element and comparing the drain current with a predetermined current, the drain current of the storage element being given in advance. A semiconductor memory device, wherein charges are injected into the storage element until a predetermined current is reached, and the injection of charges is completed when the drain current of the storage element reaches a predetermined current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14192886A JPH0782755B2 (en) | 1986-06-18 | 1986-06-18 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14192886A JPH0782755B2 (en) | 1986-06-18 | 1986-06-18 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62298999A JPS62298999A (en) | 1987-12-26 |
| JPH0782755B2 true JPH0782755B2 (en) | 1995-09-06 |
Family
ID=15303411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14192886A Expired - Lifetime JPH0782755B2 (en) | 1986-06-18 | 1986-06-18 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0782755B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100473308B1 (en) | 1995-01-31 | 2005-03-14 | 가부시끼가이샤 히다치 세이사꾸쇼 | Nonvolatile memory device |
| JP3740212B2 (en) | 1996-05-01 | 2006-02-01 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6126999A (en) * | 1984-07-14 | 1986-02-06 | Ricoh Co Ltd | read-only memory |
| JPS61113194A (en) * | 1984-11-06 | 1986-05-31 | Nec Corp | Semiconductor integrated circuit device |
-
1986
- 1986-06-18 JP JP14192886A patent/JPH0782755B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62298999A (en) | 1987-12-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |