JPH0783025B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to a structure of a transistor element suitable for high speed and high integration of a bipolar type integrated circuit and a manufacturing method thereof.

2. Description of the Related Art Recently, in the field of bipolar integrated circuits, various new technologies have been proposed for improving the switching speed of transistors. The major improvements made by these technologies are to make the internal base of a vertical NPN transistor shallow to form a narrow width in the depth direction of the base to shorten the transit time of electrons in the base. On the other hand, there is a method of lowering the resistance of this parasitic base in order to reduce the delay time due to the coupling between the parasitic base resistance and the base input capacitance that enter in series. As a method of reducing the resistance of the parasitic base, a so-called graft base method is known, in which a parasitic base region for extracting an electrode is formed by diffusion with impurities having a higher concentration than the internal base, and this is used as an external base. Has been. For example, the 1984 International Electron Device Meeting Digest of Technical Papers (INTERNATIONAL EL
ECTRON DEVICE MEETING DIGEST OF TECHNICAL PAPERS P
In P.753-756), when forming a vertical NPN transistor, the external base formed under the thermal oxide film and the internal base formed from the opening of the thermal oxide film are close to the edge of the thermal oxide film. A connected structure is disclosed.

Problems to be Solved by the Invention In order to increase the speed of a bipolar transistor, it is necessary to simultaneously form a shallow internal base and a low resistance external base. As the inner base is made shallower, the layered resistance of the inner base is likely to increase, and in order to reduce this effect, a method of narrowing the width of the emitter is usually adopted. However, in this case, if the high-concentration impurity concentration of the external base is increased, the impurity atoms invade the internal base and change the impurity profile of the internal base. A bad phenomenon such as an increase in the base transit time of the electron occurs. The only way to suppress this phenomenon is to reduce the impurity concentration of the external base and reduce the lateral diffusion of the base. According to this method, invasion of the external base is suppressed, but when the internal base is formed to have a very shallow depth of 150 nanometers, the following structural or manufacturing problems occur. That is, since the opening end formed by the beak-shaped end portion of the oxide film fluctuates unstable due to etching during the process, the connectivity itself between the internal base and the external base becomes unstable, and further, the connection is In a bad case, the lateral diffusion of the internal base under this beak is small, so the effective base width in the lateral direction is narrowed, so that a punch-through leakage current between the collector and the emitter is likely to occur. was there. For example, FIG. 3 (a)
As shown in, a P-type silicon semiconductor substrate 100
After forming the N type buried layer 102 and the N type epitaxial semiconductor layer 104 thereon, silicon having a thickness of about 100 nanometers is formed on the thin thermal oxide film 108 having a thickness of about 20 nanometers. Using the nitride film pattern 110 as a mask, boron with a dose amount of 2 × 10 / cm ² is ion-implanted to form a P-type semiconductor region 116 serving as an external base. Further, as shown in FIG. 3 (b), an oxidation resistant silicon nitride film pattern 11 is formed.
Thermal oxidation is performed using 0 as a mask to form an oxide film 122 having a thickness of about 250 nanometers, the silicon nitride film pattern 110 and the oxide film 108 are removed, and an opening for an emitter is formed.
A polycrystalline silicon film is deposited on the entire surface and patterned to form a polycrystalline silicon film pattern 124. Further, boron with a dose amount of 2 × 10 / cm ² is ion-implanted into the polycrystalline silicon film pattern 124. Then, by heat treatment, a P-type semiconductor region 12 having an active base with a depth of about 150 nanometers 12
After forming 6, the arsenic was similarly ion-implanted into the polycrystalline silicon film pattern 124, and a heat treatment was performed to form a semiconductor region 128 having an N type depth. According to such a manufacturing method, the connectivity between the external base 116 and the internal base 126 may be different depending on the shape of the beak-shaped end of the oxide film pattern 122 as shown in FIG. 3B. It will be difficult. Therefore, there is a need for a novel transistor structure and a method for manufacturing the same, which solves the problems in the structure and manufacturing due to the unstable connection between the external base and the internal base.

Means for Solving the Problems In order to solve such a problem, the present invention provides an opening of an insulating film formed on a semiconductor layer of the first conductivity type and a first insulating film formed below the insulating film. A first semiconductor region of two conductivity type;
A groove portion formed in the opening of the insulating film, a second semiconductor region of the second conductivity type formed in the groove portion, and the second
In a structure having a third semiconductor region of a first conductivity type formed in a second semiconductor region of a conductivity type, the first semiconductor region and the second semiconductor region are connected to each other. A structure of a semiconductor device; a step of forming an opening of an insulating film on a first conductive type semiconductor layer; a step of forming a second conductive type first semiconductor region below the insulating film; Forming a groove in the opening, forming a second semiconductor region of the second conductivity type in the groove, and forming a second semiconductor region of the second conductivity type in the second semiconductor region of the second conductivity type. And a step of forming a semiconductor region of No. 3, which provides a method for manufacturing a semiconductor device characterized by connecting the first semiconductor region and the second semiconductor region.

Operation When the means according to the present invention is applied to the emitter-base junction of a bipolar transistor as an example, the following operation occurs.

By forming the groove, the area for connecting the second semiconductor region serving as the external base and the third semiconductor region serving as the internal base immediately below the end of the opening of the oxide film which is the insulating film is increased. As a result, the connectivity between the external base and the internal base could be well stabilized. Furthermore, since the internal base can be made as deep as the external base by the groove portion formed in the opening of the oxide film, the N-type epitaxial layer left between the internal base and the N-type buried layer immediately below can be thinned. As a result, the collector resistance could be reduced. In addition, since the distance between the external base and the internal base can be optimized by widening the side surface of the groove portion in the lateral direction, the controllability of these connections can be improved. As a result, it is possible to prevent the occurrence of defects such as a leak current having a punch-through property between the collector and the emitter. From the above, it is possible to prevent the generation of a punch-through leak current in terms of direct current, and the occurrence of a bad phenomenon such as an increase in switching time due to a large base resistance in terms of alternating current. Since it can be reduced, the switching time of the transistor can be further improved.

EXAMPLE A first example in which the method of the structure according to the present invention is applied to the emitter-base junction of a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 1, in the N-type epitaxial semiconductor layer 104 having the N-type buried layer 102 formed on the P-type silicon semiconductor substrate 100, a thermal oxide film 122 having a beak-shaped end portion is formed on the surface. Has been done. Under the main part of the oxide film, a P-type semiconductor region 116 serving as an external base,
A groove 142 formed in the opening formed by the oxide film, and a P-type semiconductor region 126 serving as an internal base is formed in a lower portion of the groove 142.
And are formed. The external base 116 and the internal base 126 are connected immediately below the beak-shaped end of the oxide film, and the polysilicon electrode 124 of the N-type semiconductor region 128 which serves as an emitter is formed.

If the polysilicon electrode 124 is used as a diffusion source of the internal base 126 and the emitter 128 as an example of a method of forming such an emitter-base junction, the internal base depth is 150 nanometers and the emitter depth is 50 nanometers. Since a structure excellent in high-speed performance can be realized, and by forming the groove portion, it is possible to satisfactorily connect the external base and the internal base on the side surface of the groove portion with a relatively large area. -It was possible to prevent the occurrence of defects such as through-current leak current and stabilize the connectivity of the base. Furthermore, since the internal base can be made as deep as the external base by the groove portion formed in the opening of the oxide film, the N-type epitaxial layer left between the internal base and the N-type buried layer immediately below can be thinned. As a result, the collector resistance could be reduced. In the structure of FIG. 1, the side surface of the groove is almost vertical, but it may be of any shape if necessary. For example, when the beak-shaped end portion of the oxide film and the P-type semiconductor region 116 serving as an external base are considerably separated from each other, an isotropic etching method is used to form a groove portion under the beak-shaped end portion. If the side surface of the groove portion is formed so as to go under, the distance between the internal base and the external base can be reduced. As a result, the parasitic base resistance can be reduced, and advantages such as stabilization of the controllability of the connection occur.

Next, a second embodiment in which the method of the present invention is applied to a method for manufacturing a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 2 (a), a P-type silicon semiconductor substrate 100
After forming the N-type buried layer 102 on the top, the N-type epitaxial semiconductor layer 104 was formed. P-type element isolation region 1
After forming 06, a thin thermal oxide film 108 of about 20 nanometers is formed.
Thermal oxidation was performed using the silicon nitride films 110A and 110B having a thickness of about 100 nanometers formed on the A and 108B as masks to form a thick oxide film 112 having a thickness of about 600 nanometers.

As shown in FIG. 2B, a resist pattern 114 is formed by a photomask process, and using this as a mask, a silicon nitride film pattern 110C having a width of about 1 micron is left on a portion where an emitter is to be formed. Using the pattern 114 as a mask, boron with a dose amount of 2 × 10 / cm ² is ion-implanted to form a P-type semiconductor region 116 serving as an external base.

As shown in FIG. 2 (c), after removing the resist pattern 114, an N type semiconductor region 120 is selectively formed by ion implantation of phosphorus, and an oxidation resistant silicon nitride film pattern 110C is further formed. Thermal oxidation was performed as a mask to form an oxide film 122 having a thickness of about 200 nanometers.

As shown in FIG. 2D, the silicon nitride film pattern 110C,
After forming the opening for the emitter from which the oxide film 108A is removed,
A resist pattern 140 was formed, and using this as a mask, a groove 142 was formed in the opening for the emitter.

As shown in FIG. 2 (e), a polycrystalline silicon film is deposited on the entire surface, patterned to form polycrystalline silicon film patterns 124A and 124B, and further, a boron dose of 2 × 10 / cm ² is applied. After ion-implanting into the polycrystalline silicon film pattern 124A and forming a P-type semiconductor region 126 having a depth of about 150 nanometers as an active base by heat treatment, arsenic is similarly added to the polycrystalline silicon film 124A. Ions are implanted into the pattern 124A and a heat treatment is performed to form an N-type semiconductor region 128 having a depth of about 50 nanometers and serving as an emitter.

As shown in FIG. 2 (f), after depositing a silicon oxide film 130 on the entire surface, aluminum electrodes 132A, 132B, 132C, etc. were formed according to a usual manufacturing method.

As described above, according to the method of the present invention, a vertical NPN transistor is formed, and the base width of the active element portion (internal base) is excellent at about 100 nanometers. Since the external base and the internal base were satisfactorily connected by the formation of the groove, it was possible to prevent the generation of the leak current between the collector and the emitter under the beak-shaped oxide film. Furthermore, by forming the groove,
Since the collector resistance was reduced, the switching characteristics were improved, and the unnecessary intermediate base formed in the internal base formation planned part was also removed, resulting in good characteristics with little variation in the current amplification factor. Was given.

According to the method of the present invention, the emitter of the bipolar element is the gate, the external bases on both sides of this gate are the sources,
When considered as a drain, it can function as a junction field effect transistor having an internal base as a channel portion. Thus, the method of the present invention can be applied not only to bipolar devices but also to various semiconductor devices.

EFFECTS OF THE INVENTION By the structure of the present invention and the method of manufacturing the same, a semiconductor device having a structure of an active element portion excellent in speeding up and high integration and having good controllability in manufacturing the active element portion is provided. We were able to.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a bipolar NPN transistor according to the present invention, FIG. 2 is a sectional view of a series of steps showing a method for manufacturing a bipolar NPN transistor according to the method of the present invention, and FIG. 3 is a bipolar NPN according to a conventional method. 6A and 6B are cross-sectional views illustrating a structure of a transistor and a problem in manufacturing the transistor. 100 ... P-type semiconductor substrate, 102 ... N-type buried layer, 104
... N-type semiconductor layer, 106, 116, 126 ... P semiconductor region, 1
20, 128 …… N-type semiconductor region, 108, 112, 122, 130 ……
Silicon oxide film, 110 ... Silicon nitride film, 124 ... Polycrystalline silicon film, 114, 140 ... Resist, 132 ... Aluminum electrode, 142 ... Groove part.

Claims (7)

[Claims] 1. An opening of an insulating film formed on a semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type formed below the insulating film, and an opening of the insulating film. A second conductivity type second semiconductor region formed in the groove, a second conductivity type second semiconductor region formed in the groove, and a first conductivity type third semiconductor region formed in the second conductivity type second semiconductor region. A semiconductor device, comprising: a structure having a semiconductor region, wherein the first semiconductor region and the second semiconductor region are connected to each other. 2. The semiconductor device according to claim 1, wherein an end portion of an insulating film forming an opening overhangs a side surface of the groove portion overhangs. 3. The first semiconductor region is used as an external base, the second semiconductor region is used as an internal base, and the third semiconductor region is used as an emitter. Semiconductor device. 4. A step of forming an opening of an insulating film on a semiconductor layer of the first conductivity type, and a first conductivity type of a second conductive film under the insulating film.
Forming a semiconductor region, forming a groove in the opening of the insulating film, and forming a second conductive type second groove in the groove.
Forming a semiconductor region of the second conductive type and the second conductive type second
Forming a third semiconductor region of the first conductivity type in the semiconductor region, and connecting the first semiconductor region and the second semiconductor region to each other. 5. An oxide film having a beak-shaped end portion is formed around the mask material pattern by an oxidation method using the oxidation resistant mask material pattern as a mask in the step of opening the insulating film, and the acid resistance is used. By using the method of removing the oxidizable mask material pattern and forming the opening by the oxide film.
The method of ion-implanting impurities using a mask material composed of the oxidation-resistant mask material pattern as a mask is used as the step of forming the conductive type first semiconductor region. 4. A method of manufacturing a semiconductor device according to item 4. 6. The method according to claim 4 or 5, wherein the first semiconductor region is used as an external base, the second semiconductor region is used as an internal base, and the third semiconductor region is used as an emitter. Manufacturing method of semiconductor device. 7. A second semiconductor region of the second conductivity type and a first semiconductor region.
The third conductive type semiconductor region is formed by using the same polycrystalline semiconductor as a diffusion source.
Item 7. A method for manufacturing a semiconductor device according to any one of Items 6 to 6.