JPH0783258B2 - Phase synchronization circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit effective against frequency fluctuation.

[Conventional technology]

Conventionally, as this type of phase locked loop circuit, for example, as shown in FIG. 5, there has been proposed one in which a loop is constituted by a counter 1, a counter 2, a phase comparator 3, a loop filter 4, a DC amplifier 5, and a voltage controlled oscillator 6. Has been done. In this phase synchronization circuit, a signal A obtained by dividing the input signal from the input terminal IN by the counter 1 and a signal B obtained by dividing the output signal from the voltage controlled oscillator 6 by the counter 2 are sent to the phase comparator 3. And compare the phases.
Then, the phase comparison output is passed through the loop filter 4,
In addition, by controlling the oscillation frequency of the voltage controlled oscillator 6 with the output amplified by the DC amplifier 5, the signal B phase-locked with the signal A can be obtained from the output terminal OUT.

[Problems to be Solved by the Invention]

The conventional phase locked loop circuit described above can make the phase difference between the signal A and the signal B zero if the frequency of the external input signal does not change, but when the frequency of the external input signal changes by Δf, 2π in synchronization with signal B
A steady phase error of Δf / K (rad) [K: loop gain] occurs.

Therefore, in the conventional phase-locked loop, it is possible to reduce the steady-state phase error with respect to the input frequency fluctuation by increasing the loop gain, but it is impossible to reduce it to zero, and complete phase synchronization is performed. There is a problem that you can not.

It is an object of the present invention to provide a phase locked loop circuit that can achieve phase locking even when frequency fluctuations occur.

[Means for Solving the Problems]

The phase locked loop circuit of the present invention includes a phase locked loop circuit using a voltage controlled oscillator, a detector for detecting a phase error between the input signal and the voltage controlled oscillator, and a phase error detected as a digital value by counting a high speed clock. Counter, a latch circuit that latches this digital value, an integrator that integrates the latched digital value, a D / A converter that converts the integrated digital value to analog, and an analogized phase error A means for adding an adder added as an offset amount to the control voltage of the voltage controlled oscillator and detecting a phase error selects an input signal and an output signal of the voltage controlled oscillator as either a set signal or a reset signal. When the count value of the selector and the counter described above exceeds the upper limit, the addition is performed based on the overflow carry signal output from the counter. It generates a polarity signal, 1 to perform the selection in the selector supplies the signal to the selector /
And a set / reset circuit that outputs a reset pulse and a set pulse to the counter using the overflow carry signal and the reset signal of the selector as reset inputs and the set signal of the selector as the set input. And, the reset signal is sent to the latch circuit as a latch signal, a load signal is generated based on the reset signal and the overflow carry signal and sent to the counter, and the add / decrease polarity signal is sent to the integrator. It is configured to obtain.

[Action]

With this configuration, the phase error due to the frequency fluctuations occurring in the input signal is detected by the phase error detector, this phase error is integrated with a digital value, and this is converted into an analog quantity to obtain the control voltage of the voltage controlled oscillator. By adding it, the oscillation frequency of the voltage controlled oscillator can be controlled according to the frequency fluctuation of the input signal, and the phase error is reduced to zero to realize the phase synchronization.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 5 are designated by the same reference numerals. Here, the fifth
In addition to the phase synchronization circuit in the figure, the phase error detector 7 and counter
8, a high-speed clock generator 9, a latch circuit 10, an integrator 11, a D / A converter 12, and an adder 13 are additionally provided, and the adder 13 is interposed between the DC amplifier 5 and the voltage controlled oscillator 6. I am inserting it.

As shown in FIG. 2, the phase error detector 7 includes a selector 71, a set / reset circuit (SR flip-flop) 72,
It is composed of a 1/2 divider 73, an OR gate 74, and a NAND gate 75. The phase error detector 7 switches the signals A and B by the selector 71 to set / reset the circuit 72.
Each set input and reset input. The phase error detector 7 can output an add / decrease polarity signal C, a latch signal D, a load signal F, and a set / reset output signal G, and an overflow carry signal E is input from the counter 8.

The counter 8 counts the high speed clock H generated by the high speed clock generator 9 between set and reset, based on the load signal F and the set / reset output signal G.

The latch circuit 10 latches the number of clocks counted by the counter 8 based on the latch signal D.

The integrator 11 adds or subtracts the latched clock according to the addition / subtraction polarity signal C to integrate, and as a result, averages the phase error.

The D / A converter 12 converts the integrated digital value into an analog quantity.

The adder 13 adds the converted analog amount to the voltage output from the DC amplifier 5 to the voltage controlled oscillator 6 as an offset amount, and adjusts the voltage for controlling the voltage controlled oscillator 6.

In this configuration, the signal A obtained by 1/2 ⁿ (n is an integer) of the clock of the input frequency fi from the input terminal IN by the counter 1
And the output frequency f ₀ of the voltage controlled oscillator 6 at the counter 2
In the phase-locked circuit of the signal B that is 1/2 ^m (m is an integer) fi
When / 2 ⁿ = fo / 2 ^m , signal A and signal B are established after synchronization is established.
Are in phase with each other.

However, when the input frequency fluctuates to f _i + Δf (Δf is the input frequency fluctuation), the occurrence of the abnormal phase error causes a phase difference of Δθ = 2πΔf / K (Δθ is a phase error rad).

Therefore, the signals A and B are input to the selector 71 of the phase error detector 7, respectively. The selector 71 outputs the selected output state through the 1/2 frequency divider 73 to the addition / subtraction polarity signal C
Is operated in a feedback manner by selecting either the signal A or the signal B as the set pulse and the reset pulse of the set / reset circuit 72.

That is, to explain this in detail, as shown in FIG. 3, signals A and B when signal A is set and signal B is reset are selected.
The state of P is shown in the same figure, and the state of signals A and B when the signal B is set and the signal A is reset is shown in FIG. At this time, the output of the set / reset circuit 72 is in the state 1 for both P and Q, but in the initial state, the output signal of the 1/2 frequency divider 73 has two types of phase ambiguity: forward rotation and inversion. There is
As a result, the selection signal of the selector 71 also becomes indefinite, so it is indefinite which one becomes the set pulse or the reset pulse, and the output of the set / reset circuit may be in state 2. Therefore, in order to solve this, As shown in FIG. 4, the count value of the counter 8 has an upper limit, the count value when the counter 8 counts the high-speed clock H is compared with the upper limit value, and when the upper limit value is exceeded, the overflow carry signal E is used. Switch the selector 71 and set / reset circuit at the same time
By resetting 72 and the counter 8, the output of the set / reset circuit 72 can be always set to the state 1.

As a result of this selection, at the same time as the selection of the selector 71, the latch signal D and the load signal F are obtained by using the reset signal or the overflow carry signal E, respectively.
It is output to the counter 8. Also, a set / reset circuit
From 72, set / reset output signal G by set signal
Is obtained and output to the counter 8.

Then, if the counter 8 counts the high-speed clock H, the phase error can be obtained as a digital value.
Then, this digital value is input to the integrator 11, where addition or subtraction is performed based on the addition / subtraction polarity signal C. The integrator 11 retains the previous state and averages the digital value, that is, the phase error. And this integrator 11
The output is converted to an analog value by the D / A converter 12, and the adder 1
It is added to the output of the DC amplifier 5 at 3.

In the voltage controlled oscillator 6, the voltage corresponding to the phase error is controlled by the control voltage added as an offset, and its free-run frequency can be made to follow the input frequency fluctuation. This makes it possible to reduce the phase error to zero regardless of the frequency fluctuation of the input signal.

〔The invention's effect〕

As described above, the present invention provides a phase-locked circuit using a voltage-controlled oscillator, a phase error detector, a counter, an integrator, a D
Since an A / A converter and an adder are attached, the phase error due to the frequency fluctuation generated in the input signal is detected by the phase error detector, and this phase error is integrated with a digital value and converted into an analog quantity. Can be added to the control voltage of the voltage controlled oscillator above, which makes it possible to control the oscillation frequency of the voltage controlled oscillator according to the frequency fluctuations of the input signal, and realize phase synchronization with zero phase error. There is an effect that can be.

Also, in the phase error detector, the selector selects either the input signal or the output signal of the voltage controlled oscillator as the set signal or the reset signal, and sends the selected set signal and reset signal to the counter to output a digital value. , And at the same time, the latch signal, load signal, and add / decrease polarity signal are sent from the detector to the latch circuit, counter, and integrator, respectively. It is possible to accurately detect the phase error of the output signal and execute the above-mentioned phase synchronization with zero phase error with high accuracy.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a phase error detector, FIG. 3 is a signal waveform diagram showing an output state of a set / reset circuit, and FIG. 4 is a set / reset. FIG. 5 is a signal waveform diagram showing the principle for setting the output state of the circuit, and FIG. 5 is a block diagram of a conventional phase locked loop circuit. 1 ... Counter, 2 ... Counter, 3 ... Phase comparator,
4 ... Loop filter, 5 ... DC amplifier, 6 ... Voltage controlled oscillator, 7 ... Phase error detector, 8 ... Counter,
9 ... High-speed clock generator, 10 ... Latch circuit, 11 ...
Integrator, 12 …… D / A converter, 13 …… Adder, 71 …… Selector, 72 …… Set / reset circuit, 73 …… 1/2 divider, 74 …… OR gate, 75 …… Nand gate .

Claims (1)

[Claims] 1. A phase synchronization circuit that compares the phases of an input signal and an output signal of a voltage controlled oscillator, and controls the voltage controlled oscillator based on this phase difference, in a phase error between the input signal and the voltage controlled oscillator. A detector for detecting, a counter for detecting this phase error as a digital value by counting a high-speed clock, a latch circuit for latching this digital value, an integrator for integrating the latched digital value, and an integrated D / to convert digital value to analog
An A converter, and an adder that adds an analogized phase error to the control voltage of the voltage controlled oscillator as an offset amount, the detector of the phase error, the input signal and the output signal of the voltage controlled oscillator, A selector signal for selecting either a set signal or a reset signal, and an add / subtract polarity signal is generated based on an overflow carry signal output from the counter when the count value of the counter exceeds an upper limit, A 1/2 frequency divider that supplies the signal to a selector to perform selection by the selector, the overflow carry signal and the reset signal of the selector are used as reset inputs, and the set signal of the selector is used as a set input and a reset pulse is set. And a set / reset circuit for outputting a pulse to the counter, and the reset signal as a latch signal The load signal is output to the latch circuit, a load signal is generated based on the reset signal and the overflow carry signal, the load signal is sent to the counter, and the addition / subtraction polarity signal is sent to the integrator. A phase synchronization circuit.