JPH0783351B2 - Frame format data extraction circuit - Google Patents

Description

The present invention relates to a circuit for extracting data corresponding to a data type from frame format serial data in digital transmission, and is particularly suitable for extracting data from an arbitrary format. The present invention relates to a frame format data extraction circuit.

[Conventional technology]

In the past, for example, a reception end flag is generated every time one frame of n-bit received serial data is simply parallel-converted by one frame by the n-bit shift register, while the parallel-converted data corresponds to the data type. The flip-flops are provided so as to be transferred and stored in parallel. Note that, as a known document regarding this type of circuit, for example, "Revised Computer Data Communication Technology" (published by CQ Publishing Co., Ltd.
Page 1 of the 1st of the month (Revision 4))).

[Problems to be solved by the invention]

However, although the above-mentioned conventional technique is effective for the data of a specific frame format, it cannot deal with the data of the format when the frame formats are different. This is because, if the frame format is different, generally the position and the number of bits of the data corresponding to the data type are also different on the frame.

An object of the present invention is to provide a frame format data extraction circuit that can easily and easily extract data according to the data type even when the frame formats are variously different.

[Means for solving problems]

Since the purpose of the above is that the data type and the position of the data in each frame in each frame format are known in advance, this information is stored in the ROM corresponding to the frame format, and the transfer storage of the received serial data is performed. This is achieved by specifying the destination in bit units.

[Action]

Although the flip-flop as the data transfer storage destination is provided corresponding to the data type, the data of the same type is transferred and stored in the flip-flop corresponding to the data type even when the frame format is different. Since the data type and its position on the frame of the data in each frame format are known in advance, store the data in the flip-flop corresponding to the data type while the data of the data type is being received. It is all right.

〔Example〕

 The present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a configuration of an example of a frame format data extraction circuit according to the present invention, and FIG. 2 shows an operation timing chart of the example.

In FIG. 1, 1 is a frame detector that generates a reception synchronization pulse A3 indicating a frame start position from a frame search pattern bit in the reception data A1, and 2 is a bit counter that calculates the reception bit data based on the bit synchronization clock A2. Part 3, a format ROM for storing data designating a bit-corresponding D flip-flop to which each received bit data is to be written and data indicating the end of one frame reception in accordance with an external frame format designation signal A7, A decoder that selects a bit-corresponding D flip-flop by decoding the output data from the format ROM 3, 8 is an AND gate group that controls the supply of the bit synchronization clock A2 to the selected D flip-flop, a demultiplexer unit, and 9 is the received data Frame search pattern bit from A1 Is a data bit extraction unit, 11 is a control bit extraction unit, and 7 is a one-frame reception end flag generation unit indicating that the extraction of data for one frame has been completed.

Now, this operation will be described with reference to FIG. 2. First, at the start of data reception, the frame detection section 1 detects the frame head from the frame search pattern bits included in the received data A1 and indicates its position. Receive sync pulse
A3 is generated, and the bit counter unit 2 is initialized via the NOR gate 5. However, this reception synchronization pulse A3 is generated only once at the start of the reception operation.

From this point, the bit counter unit 2 starts the bit synchronization clock
The number of received data is started to be counted by A2, and the received bit address A4 is allocated in 1-bit units of received data in order from the first bit of the frame. In the format ROM3, the ROM data A5 is read from the address specified by the address A4 and the external format specification signal A7.
And the decoder 4 decodes it and outputs an enable signal to the AND gate group 8 as a gate control signal. The data sampling clock supplied to each bit-corresponding D flip-flop is the bit cycle clock A2 passed through the inverter 6, and which D flip-flop is supplied is determined by the logic of the enable signal and the synchronous clock A2. It depends on the product. As a result, the received data is allocated in 1-bit units to the D flip-flop corresponding to the bit specified by the ROM data A5, so that even if the frame format is different, the frame search pattern bits, data bits, and control data bits are extracted as search pattern bits. They are transferred and stored in the unit 9, the data bit extraction unit 10, and the control bit extraction unit 11, respectively.

As described above, the data is extracted in order from the first bit of the frame, and the flag generation data A6 is output from the frame format ROM 3 at the same time as the reception of the last bit of the frame. Therefore, this data A6 causes the bit counter unit 2 to pass through the NOR gate 5. Is initialized and a flag signal is generated from the flag generator 7 for the end of reception of one frame, the operation is repeated for the reception operation of the next frame.

Data conforming to several kinds of formats are written in the format compatible area in the format ROM 3 in advance. However, by switching the format designation signal 7 from the outside as the upper address signal, the data of any frame format is classified by its type. Can be extracted.

Although a frame search pattern bit is attached to the beginning of each frame, the one attached to the first frame is not extracted by the pattern bit extraction unit 9, and the ones associated with the second and subsequent frames are extracted. It is supposed to be done. That is, when receiving the Nth frame data, the N + 1th frame search pattern bit is extracted. By monitoring the bit pattern, the processing device can know whether or not the frame synchronization is lost.

〔The invention's effect〕

As described above, according to the present invention, there is an effect that data can be extracted for each data type even when the frame formats are variously different.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an example of a frame format data extraction circuit according to the present invention, and FIG. 2 is a diagram for explaining its operation timing. 1 ... Frame detection section, 2 ... Bit counter section, 3 ...
Format ROM, 4 Decoder, 8 AND gate group demultiplexer, 9 Search pattern bit extractor, 10 Data bit extractor, 11 Control bit extractor.

Claims (1)

[Claims] 1. A frame format data extraction circuit for extracting data corresponding to a data type from frame format data in which the position of the data type on the format and the number of bits of the data type are different for each frame format. A frame detection section for detecting a frame search pattern from the frame format data of the above, a bit counter section which is initialized at the time of frame detection and generation of a frame end signal, and counts a bit synchronization clock bit-synchronized with the frame format data, Data transfer storage that is read and accessed based on the count value as the lower address signal from the counter unit and the frame format signal as the upper address signal that is set from the outside and that is compatible with the frame format And a ROM in which the data for generating the frame end signal is stored in advance, a decoder for decoding the data transfer storage destination from the ROM, each bit constituting the decode output of the decoder, and the bit synchronization clock are logically A demultiplexer unit that generates a data set signal corresponding to a data transfer storage destination by multiplying, and a plurality of data type-corresponding data units that sequentially store the format data in bit units based on the data set signal from the demultiplexer unit. A frame format data extraction circuit configured to include at least a flip-flop and a frame end signal generation unit that generates a frame end signal based on generation data for generating a frame end signal from the decoder.