JPH0783384B2 - Method of generating adaptive level judgment voltage - Google Patents

Description

TECHNICAL FIELD The present invention relates to an adaptive level determination voltage generation method used for demodulating a digital signal that has passed through a transmission system in which a low frequency band is cut off.

(Prior Art) In recent years, there has been a demand for wireless transmission of digital signals. In particular, in the single channel per carrier system for mobile radio, a system that directly FM-modulates a binary digital signal and a binary digital signal is used to narrow the transmission bandwidth. , LPF) has been adopted such as FM modulation method after passing through. The method using a Gaussian filter as the LPF is a GMSK (Gaussian Filter Manipulated Minimum Shif).
t Keying) is a very narrow band modulation method.
There is also a method of converting a binary digital signal into a multi-valued signal, for example, a four-valued signal, and then performing FM modulation through an LPF.

As described above, any of the modulation methods can be considered as a binary or multivalued frequency modulated wave. Since these frequency-modulated waves include a DC component as is clear from the generation process, the DC component must be considered in all of the modulation process, transmission process, and demodulation process. However, transmission of this DC component is extremely difficult for the following two reasons.

(A) The transmission frequency and the reception frequency respectively fluctuate due to changes in environmental conditions such as temperature, and the relative shift appears as a shift in the DC potential during demodulation. In order to prevent the shift of the DC potential, a DC cutoff circuit is often inserted on the output side of the frequency discriminator of the receiver.

(B) Since it is necessary to switch the transmission frequency to use, a frequency synthesizer has been used in recent years to generate a carrier wave, but when FM modulation is applied to this, the circuit becomes extremely complicated if the DC component is taken into consideration.

A system that does not transmit a DC component is desired by the above use, but if the DC component is not transmitted, the center voltage of the demodulated signal may fluctuate on the receiving side and an error may occur in code determination. As a method of solving this problem, it is conceivable to reproduce the DC component on the receiving side. FIG. 2 is a block diagram showing an example of a direct current regeneration system, which uses a decision feedback system (see, for example, IEICE Technical Report 75 [51] (1975).
-6-25) IEICE p.93-94). In FIG. 2, 1 is an input terminal, 2 is a forward filter, 3 is an adder circuit, 4 is an identification circuit, 5 is a feedback filter, and 6 is an output terminal. The front filter 2 is a high-pass filter whose frequency characteristic is A (jω),
Assuming that the feedback filter 5 is a low-pass filter having a frequency characteristic of B (jω), the relationship of the expression (1) is established between these filters, and the low-pass component lost by the front filter 2 is a feedback filter. It is compensated by the output of 5.

A (jω) + B (jω) = 1 (1) Here, assuming that the front filter 2 is a first-order high-pass filter, its frequency characteristic A (jω) can be expressed by equation (2).

However, S = jω, ω = 2π ₀ , ₀ is the transmission clock frequency, and α is the ratio of the cutoff frequency of the high-pass filter to ₀ .

Therefore, the equation (3) can be obtained from the equations (1) and (2). That is, The feedback filter 5 is a primary low pass filter having the same cutoff frequency as the front filter 2.

FIG. 3 shows the waveform of each part of the block diagram shown in FIG. 2. (a) of (a) is the waveform of the input signal applied to the input terminal 1, and (a) of (a) is The output waveform of the front filter 2, (c) of (b) is the output waveform of the discrimination circuit 4,
(D) of (b) is an output waveform of the feedback filter. The output waveform of the adder circuit 3 is a waveform obtained by adding the output waveform (a) of the front filter 2 and the output waveform (d) of the feedback filter 5, which is the waveform of the input signal shown in (a) of (a). Therefore, a signal having the same waveform as the input signal, which is not affected by the characteristics of the front filter 2, is input to the identification circuit 4.

That is, even if there is a high-frequency wave characteristic in the transmission process including the modulation process and the DC component is lost, the DC component is regenerated by the above method to fix the center voltage of the demodulated signal, and the level is determined without error. be able to.

Further, (e) of FIG. 3 (a) shows the center level of the output waveform (a) of the front filter 2 shown in FIG. 2, and the level judgment can be performed using the same judgment level voltage as this center level. Thus, it is possible to make an error-free decision without being affected by the fluctuation of the central level. (F) of FIG. 3 (b) is an inversion of the output waveform (d) of the feedback filter 5,
The waveform of the center voltage of the output of the front filter 2 shown in (e) of (a) is the same. Therefore, as the judgment level voltage,
By inverting and using the output of the feedback filter 5, it is possible to perform error-free level determination without being affected by the center level fluctuation.

(Problems to be Solved by the Invention) However, in the above DC regeneration method, the amplitude of the input signal and the output amplitude of the discriminating circuit 4 need to be always equal as shown in the expression (1). Considering that it normally fluctuates, it is necessary to provide an automatic gain control (AGC) circuit to suppress the amplitude fluctuation. Moreover, since the AGC circuit must be capable of linearly adjusting the amplitude, the circuit becomes complicated and it cannot be applied when the input signal is multi-valued.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate these drawbacks and provide an adaptive level determination voltage generation method that easily responds to an amplitude fluctuation of an input signal and generates a judgment voltage that follows the fluctuation of the center voltage of the input signal. To do.

(Means for Solving the Problem) The present invention provides a method of generating an adaptive level determination voltage, which generates a determination voltage as a reference for determining the level of a digital input signal, in which the level value of the input signal is determined by a reproduced clock signal. , A voltage holding circuit corresponding to the level value is selected, the difference between the input signal and the reference voltage is held, an average level of absolute values of the voltages held in each voltage holding circuit is calculated, and the average level is calculated. Generating one or more levels of positive, negative voltage and zero voltage based on the above, selecting one of them according to the level value, passing through a low pass filter as the reference voltage, and holding the voltage. A method of generating an adaptive level voltage, which is characterized in that a determination voltage adapted to an input signal is generated based on a voltage held in a circuit and the reference voltage. A reference voltage that follows the fluctuation of the digital signal is generated, and the judgment voltage that is adapted to the fluctuation of the digital signal is generated by the digital signal and the reference voltage. Level judgment can be performed.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
Is an input terminal, 12 is a high-pass filter as a front filter, 1
3,16,19,36 are operational amplifiers that are voltage followers, 14,17 are switches, 15,18 are capacitors, 22 and 33 are inverting amplifiers with gain of 1, 23 and 24 are the same resistance value for averaging With a resistor, 25 is a judgment voltage generation circuit, 26, 27, 31 are analog comparators, 28 is a discrimination circuit, 29 is a logic circuit, 30 is an output terminal, 32 is a clock recovery / timing generation circuit, 34 is a discrimination circuit, A quantization level selection circuit that selects a quantization level opposite to the determination result of 28, and 35 is a low pass filter as a rear filter having the same cutoff frequency as the high pass filter 12.

As an example, it is assumed that the GMSK signal of Bb · T = 0.25 is applied to the input terminal 11. However, Bb is the bandwidth of the Gaussian filter used at the time of modulation, and T is the reciprocal of the bit rate of the digital signal. This GMSK signal has the eye pattern shown in FIG. 4 (a) and takes _three level values L ₁ , L ₂ and L ₃ at each nT (n is an integer and T is the reciprocal of the bit rate). The determination of L ₁ , L ₂ and L ₃ is performed by the determination voltage generation circuit 2
5. The analog comparators 26 and 27 and the discriminating circuit 28 carry out the process as follows. First, the judgment voltage generation circuit 25 determines the maximum level L ₁ of the input signal (the output level of the operational amplifier 16).
And the center level L ₂ (the output level of the operational amplifier 36), the center voltage L _a of L ₁ and L ₂ is generated, and the center level L ₂ of the input signal and the lowest level L ₃ (the output level of the operational amplifier 19) ) And the central voltage L _b between L ₂ and L ₃ is generated.

FIG. 6 shows an embodiment of the judgment voltage generating circuit 25.
Terminals 25-1, 25-5, 25-9 are operational amplifiers shown in Fig. 1, respectively.
It is connected to each output side of 16, 19 and 36, and the voltages of levels L ₁ , L ₃ and L ₂ are input respectively. Terminal 25-3,25-7 are respectively connected to the analog comparators 26, 27 shown in FIG. 1, the determination voltage L _a, L _b is output. Since the resistors 25-2, 25-4, 25-6, 25-8 all have the same resistance value R, the judgment voltage
L _a and L _b are the voltage at the center of levels L ₁ and L ₂ , respectively, and level L ₂
And the central voltage of L ₃ . Therefore, the judgment voltages L _a and L _b change following the levels L ₁ , L ₂ and L ₃ of the input signal.

Analog comparator 26 outputs a digital signal "0" when the digital signal "1" when the input signal exceeds a L _a the L _a a determination voltage, does not exceed. On the other hand, the analog comparator 27 outputs a digital signal "0" when the digital signal "1" when the input signal exceeds a L _b the L _b as a determination voltage, does not exceed. Discrimination circuit 28
Indicates that the level of the input signal is L ₁ , L ₂ or L from the combination of the digital signals output from the analog comparators 26 and 27.
Determine which of the _three applies. For example, if the output from the analog comparator 26 is “0” and the output from 27 is “1”, the level of the input signal corresponds to L ₂ .
Based on the determination result of the determination circuit 28, the logic circuit 29 outputs “1” when the input signal is L ₁ , “0” when the input signal is L ₃ , and “1” from the past level transition when it is L _2. "" Or "0" is determined and output to the output terminal 30.

On the other hand, a voltage of level L ₂ output from the operational amplifier 36 is applied to the analog comparator 31 as a determination voltage, and when an input signal is applied, a digital signal “1” is output when the input signal exceeds L ₂ . If it does not exceed, it outputs digital signal "0". The clock reproduction / timing generation circuit 32 receives the output of the analog comparator 31 and generates a reproduction clock signal as shown in FIG. 4 (b), and at the same time, raises the reproduction clock signal as shown in FIG. 4 (c). To generate a sampling pulse delayed by time t. As shown in FIG. 4, this sampling pulse is almost synchronized with the portion where the three values of the eye pattern of the input signal are concentrated.
The discriminating circuit 28 discriminates whether the input signal level corresponds to L ₁ , L ₂ or L ₃ based on the digital signals from the analog comparators 26 and 27 at the rising edge of the reproduced clock signal shown in FIG. 4 (b). However, when L ₁ is applied, the sampling pulse is applied to the switch 14, when L ₃ is applied, it is added to the switch 17, and when L ₃ is applied, it is not applied to any of the switches 14 and 17. The sampling pulse is shown in FIG. 4 (c).
As shown in FIG. 5, the reason why the rising of the reproduction clock signal is delayed by the time t is that the time required for the judging circuit 28 to carry out the judging operation is taken into consideration. Therefore, the capacitor
Reference numeral 15 holds the voltage difference between the input signal level L ₁ and the output level L ₂ from the operational amplifier 36, and capacitor 18 holds the difference voltage between the input signal level L ₃ and the L ₂ . The voltages held by the capacitors 15 and 18 are superimposed on the output voltage from the operational amplifier 36 and input to the operational amplifiers 16 and 19, respectively. The outputs of the operational amplifiers 16 and 19 are added and averaged by the inverting amplifier 22 and the resistors 23 and 24, and added to the terminal a of the computerization level selection circuit 34, and also to the terminal b via the inverting amplifier 33. Therefore, to the input side of the quantization level selection circuit 34, a voltage that is 1/2 the difference between the maximum value L ₁ and the minimum value L ₃ of the input signal level is applied,
This voltage matches the voltage of the difference between the levels L ₁ and L ₂ of the input signal and the voltage of the difference between L ₂ and L _3, and changes following the level change of the input signal. Quantization level selection circuit 34 based on an instruction determination circuit 28, the contact point a when該判filter circuit 28 to the contact b when the level of the input signal is determined as L _1, is determined as L _3, L ₂
When it is determined that the contact point c is selected, it is connected to the output side.
The contact c is connected to the ground. The output of the quantization level selection circuit 34 is applied to one ends of the capacitors 15 and 18, the decision voltage generation circuit 25 and the analog comparator 31 via the low pass filter 35 and the operational amplifier 36, respectively. The above operation is shown in FIG. When the input signal shown in (a) of FIG. 5 (a) is applied to the input terminal 11, the high-frequency wave filter 12 causes the center level to fluctuate as shown in (c) of (a). B) is output. On the other hand, the quantization level selection circuit 34 quantizes the (+) voltage, the (-) voltage, and the zero voltage having the value of 1/2 of the difference between the levels L ₁ and L ₃ corresponding to the input signal level. The waveform is the fifth
It becomes as shown in FIG. The output of the quantization level selection circuit 34 is input to the low pass filter 35,
The voltage of the waveform shown in (e) of FIG. 5 (b) is output from 35. The output waveform (b) of this low-pass filter 35 (e)
Is the high-frequency wave filter 12 regardless of fluctuations in the input signal level.
(C) of the output center level (a), which is used as a reference voltage when the determination voltage is generated. As described above, according to the present embodiment, since the determination voltage that follows the amplitude variation and the center level variation of the input signal is generated and the level determination is performed, the accurate level determination can be performed without using the AGC circuit. You can

In the present embodiment, the case where the low frequency characteristics including the transmission system are determined by the high frequency wave filter 12 has been described as an example, but the high frequency wave filter 12 is omitted and the cutoff frequency of the low frequency wave filter 35 is omitted. The same effect as in the present embodiment can be obtained even when is determined in accordance with the high frequency characteristics of the transmission system.

Further, the present embodiment can be similarly applied to the case where the digital signal is multi-valued such as binary or ternary.

(Effects of the Invention) As described in detail above, according to the present invention, in the level determination of the digital signal in which the low-frequency component is cut off, the determination voltage is generated in accordance with the level of the input signal.
It is not necessary to use the AGC circuit, and it is possible to perform level determination that is not affected by the level fluctuation of the input signal and the center level fluctuation.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a conventional level determination method, FIG. 3 is a signal waveform diagram of each part of FIG. 2, and FIG. 4 is an explanatory diagram of timing signals of FIG. Figure 5 shows the first
FIG. 6 is a diagram of the signal waveform of each part in the figure, and FIG. 11 …… Input terminal, 12 …… High-frequency wave filter, 13,16,19,36 ……
Operational amplifier, 14,17 ... Switch, 15,18 ... Capacitor, 22,33 ... Inversion amplifier, 23,24 ... Resistor, 25 ... Judgment voltage generation circuit, 26,27,31 ... Analog comparator ,
28 …… discrimination circuit, 29 …… logic circuit, 30 …… output terminal, 32
...... Clock regeneration / timing generation circuit, 34 …… Electronic level selection circuit, 35 …… Low-pass filter.

Claims (3)

[Claims] 1. A method of generating an adaptive level judgment voltage for generating a judgment voltage as a reference for level judgment of a digital input signal, wherein a level value of the input signal is judged by a reproduced clock signal, and a voltage corresponding to the level value is judged. A holding circuit is selected, the difference between the input signal and the reference voltage is held, the average level of the absolute value of the voltage held in each voltage holding circuit is calculated, and one or a plurality of values are calculated based on the average level. Voltages held in the voltage holding circuit are generated by generating positive and negative levels of voltage and zero voltage, selecting one of them according to the level value, passing through a low-pass filter to be the reference voltage. And a method for generating an adaptive level voltage, wherein a determination voltage adapted to an input signal is generated based on the reference voltage. 2. The adaptive level judgment voltage generating method according to claim 1, wherein a high-pass filter having the same cutoff frequency as that of the low-pass filter is provided on the input side. 3. The adaptive level judgment voltage generating method according to claim 1, wherein the cutoff frequency of the low-pass filter is matched with the cutoff frequency of the high-pass filtering characteristic of the transmission system.