JPH0783439B2 - Video signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for converting a video signal into a digital video signal by an analog / digital converter and then performing digital signal processing using an image memory. In particular, the present invention relates to a video signal processing device for making a quantization error associated with analog / digital conversion inconspicuous visually.

2. Description of the Related Art In recent years, due to the rapid development of semiconductor technology, large-scale digital circuit LSIs, high-speed analog / digital converters (hereinafter abbreviated as A / D converters) that can operate at video rates, and digital / analog converters are available. (Hereinafter, abbreviated as D / A converter) has become feasible, and digital signal processing for consumer video equipment has become feasible.

Digitization of TV receivers and video tape recorders, which are consumer video equipment, has improved basic performance, efficient connection with new media equipment, stable quality uniformity, reduction of the number of parts, service efficiency, etc. In addition, in recent years, digital application equipment with various mechanical characteristics such as screen stillness, parent-child screen (picture-in-picture), multi-screen, etc. has been developed by adopting digital memory and memory control with remarkable increase in capacity and low price. ("TV Technology" 1986, VOL34, P19).

FIG. 4 shows an example of a digital video signal processing device using an image memory. In the figure, 1 is a video signal input terminal, 2
Is a clock generator, 3 is a clamp circuit, 4 is an A / D converter, 6 is an image memory, 7 is a memory control unit, 8 is a microcomputer for giving commands or data to the memory control circuit, 9 Is a digital / analog converter (hereinafter abbreviated as D / A converter), and 10 is a video signal output terminal.

The operation of the digital video signal processing device configured as described above will be described below.

First, the tip of the horizontal synchronizing signal of the input video signal input to the video signal input terminal 1 is fixed in a predetermined position by the clamp circuit 3, converted into a digital signal by the A / D converter 4, and written in the image memory 6. At this time, control of the write address, the read address, and the timing of writing and reading of the image memory 6 is performed by the memory control unit 7, and the memory control unit 7 controls the memory to synthesize images, thin out image data, and change the time axis. Various functions such as removal of the minutes can be realized. The data sent from the microcomputer (hereinafter abbreviated as “microcomputer”) 8 is for transmitting the mode command for selecting the above-mentioned various functions and the data such as address designation on the memory to the memory control unit 7. so,
Combinations of various functions, selection, connection with other devices, etc. can be changed and specified by software. The digital signal that has undergone various conversion processes in the image memory 6 is D /
It is converted into an analog video signal by the A converter 9 and output to the video signal output terminal 10.

In FIG. 4, the clock generation circuit 2 has A / D converters 4, D
In addition to generating the sampling ring clock of the / A converter 9, it also serves as a reference clock for generating various timing pulses for writing and reading timing of the image memory 6 and transfer of digital data. The clock frequency is
Generally, the horizontal synchronizing signal in the input video signal is frequency-divided by a predetermined frequency division ratio, or is multiplied by 3 to 4 in synchronization with the carrier color subcarrier (burst signal) included in the input video signal. Things are used.

With the above configuration, it is possible to digitize a video signal and store it in a memory, and it may have functions such as staticizing an image, synchronizing with an input image of another system, reducing or enlarging an image. Although it is possible, it causes the image quality deterioration peculiar to digital images when A / D conversion and D / A conversion of video signals.

As is well known, the most representative image quality deterioration due to digitization is a quantization error, and the quantization error correlates in the video signal portion where the gradation actually changes gradually. Mochi, where the quantization level changes, a contour like a contour line of a map is seen, and this is called false contouring ("Digital image signal processing" by Takahiko Fukibe, Nikkan Kogyo Shimbun). , P7
7).

For example, when a video signal as shown in FIG. 5 (a) is quantized, a stepwise waveform as shown in FIG. 5 (b) is obtained, and the quantization error is a two-dimensional low frequency component (low frequency space) with high visual sensitivity. Frequency component), which is recognized as a static false contour component on the screen. When all the video signals in one frame have the ramp waveform of FIG. 5 (a), the quantized signal (FIG. 5 (b)) is observed on the TV screen, and the alternate long and short dash line of FIG. 5 (e) is used. Vertical stripes like A are seen, which is visually unfavorable.

It is said that the above false contour cannot be visually detected if the quantization bit number is 7 bits, but at least 8 bits are required to realize a large number of arithmetic processes, high image quality, and the like. . Therefore, generally, in order to perform high-quality digital processing, the number of quantization bits needs to be 8 bits or more.

Problems to be Solved by the Invention However, selecting the number of quantization bits of 8 bits or more in the above-mentioned configuration increases the image memory,
This leads to complication of the memory control unit, cost increase of A / D, D / A converters, etc. It is common to perform 6 to 7 bit digital processing in the current consumer equipment. There was a problem that image quality deterioration such as S / N deterioration occurs.

In view of the above problems, the present invention makes it possible to visually make the false contour phenomenon caused by quantization inconspicuous and substantially obtain the same image quality as when the number of quantization bits is increased by 1 bit. The present invention provides a simple video signal processing device.

Means for Solving the Problems In order to solve the above problems, a video signal processing device of the present invention converts an input video signal into a digital signal by an analog / digital converter, and then performs digital signal processing using an image memory. In the video signal processing device for performing, a horizontal sync separation circuit that separates a horizontal sync signal from the input video signal, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit into 1/2, When the output pulse of the 1/2 frequency divider is high level, the input video signal is clamped to the first clamp voltage, and when the output pulse of the 1/2 frequency divider is low level, it is clamped to the first clamp voltage. In comparison with a clamp circuit configured to clamp the input video signal to a second clamp voltage that is higher or lower by a voltage equivalent to 1/2 of the least significant bit at the time of analog / digital conversion. , And an analog / digital converter for converting the output of the clamp circuit into a digital signal.

Effect The present invention has the above-described configuration, and the first clamp voltage and the second clamp voltage differ by the input voltage corresponding to 1/2 of the least significant bit (LSB) as the clamp voltage of the video signal before A / D conversion. Two types of clamp voltages are set, and a control pulse obtained by dividing the horizontal synchronizing signal is used to alternately clamp the above two types of clamp voltages for each horizontal scanning period. That is, the input video signal in the first horizontal scanning period is
The input video signal clamped at the first clamp voltage and in the next second horizontal scanning period is more than the first clamp voltage.
The input video signal is clamped to the second clamp voltage which is higher (or lower) by 1/2 LSB, and the input video signal is 1 / every horizontal scanning period.
DC shift of 2LSB is applied.

By the clamp operation described above, the threshold level of the voltage comparator during A / D conversion rises and falls by 1/2 LSB for each horizontal scanning period, so that the false contour phenomenon described above becomes noticeable Even when a signal is input, the false contour generation position alternately changes every horizontal scanning period, and the false contour generation of the video signal after D / A conversion is visually doubled as a two-dimensional frequency (spatial frequency). It becomes unnoticeable.

Further, in addition to the control of the clamp voltage described above, the image data of the A / D converter is led to a line memory configured to delay by one horizontal scanning period (hereinafter, abbreviated as 1H delay),
The image data before 1H delay and the image data after 1H delay are compared, and when both image data are almost the same, that is, when both image data have line correlation, 1H delay before and 1H The image data after the delay is averaged (smoothed), and it is possible to substantially improve the number of quantization bits by one bit. This makes it possible not only to make false contours visually inconspicuous but also to improve the S / N ratio including quantization noise.

Example An image signal processing apparatus according to an example of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main blocks of a video signal processing apparatus according to the first embodiment of the present invention. 1 in FIG.
Is an input terminal, 2 is a clock generation circuit, 4 is an A / D converter,
6 is an image memory, 7 is a memory controller, 8 is a microcomputer, 9 is a D / A converter, 10 is an output terminal, 21 is a clamp voltage control circuit, 22 is a horizontal sync separation circuit, and 23 is a clamp circuit.

The operation of the video signal processing device configured as described above will be described below with reference to FIGS. 1 and 5.

First, the horizontal sync signal in the video signal input to the input terminal 1 in FIG. 1 is separated by the horizontal sync separation circuit 22, the horizontal sync signal is divided by 1/2 by the clamp voltage control circuit 21, and the first A control pulse having a cycle twice as long as that of the horizontal scanning period is generated so that the level is high during one horizontal scanning period and low during the next horizontal scanning period.

Further, the control pulse generated by the clamp voltage control circuit 21 is supplied to the clamp circuit 23, in which the input video signal is clamped by the first clamp voltage V ₁ when the control pulse is at a high level, and the control pulse is At low level, the clamp voltage is higher (or lower) by the input voltage corresponding to 1/2 of the least significant bit (LBS) than the first clamp voltage.
Clamp the input video signal with V ₂ . This allows
The video signal from the clamp circuit 23 is 1 / 2L every horizontal scanning period.
A / D converter 4 clamped with a DC voltage difference equivalent to SB
Is supplied to.

The A / D converter 4 samples the video signal according to the clock pulse generated by the clock generation circuit 2 and further converts it into a digital signal. At this time, the video signal input to the A / D converter 4 is 1 / 2LS of the comparison voltage of the A / D converter 4.
Since the signal is DC-shifted and clamped by the amount corresponding to B for each horizontal scanning, the sampling waveform changes alternately every horizontal scanning period.

This will be described with reference to FIG. FIG. 5 (a) shows an input video signal, which is clamped by the clamp circuit 23 and then sampled by the A / D converter 4, and it is ascertained that it is clamped at the clamp voltage V ₁ in the first horizontal scanning period. For example, the video signal after sampling is as shown in FIG.

In the next one horizontal scanning period, the video signal is controlled by the clamp voltage control circuit 21 and clamped to the clamp voltage V ₂ (V ₁ <V ₂ ), so that the video signal after sampling is as shown in FIG. 5 (c). Then, the video signal is sampled in a form shifted upward by 1/2 LSB as compared with the video signal (FIG. 5 (b)) one horizontal scanning period before. As described above, the feature of the video signal processing device of the present invention is that the sampling points are sampled up and down in the amplitude direction by an amount corresponding to 1/2 LSB in each horizontal scanning period.

The video signal sampled as described above is A / D
After being further encoded by the converter 4 and converted into a digital signal, it is written in the image memory 6 based on the write timing controlled by the memory control section 7 described above, and the mode designated by the microcomputer 8 by address control or the like. Image data processing is performed. After predetermined image data processing is performed by the image memory 6, the memory control unit 7, and the microcomputer 8, the image data is read based on the read timing and converted into an analog video signal by the D / A converter 9.

As described above, according to the present embodiment, each horizontal scanning period of the video signal before A / D conversion is clamped to a clamp voltage different by 1/2 LSB, so that a false contour generated at the time of quantization is generated. The phenomenon can be made visually inconspicuous.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram of a video signal processing device showing a second embodiment of the present invention. The difference from the configuration of FIG.
Although the false contour phenomenon described above is made inconspicuous by switching the clamp voltage of the clamp circuit 23 every horizontal scanning period in the figure, the clamp voltage of the clamp circuit 3 is fixed in FIG. The pseudo-contour phenomenon is made inconspicuous by raising and lowering the comparison voltage used during conversion by 1/2 LSB each horizontal scanning period. That is, in FIG. 2, the video signal clamped to a predetermined voltage by the clamp circuit 3 is converted into a digital signal by the A / D converter 4. At that time, the horizontal sync separation circuit 23 described above is used. The horizontal sync signal, which is the output of, is divided by 1/2 by the comparison voltage control circuit 24, and the comparison voltage of the comparison voltage generation circuit 25 is set higher by 1/2 LSB when the output pulse is high level than when it is low level. Then, the comparison voltage value of the comparison voltage generation circuit 25 is controlled so as to perform A / D conversion. As a result, the same effect as that of the first embodiment can be obtained.

As described above, the first embodiment and the second embodiment can obtain the same effect in terms of making the false contour phenomenon inconspicuous, but further make the false contour phenomenon inconspicuous and S / N
In order to improve the ratio, the third embodiment as shown in FIG. 3 is effective.

The third embodiment of the present invention will be described below with reference to FIG. In the figure, 1 is an input terminal, 2 is a clock generator, 3 is a clamp circuit, 4 is an A / D converter, 6 is an image memory, 7 is a memory controller, 8 is a microcomputer, and 9 is a D / A.
A converter, 10 is an output terminal, 22 is a horizontal sync separation circuit, 24 is a comparison voltage control circuit, and 25 is a comparison voltage generation circuit.
The configuration is similar to that shown in the figure. The difference from the configuration of FIG. 2 is that a line memory 27, a line correlation detection unit 29, and a calculation unit 28 are provided after the A / D converter 4, and the line memory 27
The point is that the line memory control unit 26 is provided for the control of.
Here, the line memory 27 is a digital memory capable of delaying only one horizontal scanning period, and a signal obtained by delaying the digital video signal after A / D conversion by one horizontal scanning period by the line memory 27 and a signal before the delay are subjected to line correlation. The line correlation amount between both signals is detected by inputting to the detection unit 29 and detecting the difference between both signals. When the line correlation amount is large, that is, when the signal before one horizontal scanning period and the current signal are almost the same, both signals are added by the arithmetic unit 28, the average value thereof is taken and output to the image memory 6, When the correlation is small, that is, when the signal before one horizontal scanning period and the current signal are different,
In the calculation section 28, the output signal of the A / D converter 4 is directly output to the image memory 6.

By performing the above operation, if the line correlation amount is large, the adjacent horizontal scanning lines are averaged (smoothed), and the sample points during A / D conversion described above are set to 1 per flat scanning period. This embodiment 1, in which the amount of movement is equivalent to / 2 LSB,
Alternatively, the number of quantization bits is visually increased by one bit in combination with the operation described in 2. For example, considering the video signal of FIG. 5 (a) having line correlation,
As described above in the first or second embodiment, the video signal sampled by the A / D converter 4 is as shown in FIG. 5 (b) in the first horizontal synchronization period, and the next horizontal synchronization period. Then, it becomes as shown in Fig. 5 (c).
After the digital averaging processing between the lines is performed by the and calculation unit 28, the analog signal is converted by the D / A converter 9 as shown in FIG. 5 (d). The width is doubled, which means that the number of quantization bits has increased substantially by 1 bit. As a result, the false contour phenomenon becomes inconspicuous, the quantization noise is reduced, and the S / N ratio is improved.

In the third embodiment, the line memory 27, the line correlation detector 29, and the calculator 28 are described as digitally processing after A / D conversion. However, analog processing is performed after A / D conversion. You may. In that case, the line memory 27 needs to use a CCD or the like which is an analog delay element.

In addition, the clamp voltage control circuit 21 in the first embodiment
And the comparison and comparison voltage control circuit 24 in the second embodiment,
The frequency divider for dividing the horizontal synchronizing signal has been described, but any frequency divider can be used as long as it can switch the clamp voltage or the comparison voltage of the A / D converter for each horizontal scanning period.

EFFECTS OF THE INVENTION As described above, according to the present invention, a clamp circuit configured to clamp a voltage different by 1/2 LSB for each horizontal scanning period, and a horizontal synchronization signal for controlling the clamp circuit By providing a / 2 frequency divider to make the false contour phenomenon caused by quantization error inconspicuous, and when the line correlation detector that detects the line memory and line correlation amount and the line correlation amount become large. By adding an arithmetic unit configured to take an arithmetic mean between lines, the same effect as a 1-bit increase in the number of quantization bits is obtained, and the S / N ratio is improved. Can be planned.

[Brief description of drawings]

1 is a block diagram of a video signal processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a video signal processing device according to a second embodiment of the present invention, and FIG. 3 is a block diagram of the present invention. 3 is a block diagram of a video signal processing device according to the third embodiment, FIG. 4 is a block diagram of a conventional video signal processing device, and FIG. 5 is an explanatory diagram. 21 …… Clamp voltage control circuit, 22 …… Horizontal sync separation circuit, 23 …… Clamp circuit, 24 …… Comparative voltage control circuit, 25
…… Comparison voltage generation circuit, 26 …… Line memory control unit,
27 …… Line memory, 28 …… Calculator, 29 …… Line correlation detector.

Claims (4)

[Claims] 1. A video signal processing apparatus for converting an input video signal into a digital signal by an analog / digital converter and then performing digital signal processing using an image memory, wherein a horizontal synchronizing signal is separated from the input video signal. Horizontal sync separation circuit, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit by 1/2, and a first clamp when the output pulse of the 1/2 frequency divider is at a high level. When the input video signal is clamped to a voltage and the output pulse of the 1/2 frequency divider is at a low level, the voltage of 1/2 of the resolution voltage width at the time of analog / digital conversion is compared with the first clamp voltage. A clamp circuit configured to clamp the input video signal to a second clamp voltage that is higher or lower by the amount, and an analog / digital converter for converting the output of the clamp circuit into a digital signal. A video signal processing apparatus characterized by having a transducer. 2. A video signal processing device for converting an input video signal into a digital signal by an analog / digital converter and then performing digital signal processing using an image memory, wherein a horizontal synchronizing signal is separated from the input video signal. Horizontal sync separation circuit, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit by 1/2, and a first clamp when the output pulse of the 1/2 frequency divider is at a high level. When the input video signal is clamped to a voltage and the output pulse of the 1/2 frequency divider is at a low level, the voltage of 1/2 of the resolution voltage width at the time of analog / digital conversion is compared with the first clamp voltage. A clamp circuit configured to clamp the input video signal to a second clamp voltage that is higher or lower by the amount, and an analog / digital converter for converting the output of the clamp circuit into a digital signal. A converter, a line memory configured to delay the output of the analog / digital converter by one horizontal scanning period, and a line correlation detection for detecting a correlation amount between the output of the line memory and the output of the analog / digital converter. And an arithmetic unit configured to take an arithmetic mean of the output of the analog / digital converter and the output of the line memory when the line correlation detection output is large. A video signal processing device comprising: 3. A video signal processing apparatus for converting an input video signal into a digital signal by an analog / digital converter and thereafter performing digital signal processing using an image memory, in which a horizontal synchronizing signal is separated from the input video signal. A sync separation circuit, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit by 1/2, a clamp circuit that clamps the input video signal to a predetermined voltage, and the 1/2
When the output pulse of the frequency divider is at high level, the above analog /
When the first comparison voltage is used as the comparison voltage of the digital converter and the output pulse of the 1/2 frequency divider is at a low level, the comparison voltage of the analog / digital converter is set to the resolution voltage width at the time of analog / digital conversion. An analog / digital converter for converting the output of the clamp circuit into a digital signal by using a second comparison voltage which is higher or lower by 1/2 voltage. 4. A video signal processing apparatus for converting an input video signal into a digital signal by an analog / digital converter and thereafter performing digital signal processing using an image memory, in which a horizontal synchronizing signal is separated from the input video signal. A sync separation circuit, a frequency divider that divides the horizontal sync signal output from the horizontal sync separation circuit by 1/2, a clamp circuit that clamps the input video signal to a predetermined voltage, and the 1/2
When the output pulse of the frequency divider is at high level, the above analog /
When the first comparison voltage is used as the comparison voltage of the digital converter and the output pulse of the 1/2 frequency divider is at a low level, the comparison voltage of the analog / digital converter is set to the resolution voltage width at the time of analog / digital conversion. An analog / digital converter that converts the output of the clamp circuit into a digital signal by using a second comparison voltage that is higher or lower by 1/2 voltage, and delays the output of the analog / digital converter by one horizontal scanning period. The line memory configured to operate, the line correlation detector that detects the correlation amount between the output of the line memory and the output of the analog / digital converter, and the line correlation detection output increase the line correlation voltage. In some cases, it has an arithmetic unit configured to take an arithmetic mean of the output of the analog / digital converter and the output of the line memory. That the video signal processing apparatus.