JPH0783513B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a semiconductor memory device, and more particularly to a time switch memory (TSW) device relating to multiplex communication such as a communication path of a telephone exchange, by devising a method of supplying a write command. The purpose is to insert a random write into the memory during sequential read with a simple configuration, and to prevent unintended data from being inserted into the data during sequential read (to ensure continuity of read data). The first storage means for sequentially reading the data randomly written based on the write instruction and the random address based on the sequential address, and the write instruction and the random instruction during the period during which the first storage means is sequentially read. Randomly write data based on the address and the first storage means runs. When the random write and the sequential address are compared with each other by comparing the second storage means for sequentially reading the randomly written data based on the sequential address during the mullite writing, when the both addresses match, an address match signal is issued. An address comparison unit that is generated and a write command control unit that outputs a write command that inserts a random write into either the first or second storage unit during the sequential read according to the address match signal from the address comparison unit. Prepare

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a time switch memory device (time division converter: hereinafter referred to as TSW device) related to multiplex communication such as a communication path of a telephone exchange.

[Prior art]

4 and 5 are explanatory views according to a conventional example. FIG. 4 is a schematic explanatory diagram of time division exchange of a TSW device according to a conventional example, and FIG. 5 is a diagram in which a control memory according to the conventional example has two banks. For example, as shown in FIG. 4, a TSW device applied to multiplex communication such as a communication path of a telephone exchange has a time switch memory (hereinafter referred to as TSW memory) 101, a control memory 103 and a sequential counter 1
Equipped with 05. The TSW memory is connected to the input highway 102 and the output highway 103. The input highway 102 is a line for transmitting call data from a telephone subscriber, and the output highway 103 is a line for transmitting time-division exchanged call data.

The function of the TSW device is, for example, time slots t0, t1, t
When the input highway 102 is occupied by four subscribers at a time (time division) corresponding to 2, t3, and the call data A, B, C, D are transmitted at this time, When this call data A, B, C, D is time-division exchanged and transmitted to the output highway 103, a random address corresponding to the time slot t0, t1, t2, t3 is transmitted from the control memory 103 to the TSW memory 101.
Is output to.

That is, regarding the operation of writing the call data in the TSW memory 101, the address = 2 is read from the storage address # 0 of the control memory 103 at the time corresponding to the time slot t0.
This address = 2 is output to the TSW memory 101. Similarly, at the time corresponding to the time slot t1, the storage address #
Address = 1 is read from 1 and address = 3 is read from storage address # 2 at the time corresponding to time slot t2. Address = 3 is read from storage address # 3 at the time corresponding to time slot t3. 0 is read. These addresses = 2, 1, 3, 0 are output to the TSW memory 101.

In the TSW memory 101, the call data D is written in the designated address # 0 designated by the control memory 103. Similarly, the data B is written in the storage address # 1, the data A is written in the storage address # 2, and the data C is written in the storage address # 3. As a result, the TSW memory 101 can store the call data at the address specified by the control memory 104.

When the call data is read from the TSW memory 101, the storage address # 0 is selected by the sequential counter 105 at the time corresponding to the time slot t0, and the call data D is read. Similarly, at the time corresponding to the time slot t1, the storage address # 1 is selected, the call data B is read, and at the time corresponding to the time slot t2,
Stored address # 2 is selected, call data A is read,
At the time corresponding to the time slot t3, the storage address # 3 is selected and the call data C is read. These time division data D, B, A, C are transmitted to the output highway 103. The time-division data D, B, A, C are for four subscribers α,
It is transmitted to β, γ, and δ.

As a result, the line between the subscribers A-γ, B-β, C-δ, and D-α is connected, and the signal of the subscriber A is transmitted to the subscriber δ.
In addition, the others can be similarly transmitted. The control memory 104 stores each # specified in each time slot t0 to t3.
Random addresses of addresses 0 to # 3 = 2, 1, 3, 0 are held until the end of the call.

[Problems to be solved by the invention]

Therefore, in order to secure the subscriber's channel until the end of the call, the control memory 104 does not continuously output addresses for random writing of call data and random reading of time division data to the TSW memory 101. Don't let it go.

Normally, the addresses are sequentially read from the control memory 104 to the TSW memory 101. However, when a new call is made, the connection destination information of the call partner is stored in the control memory 10.
You need to write to the corresponding address of 4. Control memory 104
Request to write occurs when a new call is made,
This new call is totally random when and when it happens.

Therefore, each time a new call is made,
The read request cannot be canceled and the write request cannot be executed. If this writing is intentionally executed, the reading order will be different or a gap will be created in the read data, making it impossible to secure a normal call. In this way control memory 104
The reading of addresses from must be continuous.

Next, with reference to FIG. 3B, a specific example of the case where the reading is stopped and the writing is executed will be described. FIG. 3 is a block diagram of a semiconductor memory device according to the related art of the present invention. For example, the applicant filed on the same day (Japanese Patent Application
No. 62-217510), the time switch memory as seen in the semiconductor memory device is, as shown in FIG. 1A, a D-type flip-flop circuit 1a, 1b, 2a to 2c, 4a, a counter 1c,
Selectors 3a, 3b, address selectors 5a-5c, RAMs (writable and readable memory at any time) 6a, 6b, predecoders 7a, 7b,
The clock generation circuit 8 and the control circuit 9 are provided.

The D-type flip-flop (hereinafter referred to as DFF) circuit 1a latches the input data Din (8 bits) in synchronization with the rising edge of the clock signal (hereinafter referred to as CLK signal), and the data D
Output IN. DFF1b is the input random address ra (10bi
t) is latched in synchronization with the rising edge of the CLK signal, and the random address RA is output to the selectors 5a and 5b, respectively.

The counter 1c inputs the clear signal fc, counts the CLK signal, and outputs the sequential address SA to the address selectors 5a and 5b.

The address selector 5a is a random address RA latched in DFF1b or a sequential address from the counter 1c.
SA is selected according to the control signal c1 from the control circuit 9, and the address RA or SA is output to the predecoder 7a. Similarly, the address selector 5b selects the random address RA or the sequential address SA according to the control signal c2, and
RA or SA is output to the predecoder 7b.

The predecoder 7a predecodes the address RA or SA,
Output to predecoded address RA or DFF2b.
The predecoder 7b predecodes the address SA or SA,
The predecoded address SA or SA is output to DFF2c.

The DFF2a latches the data DIN in synchronization with the rising edge of the CLK signal. The DFF 2b latches the predecoded address RA or SA in synchronization with the rising edge of the CLK signal, and outputs the address (# 1) to the RAM 6a. The DFF 2c latches the predecoded address RA or SA in synchronization with the rising edge of the CLK signal, and outputs the address (# 2) to the RAM 6b.

The RAM 6a has a write command W (# 1) and an address A (#
The data DIN is written according to 1) and the data D (# 1) is read according to address A (# 1). RAM6b has write command W (# 2) and address A
The data DIN is written according to (# 2) and the data D (# 2) is read according to address A (# 2).

The DFF 3a latches the data D (# 1) in synchronization with the rising edge of the CLK signal. Similarly, DFF3b converts data D (# 2) to C
Latch in synchronization with the rising edge of the LK signal. Selector 5c
Selects the read data D (# 1) or D (# 2) according to the control signal c3 from the control circuit 9 and outputs it to DFF4a.

The DFF 4a latches the read data D (# 1) or D (# 2) in synchronization with the rising edge of the CLK signal, and outputs it as read output data dout.

The clock generation circuit 8 supplies a CLK signal to each DFF 1a, 1b, 2a to 2c, 4a and a counter 1c, and also supplies write enable signals (hereinafter referred to as write signals) W1 and W2 to the RAMs 6a and 6b, respectively.

The control circuit 9 sends control signals c1 to c3 to the selectors 3a, 3b, 5a to 5c.
Is output and double buffer processing is performed. The double buffer process is to alternately supply the write commands W1 and W2 and the addresses SA and RA to the two RAMs 6a and 6b to alternately execute the sequential read and the random write, specifically, the control circuit 9 Is a sequential address for each frame that defines the data write or read period.
SA is selected by one selector 5a, and this address
The SA is supplied to one RAM 6a to execute the sequential read of the read data D (# 1), the random address DA is selected by the other selector 5b, and the address RA and the write command W2 are supplied to the other RAM 6 And data D
Random write of IN is executed.

In the next frame, on the contrary, the control circuit 9 causes the selector 5a to select the random address RA and
The RA and the write command W1 are supplied to the RAM 6a to execute the random write of the data DIN, and the sequential address SA is selected by the selector 5b.
The data is supplied to the RAM 6b to execute the sequential read of the read data D (# 1).

That is, according to the semiconductor memory device of the related art of the present invention, the address selectors 5a and 5b for switching the random write and the sequential read for each frame, the write command W1 for each frame, the RAM 6a, or the write command W2 for each frame.
The clock generation circuit 8 supplied to 6b is provided inside the same chip.

Therefore, while RAM6a is performing sequential read, RAM6b is read according to write command WE2 and random address.
On the contrary, the RAM 6a can be randomly written according to the write command W1 and the random address while the RAM 6b is sequentially reading.

However, when a random write command is inserted from outside the chip into the RAM6a during sequential read due to a call request from a new subscriber, etc., and there is a request to rewrite data at a certain read address, the data during sequential read is In addition, there is a risk that unintended data will be mixed.

In response to such a data rewrite request, when inserting random write into RAM6a during sequential read,
Write command W1 supplied from the clock generation circuit 8 to the RAM 6a
Is forcibly activated based on the write command we of the CPU, etc., and the address selector 5a is switched to RAM6a.
It is possible to supply a random address to the.

Next, a specific example will be described. FIG. 3B is a time chart explaining the operation of the time switch memory. For example, for random address = a, b, c, d, e ..., at the time of reading, the sequentially generated sequential address = 0,1,2,3,4 ... causes the storage address 0 = a, 1. = B,
2 = c, 3 = d, 4 = e ... Read data D (# 1) or D (#
In the semiconductor memory device outputting 2), FIG.
As shown in, if the write request from the CPU is to the address “d” of the RAM 6a and the write command we of the CPU is generated at the rising edge of the clock signal (hereinafter simply referred to as CLK signal), the next CLK At the rising edge of the signal, the write command WE1 is input to the RAM 6a and the sequential address SA from the address selector 5a to the RAM 6a.
Random address = “d” is supplied instead of “= 3”.

Thereby, the writing to the address "d" is achieved. After that, the read data D (#
1) is latched, and the read data D (# 1) becomes output data dout at the next rising edge of the CLK signal. This CLK
The data output at the rising edge of the signal is the data for the address "d".

However, depending on the switching timing of the address selector 5a, the sequential address SA changes to "3" from the selector 5a to the RAM 6a, and the random address = "d".
May not be available.

For this reason, since the RAM 6a executes random write with an address other than the random address = “d”,
Wrong data DIN is written. Therefore, when d ≠ 3, the target data by random writing cannot be inserted into the output data dout with good reproducibility.

As a result, there is a problem that untargeted data is erroneously inserted into the data during the sequential read (a data discontinuity occurs).

In order to avoid such discontinuity of read data, the fifth
A control memory having a two-bank configuration as shown in the figure can be considered. This control memory, as shown in FIG.
One bank I, II is composed of RAM etc., and one bank I
The random write is executed to the other bank II during the sequential read.
When the reading of the data from the 0th address to the last address of the bank I is completed, the banks are switched as shown in FIG. 5 (b), and the bank II performs the sequential read,
Bank I performs a random write. By repeating such operations, the continuity of read data required for the control memory is ensured.

However, since the memory is divided into two banks, the number of control circuits around the memory is increased. In addition, when a write request is issued to a bank during sequential reading, the continuity of read data is broken as in the case where the bank configuration is not adopted.

The present invention was created in view of the problems of the conventional example, and by devising a method of supplying a write command, a simple configuration can be applied to a memory during sequential read without supplying a random address. An object of the present invention is to provide a semiconductor memory device capable of inserting random write and preventing untargeted data from being inserted into data during sequential read (securing read data continuity).

[Means for solving problems]

As shown in the principle diagram of FIG. 1, the semiconductor memory device of the present invention includes first memory means for sequentially reading data randomly written based on a write command and a random address based on a sequential address,
Data is randomly written based on a write command and a random address during a period when the first storage unit is sequentially reading, and the random write is performed during a period when the first storage unit is randomly writing. Second storage means for sequentially reading data based on a sequential address, address comparison means for generating an address match signal when both addresses are compared by comparing the random address and the sequential address, and the address comparison Write command control means for outputting a write command for inserting a random write into either the first or second storage means during sequential read in response to an address match signal from the means. To achieve.

[Work]

The operation of the semiconductor memory device of the present invention will be described. For example, when address information (hereinafter simply referred to as data) is supplied to the time switch memory or the like, one frame of data is randomly written by the first storage means based on the write command and the random address, and this first storage means is used. During the period in which random writing is performed, data of one frame is sequentially read in the second storage means based on the sequential address.

Thereafter, in the first storage means, one frame of data is sequentially read based on the sequential idle, and during the period in which the first storage means is sequentially read, one frame of data is read based on the write command and the random address. The data is randomly written by the second storage means.

Further, when the first and second storage means repeat the sequential read and random write, the random address and the sequential address are compared by the address comparison means, and the comparison result is written as an address match signal or an address mismatch signal. It is output to the command control means.

Furthermore, when a write command for forcibly inserting a random write is supplied to the write command control device during the sequential read period of either the first or second storage device, the random command is input by the random write insertion. Since the address is also compared with the sequential address by the address comparison means, when the addresses match, the address comparison signal is output from the comparison means to the write command control means, and the first or second sequential read from the control means. A write command for forcibly inserting a random write is supplied to any one of the storage means.

Therefore, unlike the related art of the present invention, the sequential address matching the random address is supplied to the storage means during the sequential read without forcibly switching the sequential address to the random address via the address selector. , Random write can be inserted in the storage means during sequential read.

As a result, in the first or second storage means during the sequential read based on the sequential address,
Data can be rewritten and data that is not the data target during sequential read is not inserted. That is, the continuity of read data is ensured.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a principle diagram of a semiconductor memory device according to an embodiment of the present invention. For example, a control memory, which is an example of a semiconductor memory device, has data input means 11a,
Counter 11b, address selector 12, first and second RAM (writable / readable memory at any time) 13, 14, data selector 1
5, data output circuit 16, clock generation circuit 17, control circuit 18,
An address comparison unit 19, a write command processing unit 20, a write command output unit 21, and a selection unit 22 are provided. The control memory supplies the input random address to the time switch memory shown in FIG.

The data input means 11a inputs the input data DIN and the random address ra and supplies the data DIN to the first and second RAMs 13 and 14. The data input means 11a is provided with a D-type flip-flop circuit (DFF) not shown, and supplies the data DIN to the first and second RAMs 13 and 14 in synchronization with the clock signal CLK.

The data DIN is, for example, A / D converted from an analog voice signal with a multiplicity of n = 1024 lines and is pulse code modulated (PCM).
It was done.

The data input means 11a also outputs the address ra to the address selector 12. The counter 11b inputs the clear signal fc and supplies the sequential address SA to the address selector 12.

The address selector 12 selects either the random address RA or the sequential address SA to select the address RA or
One of the SAs is output to RAM13 or RAM14. For example, the selector 12 outputs the address RA to the RAM 13 based on the control signal from the control circuit 18, and the address S to the RAM 14 at this time.
Output A. Conversely, the selector 12 addresses the RAM 13
When SA is output, the address RA is output to RAM14.

The RAM 13 is an example of the first storage means, and the write command WE
Data DIN based on (# 1) and random address RA
Is randomly written and the data D (# 1) is sequentially read based on the sequential address SA.

The RAM 14 is an example of the second storage means, and the write command WE
Data DIN based on (# 2) and random address RA
Is randomly written, and the read data D (# 2) is sequentially read from this data DIN based on the sequential address SA. For example, RAM14 is RAM13
Write command WE during the sequential read
Data DIN based on (# 2) and random address RA
Is randomly written, and the read data D (# 2) is sequentially read based on the sequential address SA while the RAM 13 is randomly writing. The RAMs 13 and 14 may have a two-bank configuration by dividing the same RAM.

The data selector 15 is the data D (# 1) or R from the RAM 13
One of the data D (# 2) from the AM 14 is selected based on the control signal from the control circuit 18, and either the data D (# 1) or D (# 2) is output to the data output circuit 16.

The data output circuit 16 synchronizes with the clock signal CLK from the clock generation circuit and outputs the data D (#
1) or D (# 2) is output to a communication line or the like. The clock generation circuit 17 generates a clock signal CLK based on the control signal from the control circuit 18, and uses this signal CLK for the data input means 11
a and the data output circuit 16.

The control circuit 18 controls input / output of the address selector 12, the data selector 15, and the clock generation circuit 18. For example, the control circuit 18 outputs a control signal for selecting an address to the selector 12, outputs a control signal for selecting data to the data selector 15, and controls the timing of the clock signal CLK to the clock generation circuit 17. The control signals for performing are output.

Note that the above is the same as the control memory for supplying a random address to the time switch memory (semiconductor memory device of the same application) of the related art of the present invention. In the embodiment of the present invention, the following additional means is provided.

That is, as shown in FIG. 1, an address comparison unit 19, a write command processing unit 20, a write command output unit 21, and a selection unit 22 are newly provided in the control memory.

The address comparison means 19 compares the random address RA with the sequential address SA and outputs an address match signal COMP to the write command processing means 20 when both addresses match. For example, random address RA (10
bit) and sequential address (10bit) SA are compared, and when both addresses match, the address match signal C
The OMP is output to the write command processing means 20.

The write command processing means 20, the write command output means 21, and the selection means 22 constitute write command control means,
In response to the address match signal COMP from the address comparison means 19, a write command we for inserting random write is output to either the RAM 13 or 14 during the sequential read.

For example, the write command processing means 20 latches the write command we for inserting the random write in response to the address match signal COMP from the address comparison means 19 and writes the write processing signal WE2.
Is output to the write command output means 21. The write command we is supplied from the CPU or the like of the TSW device in which the control memory is built. Specifically, when the telephone subscriber issues a call request to the TSW device, the write command we asserts.

The write command output means 21 inputs the write processing signal WE2 and the write pulse φWE from the clock generation circuit and outputs the write command WE3 to the selection means 22. Selection means 22
Selects the RAM 13 or RAM 14 and outputs the write command WE3.

FIG. 2A is a logic circuit diagram of the write command control means of the control memory according to the embodiment of the present invention. In FIG. 2 (a), the address comparison means 19 comprises, for example, 10-bit E-OR logic circuits 90 to 99 and a comparison operation circuit 901.
The E-OR logic circuit 90 compares the sequential address SA ₀ from the data input means 11a with the random address RA ₀ and outputs the comparison signal to the comparison operation circuit 901. Similarly, each of the E-OR logic circuits 91 to 99 has a sequential address SA _{1 to} SA ₉ and a random address from the data input means 11a.
RA _{1 to} RA ₉ are compared, and the comparison signal is output to the comparison operation circuit 901.

The comparison operation circuit 901 outputs an address coincidence signal COMP to the write instruction processing means 20 when there is a coincident address among the comparison signals of the E-OR logic circuits 90 to 99.

The write command processing means 20 includes a DFF 201, 203 and a NAND circuit 202.
Consists of. The DFF 201 latches a write command we for inserting a random write from the CPU or the like according to the address match signal COMP from the comparison operation circuit 901, and outputs the output signal NAND.
Output to the circuit 202. The NAND circuit 202 receives the address match signal C
The logical signal of the OMP and the output signal from DFF201 is output to DFF203. The DFF 203 outputs the write processing signal WE2 to the write command output means 21 according to the logic signal from the circuit 202.

The write command output means 21 includes an inverter circuit 211 and a NAND.
The circuit 222. Inverter circuit 211 is a write processing signal
WE2 is logically inverted and the inverted signal is output to the NAND circuit 222. The NAND circuit 222 inputs the write pulse φWE from the clock generation circuit 17 and the inverted signal from the inverter circuit 211 and outputs the write command WE3 to the selection means 22.

Next, the operation of the control memory according to the embodiment of the present invention will be described. FIG. 2B is an operation waveform diagram of the control memory according to the embodiment of the present invention, and is an operation time chart when a random write is inserted into the address d (= 3) of the RAM 13 in the control memory during the sequential read. Is shown.

In FIG. 2 (b), CLK is a clock signal, SA is a sequential address, RA is a random address, we is a write command, COMP is an address match signal, WE2 is a latched write processing signal, φWE is a write pulse, and WE3 is Write commands are shown respectively. The write command WE3 is, for example,
It is supplied to the RAM 13 during sequential reading. Also,
A (# 1) is a sequential address input to the RAM 13 during sequential read. D (# 1) indicates each signal of read data, dout ... Read output data.

For example, the control memory during sequential read is RAM13
If there is a request to insert a random write at address d (= 3), the write request will not be executed immediately. The actual write operation is performed when the read address indicates the address d = 3, and in the embodiment of the present invention, when the read address matches the write address. By doing so, the read data other than the address 3 where the writing is executed is not disturbed by the writing,
It can be read continuously.

That is, in FIG. 2B, for example, the sequential address SA is cleared (SA = 0) in synchronization with the rising of the clock signal CLK, and the random address RA
(D = 3) is latched by the data input circuit 11a, and the write command we is input by the write command processing means 20.

In synchronization with the rising edge of the next clock signal CLK, the content "0" of the sequential address SA of the previous cycle is RA.
The content "0" of the read data D (# 1) from address 0 is input to M13 and synchronized with the rising edge of the clock signal CLK with a delay of one clock, and the data output circuit 15 latches the content "0". After a delay, the read output data dout = “0” is output to the output terminal in synchronization with the rising edge of the clock signal CLK.

Also, in synchronization with the rising edge of the clock signal CLK,
The content of the sequential address SA becomes "3", but since this matches the address d = 3 specified by the random address RA, the address match signal COMP becomes "H" (high) level and the next clock signal CLK. The write processing signal WE2 is output from the write command processing means 20 to the write command output means 21 in synchronization with the rising edge of.

Upon receiving the write processing means WE2, write command output means 21
The write command WE3 from is output to the selection means 22, and the selection means 22 outputs the write command WE3 to the RAM 13.

As a result, the writing to the address 3 is achieved in the RAM 13. After that, the content “3” of the read data D (# 1) is latched in the data output circuit 15 in synchronization with the rising edge of the clock signal CLK, and further, one clock later, in synchronization with the rising edge of the clock signal CLK. The read output data dout = “3” is output to the output terminal.

Thus, according to the control memory of the embodiment of the present invention, as shown in FIG. 1, the address comparing means 19, the write command processing means 20, the write command outputting means 21, and the selecting means 22 are provided. Prepare

Therefore, when the random address RA and the sequential address SA are constantly compared by the address comparing means, the designated addresses of both the addresses RA and SA match, and the write command we is obtained, the RAM 13 or the RAM 13 during the sequential read or R
Can be output to the write command WE3 in AM14.

That is, when the write command we forcibly inserting the random write from the outside is supplied to the write command processing means 20 while the RAM 13 or 14 is sequentially read, the write command we is input by the random write insertion. Random address RA and sequential address SA are compared by the address comparison means 19, and if they match,
The address coincidence signal COMP is output from the comparison means 19 to the write command processing means 20, and is written from the processing means 20 to the RAM 13 or 14 which is sequentially read through the write command output means 21 and the selection means 22. The instruction WE3 can be supplied.

Therefore, unlike the related art of the present invention, it is possible to insert a random write into the RAM 13 or the RAM 14 during the sequential read without forcibly switching the sequential address SA to the random address RA via the address selector 12. Become.

As a result, it is not necessary to supply the random address RA to the RAM 13 or RAM 14 in random write and during sequential read. Further, the data can be rewritten in the RAM 13 or 14 during the sequential read based on the sequential address SA, and the untargeted data is not inserted in the data during the sequential read, and the continuity of the read output data dout is ensured. Can be kept.

Note that new data [read data D (# 1)] newly written at the address 3 is output to the line, but the old data at the same address has become unnecessary due to the start of a new call. Therefore, there is no problem in transmitting new data instead of old data. Further, the write command we does not need to be held until the write operation is executed, and it is sufficient to latch it by the DFF circuit 201 as in the embodiment of the present invention.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, the random address and the sequential address are compared, and when the two addresses match, the write command for inserting the random write is stored in the storage means during the sequential read. A write command control means is provided.

Therefore, a random write can be inserted in the storage means during sequential read without intentionally switching the sequential address supplied to the storage means during sequential read to a random address, and data can be rewritten based on the sequential address. Therefore, untargeted data is not inserted into the data during the sequential read (the continuity with the read data can be secured).

As a result, it is possible to easily configure a control memory having a two-bank configuration in which the same RAM is divided, which contributes to the provision of a time switch memory with a double buffer function in which sequential read or random write can be freely selected from the outside. large.

[Brief description of drawings]

FIG. 1 is a principle diagram according to an embodiment of the present invention, FIG. 2 is a diagram for explaining an operation according to the embodiment of the present invention, and FIG. 3 (a) is a semiconductor memory device to which the present invention is applied. FIG. 3 (b) is a diagram for explaining the circuit operation of FIG. 3 (a), FIG. 4 is a schematic diagram of time division exchange of a TSW device according to a conventional example, and FIG. 5 is a conventional diagram. It is the figure which made the control memory which relates to the example the 2 banks constitution. (Description of symbols) 11a ... data input circuit, 11b ... counter, 12 ... address selector, 6a, 6b, 13,14 ... first and second RAM (random access memory), 15 ... data selector , 16 ... data output circuit, 8, 17 ... clock generation circuit, 9, 18 ... control circuit, 19 ... address comparison means, 20 ... write command processing means, 21 ... write command output means, 22 ... ... Selection means, 1a to 1c, 2a to 2c, 3a to 3c, 4a to 4c, 201,203 ... DFF (D type flip-flop circuit), 5a, 5b ... selector, 7a, 7b ... predecoder, 10a ... ... parity check circuit, 90 to 99 ... E-OR logic circuit, 901 ... comparison operation circuit, 202,222 ... NAND circuit, DIN ... input data, ra ... input random address, RA ... random address, SA ... … Sequential address, fc …… Clear signal, CLK …… Clock signal, we …… Write command, W1, W2 (The upper line is omitted.) Write enable signal, WE0 ... Latched write command, WE1 ... Write processing signal, WE2 ... Latched write processing signal, WE3 ... Write command, φWE ... Write pulse signal , C1 to C4 ... Control signal, COMP ... Address match signal, A (# 1), A (# 2) ... Random / sequential address, D (# 1), D (# 2) ... Read data, dout ... Readout output data, dout '... Auxiliary readout output data.

Claims (1)

[Claims] 1. A first storage unit for sequentially reading data randomly written based on a write command and a random address based on a sequential address; and a period during which the first storage unit is sequentially read. Second storage means for randomly writing data based on a write command and a random address, and for sequentially reading the randomly written data based on a sequential address while the first storage means is performing random writing. And the random address and the sequential address are compared with each other, and when the two addresses match, an address comparing means for generating an address matching signal and a first during the sequential reading in response to the address matching signal from the address comparing means Or any of the second storage means The semiconductor memory device characterized by comprising a write instruction control means for outputting a write command to insert a random write to.