JPH0785234B2 - Data transfer method between processors - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data frame transfer method performed between a plurality of processors, and more particularly to an inter-processor data transfer method suitable for a system that asynchronously transfers data frames.

[Background of the Invention]

Conventionally, as a data transfer method performed between multiple processors,
For example, Intel MIP method is known. This system is a system in which two processors transfer data via a shared memory, and a plurality of data transfer areas, and a registration pointer and a fetch pointer for these data transfer areas are provided in the shared memory. The processor on the data transfer side obtains the address of the data transfer area where the data should be written next from the contents of the registration pointer, writes the transfer data in the data transfer area corresponding to this address, and then sets the registration pointer. Update. On the other hand, the processor on the data receiving side obtains the address of the data transfer area from which the data should be fetched next from the contents of the fetch pointer, fetches the transfer data from the data transfer area corresponding to this address, and then updates the fetch pointer. To do. Both processors can know whether the data transfer area is full or empty by comparing the registration pointer and the fetch pointer. Therefore, this MI of Intel
The P method has the advantage that the next data can be transferred without waiting for the processing of the receiving side processor for the transfer data to be completed, but on the other hand, registration / extraction pointer comparison, calculation of the data transfer area address from the pointer, registration / registration / Since the process of updating the fetch pointer is required, there is a disadvantage that the processing time becomes long.

On the other hand, as another method capable of reducing the processing time, there is a method described in JP-A-58-97944. In this system, a FIFO queue is prepared by hardware separately from the shared memory, and only the address of the data transfer area in the shared memory is transmitted via the FIFO queue. However, even in this method, there is a drawback that an overhead occurs in the processing for extracting the data transfer area from the empty data transfer area / queue in the shared memory.

[Object of the Invention]

An object of the present invention is to enable the processing of data transfer between processors so that the next data can be transferred without waiting for the end of the processing of the transfer data of the receiving side processor, and the processing time for data transfer can be shortened. It is to provide an inter-data transfer method.

[Outline of Invention]

According to the present invention, a plurality of processors connected to a common bus are
A buffer device is provided between each internal bus and the common bus, and each of the plurality of processors transfers data in units of transfer data frames each including a maximum of n bytes (n is a plurality) via the common bus. In the data transfer method between the processors, the data of each byte in the transfer data frame transferred from the other processor via the common bus is written in each buffer device, and the transfer data frame is individually transferred. The n number of first register groups, which are fixedly assigned to which first byte of the data to be written, and the first register group are provided in association with each other, and the processor itself is provided via the internal bus. Are provided in association with each of the n second register groups capable of reading data in byte units and the first register group, respectively. First-in first-out buffer memory groups for fetching the respective data in the first register group in parallel and outputting the data in parallel to the second register group, status information of the buffer memory group, and First command / status register means for storing data transfer control information from the first register group to the buffer memory group, status information of the buffer memory group and the buffer memory group to the second register group Second command / status register means for storing the data transfer control information of the other, and the processor as the source of the data is the first command of the partner buffer device connected to the processor as the partner of the data transmission. / Refer to the status register means and state that there is an empty area in the buffer memory group in the partner buffer device , The transfer data is written to the first register group of the partner buffer device via the common bus, and the data transfer command information is given to the first command / status register means, so that the processor to be the data transfer partner Referring to the second command / status register means of the buffer device connected to the own processor, when the buffer memory group of the own buffer device is in the state of having data, the second command / status register via the internal bus Means for providing data transfer command information, the buffer memory group in response to the data transfer command output from the first command / status register means, fetches data in the first register group in parallel,
It is characterized in that data is output in parallel to the second register group in response to the data transfer command output from the second command / status register means.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a multiprocessor system to which the present invention is applied. A plurality of processor modules PM-1 to PM-m are connected to each other by a common bus 1.

Each processor module is a processor (CPU) 3, a program that regulates processor operation, and a local memory (LM) 4 for storing work data during processor operation, for data transfer with other processor modules. Used for the burst-in-farst-out (FI
FO) buffer device (BF) 5 and a local bus (LB) 13 connecting them.

FIG. 2 shows an example of the structure of the FIFO buffer device. The buffer device 5 includes address decoders 6 and 12, command / status registers 7 and 11, and data registers 8-1 to 8-.
n and 10-1 to 10-n, FIFO memories 9-1 to 9-n,
Data input signal line 100 and data output signal line 107 from address decoder 6 to register 7, data output signal line 101 and data input signal line 108 from address decoder 12 to register 11, and address decoder 6 to data register 8
-1, ..., 8-n data input signal lines 103-1 to 103-n,
Data input signal lines 104-1 to 104-n from the register 7 to the FIFO 9-1, ..., 9-n, FIF from the FIFO 9-1 to the register 7
O full signal line 105, FIFO e from FIFO 9-1 to register 11
mpty signal line 106, register 11 to data register 10-1,
,, 10-n data input signal lines 109-1 to 109-n, data output signal line 1 from register 11 to FIFO 9-1, ..., 9-n
11-1 to 111-n, register 7 to data register 8-
Data output signal lines 102-1 to 102-n to 1, ..., 8-n, data output signal lines 110-1 to 110-n from the address decoder 11 to the data register 10-1 ,. Composed.

FIG. 3 shows a memory map in the above system. Ten
Address 0H to 100H + n (n is the maximum value of the transfer data frame)
Is a transmission area addressed to Processor Module PM-1, 200H
~ 200H + n address is the transmission area for PM-2,
These areas are accessed via the common bus 1.
Addresses 1000H to 1000H + n are the receiving area of the processor module and are accessed via the local bus 13.
The command / status register 7 is assigned to the first byte of the transmission area addressed to the processor module.
Data registers 8-1, 8-2, ..., 8-
n are sequentially assigned. On the other hand, the first byte of the reception area of each processor module has a command /
The status register 11 is assigned, and the data registers 10-1, 10-2, ..., 10-n are sequentially assigned to the second byte and thereafter.

FIG. 4 shows the bit allocation of the command / status register 7. 2 ⁰ is the data input bit, when written CPU Ga該bit "1", the signal lines 102-1 to 102-n and 10
A signal flows to 4-1 to 104-n, and the data register 8-1,
The content of 8-n enters the FIFO memory 9-1, ..., 9-n. 2 ¹
Is a full bit, and when there is no empty area in the FIFO memory 9-1, a signal flows through the signal line 105 and the bit becomes "1". 2 ² is a bit indicating that it is in use, and the data register 8
Used for exclusive write control to -1, ..., 8-n.

FIG. 5 shows the bit allocation of the command / status register 11.

2 ⁰ is a data output bit, CPU Ga該writes the signal lines 109-1 to 109-n and a 1 to bit 111-1 to 111-n
, 9-n, and data is sent from the FIFO memories 9-1, ..., 9-n to the data registers 10-1 ,. 2 ¹ bit is a Enputeibitsuto, when there is no data in the FIFO memory 9-1 is "1".

Next, the operation of the above-mentioned device will be described by taking as an example the case where data is transferred from the processor module PM-1 to PM-2. FIG. 6 shows an operation flow chart of the processor CPU 3-1 included in PM-1 during transmission processing. CPU3-1 is
First, make sure that the data register of the partner processor module PM-2 is not in use. Specifically, 20
Judges 2 ² bits of the command / status register of the address 0H (used in bits) is whether or not the "0". If the result of this judgment is "1", wait until it becomes "0",
If it is "0", it is set to "1" and the next operation is performed. The "0" check operation and the "1" set operation must be performed exclusively, and are performed in the test and set. Next examine the 2 ¹ bit (Furubitsuto) of 200H address, checks whether the FIFO memory is empty areas. If it is "1", it waits until it becomes "0". If it is "0," 201H to 20
0H + n writes the transfer data to the address, then 2 of 200H numbered ⁰
Data is sent to the FIFO memory by writing "1" to the bit (data input bit).

FIG. 7 shows a reception processing flow of the CPU 3-2 included in the receiver-side processor module PM-2. Receiving CPU
First, 2 of the command / status register at address 1000H
Check ^one bit to determine whether there is data in the FIFO memory. If it is "1", wait until it becomes "0". Writing a 1 to 2 ⁰ bit data output bits of address 1000H if it is "0", data register 10-1 from the FIFO memory, ..., after capturing the data to 10-n, 1001H~10
Receive the data in the data register at address 00H + n.

According to this embodiment, the next data can be transferred from the transfer side processor without waiting for the end of the processing of the transfer data of the reception side processor, and the data transfer processing time can be shortened, so that the throughput of inter-processor communication can be improved. You can

〔The invention's effect〕

As described below, according to the present invention, the next data can be transferred from the transfer side processor without waiting for the processing of the transfer data of the reception side processor to be completed, and the data transfer between the processors can be performed in a short processing time. It is possible to build a multi-processor system with high throughput of data transfer.

[Brief description of drawings]

Fig. 1 is a block diagram of the multiprocessor system, and Fig. 2 is
FIG. 3 is a block diagram of a FIFO buffer device, FIG. 3 is a memory map of a multiprocessor system, FIG. 4 is a bit allocation diagram of command / status 7, FIG. 5 is a bit allocation diagram of command / status register 11, and FIG. 6 is transmission. FIG. 7 shows a processing flow chart of the receiving side CPU, and FIG. 7 shows a processing flow chart of the receiving side CPU. 1 ... Common Bus, 2 ... Processor Module, 3 ... CP
U, 4 ... Local memory, 5 ... Buffer FIFO device, 6 ...
Address decoder, 7 ... Command / status register, 8 ... Data register, 9 ... FIFO, 10 ... Data register, 11 ... Command / status register, 12 ... Address decoder, 13 ... Local bus.

Claims (1)

[Claims] 1. A plurality of processors connected to a common bus have a buffer device between each internal bus and the common bus, and each of the plurality of processors mutually has a maximum of n via the common bus. In a data transfer method between processors, which transfers data in units of transfer data frames composed of bytes (n is a plurality), each buffer device transfers data from the other processor via the common bus. Of each of the first register group and the first register group of n pieces, each of which is fixedly assigned to which byte of the data in the transfer data frame is to be written. N second registers provided in association with each other and capable of reading data in byte units to the own processor via the internal bus Group and each of the first register groups, which are provided in association with each other, take in the respective data of the first register group in parallel, and output the data to the second register group in parallel. n buffer memory groups, first command / status register means for storing status information of the buffer memory groups and data transfer control information from the first register group to the buffer memory group, and the buffer memory Group status information and second command / status register means for storing data transfer control information from the buffer memory group to the second register group. Referring to the first command / status register means of the partner buffer device connected to the processor as the sender, When there is an empty area in the buffer memory group of the buffer device, the transfer data is written to the first register group of the partner buffer device via the common bus and the data transfer command is issued to the first command / status register means. When the processor to which information is given and which is a data transfer partner refers to the second command / status register means of the buffer device connected to the own processor and the buffer memory group of the own buffer device is in a state with data, internal Data transfer command information is given to the second command / status register means via a bus, and the buffer memory group responds to the data transfer command output from the first command / status register means in response to the first command. Data of registers are taken in parallel,
A data transfer method between processors, wherein data is output in parallel to the second register group in response to a data transfer command output from the second command / status register means.