JPH0785974B2 - DC feeding circuit failure selection device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a DC feeding circuit failure selection device used for DC feeding protection in a railway substation or the like.

2. Description of the Related Art Conventional technology and its problems The feeder circuit failure selection device has a notch-up method to distinguish whether the increase in the current of the feeder circuit is due to the fault current or the current at the time of notch-up of a power train. It detects current changes in stages and compares the detected value with a set value to shut off the power supply to the feeder circuit only when there is a fault current.
It is known from Japanese Patent Publication No. 52-37581.

By the way, when such a feeder circuit failure selection device is actually used in a feeder circuit, when a train running in one train section (hereinafter referred to as a regenerative car) is under regenerative braking, another train is running. There is a problem that unnecessary operation of the high-speed circuit breaker occurs when a train running on the section (hereinafter referred to as a load car) is notched off.

For example, in the feeder circuit shown in FIG. 4, when there is a regenerative vehicle in the upstream section B and a load vehicle in the downstream section D and the load vehicle consumes the electric power generated by the regenerative vehicle, If notch-off is performed, the current flowing through 50 Fb is initially in the direction indicated by the chain line (this direction is the negative direction), but becomes zero due to notch-off of the loaded vehicle. When the current becomes zero, the regenerative voltage of the regenerative vehicle rises abnormally.Therefore, the overvoltage detection in the regenerative vehicle operates and short-circuits the main circuit through the overvoltage suppressing resistor. The indicated positive current flows. When the sum (ΔI) of the change from the negative direction current to the positive direction current exceeds the set value, 50Fb is activated although the failure does not occur, and the high speed circuit breaker is cut off to supply power to the feeder circuit. Will stop the supply. Fig. 5 shows changes in the current flowing through the regenerative vehicle and the load vehicle.

In view of the above problems, the present invention provides a useful fault selection device that selectively operates only a fault current without performing unnecessary operation even when the load vehicle is notched off while consuming the regenerative current of the regenerative vehicle. It is intended to be provided.

Means for Solving the Problems In order to achieve the above object, the present invention is an integrating means for integrating a differential detection value of a feeder current, and a feeder current is a signal on a step where a plurality of signal components are superposed. In this case, the subtraction circuit that subtracts the previous integrated value from the current integrated value by the time required to separate each signal component, and the subtraction result is compared with the set value.If the set value is exceeded, the fault current is exceeded. In the DC feeder circuit failure selecting device having a judging means for judging, the judging means for judging the flowing direction of the feeder and the integrated value of the memory integrating means after the feeder current has changed from the negative direction to the positive direction. And a subtraction means for subtracting the integrated value at the time when the feeder current changes from the negative direction to the positive direction and operating only for a predetermined compensation period from the time when the direction of the feeder current reverses from the negative direction to the positive direction. It is characterized by .

Embodiment FIG. 1 shows a feeder circuit failure selection device as an embodiment of the present invention. This device is provided in the electric wire 2 branched from the bus bar 1, and is an unsaturated transformer FD for detecting a change in the feeder current, and is also provided in the feeder 2, and a hall for obtaining a detection signal proportional to the feeder current. CT (HCT), an integrating circuit IC that integrates the detection signal of FD, a multiplexer MPX that switches ICs provided for multiple feeders at appropriate timing, an A / D converter A / D, and A current direction discriminator PS that discriminates whether the feeder current detected by the HCT is positive or negative, and a microprocessor MPU that discriminates whether a fault current flows in the feeder from the discrimination result and the signal detected by FD.
, An interface IF, and a relay Ry that issues a cutoff signal when it is determined that a fault current is flowing.

Now, when the regenerative vehicle and the load vehicle are traveling at the same time as shown in Fig. 4 and the load vehicle is notched off, the electric wire connected to the train section of the regenerative vehicle is negative as shown in Fig. 2 (a). A positively changing current flows from. This current is detected by the HCT as it is and the current direction is determined by the PS, so the signal shown in FIG. 2B appears at the output of the PS.

On the other hand, the FD detects the change (differential value) of the feeder current and the IC integrates the detected value, so the output of the IC is shown in Fig. 2 (c).
The signal indicated by the solid line appears at. This signal is similar to the feeder current in FIG. 2 (a) only in the zero point, but the waveform shape is similar. The output signal of the IC and the output signal of the PS undergo predetermined processing by the MPU. This processing is performed according to the flowchart of FIG. That is, first, in # 1, the MPU reads the output signal of the IC (actually, the A / D converted digital signal) and stores it as [A] in a predetermined memory address. Then, in # 2, the difference between the previously stored [A] and the [A] read 300 ms before (this is referred to as [A ']) is taken, and this is designated as [B], and the predetermined memory address is obtained. To store. The process of # 2 discriminates the stepwise increase in current caused by the notch up of the train from the fault current, so that it is separated into the current change in each stage of notch up.

When the process of # 2 is completed, the program proceeds to # 3 to read the current direction detected by PS. When it is determined that the current direction remains negative in # 4, the process proceeds to # 5,
The MPU stores zero as a data [D ₁ ] at a predetermined memory address. Then, in # 66, [D ₁ ] is compared with a preset value of the apparatus. In this case, since [D ₁ ] is zero, the set value is larger, and therefore the process does not proceed to # 7 but returns to # 1.

The above operation is performed as long as it is determined that PS is negative,
Therefore, the process is repeated until time t ₁ in FIG.

Next, when time t ₁ is reached and the current direction reverses from negative to positive,
The program proceeds from # 8 to # 9, sets the first stage compensation calculation in progress, and then stores the [B] at that time as the first stage compensation value [C] in a predetermined memory address in # 10. Here, [C] is an average value of [B] at two points before and after the sampling time with the time when the current direction changes from negative to positive. The sampling time is the time between the previous reading and the current reading when the MPU reads the detected value of the same feeder current, and depends on the MPU clock pulse. In this embodiment, one sampling time is 2 ms.

When # finishing the process at 10, the process proceeds to # 11, to positively set the current of the current direction, followed by # 12 (B) - performs the calculation of the [C], [D ₃ the value determined by the calculation ] In a predetermined memory address. This [D ₃ ] is the current [B]
And the value of [B] when the current direction is reversed, and this value is not so large. Therefore, in # 6 [D ₃ ]
Is compared with the set value, but since [D ₃ ] does not exceed the set value, the program returns from # 6 to # 1. If two sampling times or more elapse after the current direction changes from negative to positive, the program will change from # 13 to # 14 to # 15.
→ Proceeds to # 12, and subtracts the data [C] stored at # 10 from the data [B] read at each sampling time. This subtraction process is repeated until [B] falls below the compensation value [C] of the first stage, that is, until [B] − [C] ≦ 0 holds. Until t ₁ ~t ₂ of FIG. 2 (d) corresponds to, this is a compensation calculation of the first stage.

Next, when the first-stage compensation calculation is canceled, the program
Proceeding from 16 to # 17, after setting the second stage compensation calculation in progress, the calculation of [C] × 0.67 is performed in # 18, and the value obtained by the calculation is used as the second stage compensation value [C ' ] In a predetermined memory address.

When the calculation process of # 18 is completed, the calculation of [B]-[C '] is performed in # 19, and the value obtained by the calculation is stored in a predetermined memory address as [D ₄ ]. This [D ₄ ] is the difference between the current value [B] of the output residual of the integrating circuit IC and the value at the time when the current direction is reversed, that is, the value obtained by multiplying the compensation value [C] of the first stage by 0.67. . Here, the constant 0.67 is the ratio to the point [C] at which the output residual amount of the integrating circuit IC is attenuated according to the discharge characteristic and intersects with the integrating circuit output value 300 ms before and is always constant.

Subsequently, although # 6 [D _4] is compared with a set value, [D _4]
Does not exceed the set value, so the program is # 6 →
Return to # 1. When two or more sampling times elapse after the compensation calculation in the first stage is canceled, the program proceeds from # 20 to # 21 to # 19 and the data [B] read at each sampling time is stored in # 18. The data [C '] that is present is subtracted. In this subtraction process, [C '] is 30
The process is repeated until the output value [A '] of the integrating circuit before 0 ms is reached, that is, [C'] <[A '] is satisfied. This corresponds to t ₂ to t _{3 in} FIG. 2D, which is the second-stage compensation calculation.

When the second-stage compensation calculation is canceled, the program will change to #
The sequence proceeds from 20 to # 23, and [B] of each sampling time is stored as [D ₂ ] in a predetermined memory address without subtracting the compensation values [C] and [C ′].

When the first-stage and second-stage compensation operations are performed in this manner, the data [D ₃ ] and [D ₄ ] obtained as a result have the waveforms shown in FIG. That is, this data is data [B] that protrudes above the compensation values [C] and [C '] in FIG.
And approximates to the current waveform in the positive region of the feeder current in FIG. That is, the change value of the feeder current in the positive region can be obtained by the subtraction process. Then, the data [D ₃ ] and [D ₄ ] are compared with the set value in # 6. In the case of the current flowing through the feeder as a result of notch-off of the load vehicle while consuming the regenerative current, not the fault current, the current change value in the positive region is not large as shown in Fig. 2 (a), so the set value is It cannot be exceeded. Therefore, the program does not proceed to # 7, and the disconnection signal is issued unnecessarily and the high speed circuit breaker
54F never works.

On the other hand, in the case of a fault current, the current waveform is not shown,
Since it is the current change in the positive region, the program is # 1 →
The sequence proceeds from # 2 → # 3 → # 4 → # 8 → # 13 → # 14 → # 20 → # 23, and [B] is stored as it is as [D ₂ ]. That is,
Since the compensation values [C] and [C '] are not subtracted, the value of the data [D ₂ ] greatly exceeds the set value. Therefore, the 54F of the high speed circuit breaker is selectively operated only when a failure occurs.

EFFECTS OF THE INVENTION Since the DC feeding circuit failure selecting device according to the present invention is configured as described above, it is possible to avoid unnecessary operation of the high speed circuit breaker when the load vehicle consuming the regenerative current is notched off. However, there is an effect that it can be operated accurately only when a failure occurs.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the device of the present invention, FIG. 2 is a diagram showing signal waveforms of respective parts in FIG. 1, and FIG.
FIG. 4 is a flow chart for explaining the operation of the MPU, FIG. 4 is a diagram showing a feeder circuit for explaining conventional problems, and FIG. 5 is a diagram showing currents flowing in a regenerative vehicle and a load vehicle. 1 …… Bus bar, 2 …… Supply wire, 54F …… High-speed circuit breaker, HCT
…… Hall CT, PS …… Current direction discriminator, FD …… Unsaturation transformer, MPU …… Microprocessor.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshiaki Hasegawa 4-4-10 Segawa, Minoh City, Osaka Prefecture, Tsuda Denki Keiki Co., Ltd. (56) References: 61-174836

Claims (1)

[Claims] 1. An integrating means for integrating a differential detected value of a feeder current, and, when the feeder current is a signal on a staircase in which a plurality of signal components are superposed, it is necessary to separate each signal component. A DC feeding circuit having a subtraction circuit for subtracting the integrated value before the current integrated value from the current integrated value, and a determination means for comparing the subtraction result with a set value and determining a fault current when the set value is exceeded. In the fault selection device, the feeder current changes from the negative direction to the positive direction from the determination means that determines the feeder current flow direction and the integrated value of the previous memory integration means after the feeder current changes from the negative direction to the positive direction. DC feeding circuit failure, comprising: subtraction means for subtracting the integrated value at the time point and operating only for a predetermined compensation period from the time when the direction of the feeder current is reversed from the negative direction to the positive direction. Selection device.