JPH0786750B2 - Effector - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention adds an effect to an acoustic signal.
Regarding effectors to do.

[0002]

2. Description of the Related Art Conventionally, acoustic pianos have been used.
There is an effector that adds a reverberation effect to the output acoustic signal in order to imitate the box noise and the resonance sound .

[0003]

However, simply adding the reverberation effect to the output sound signal is far from imitating the box noise or resonance sound of a natural musical instrument such as an acoustic piano, and sufficient effect addition is performed. I couldn't say that. This is because the conventional method
The reverberation sound is a high frequency signal generated in response to a keypress.
It is generated based on the issue.
A musical sound that is emitted, that is, a string that corresponds to a keystroke in a piano.
It is emitted only by the vibration of. However,
Actually, when you type a key, you will receive this key directly.
In addition to the more vibrating strings, there are strings that resonate with the vibration of this string.
Resonance sound and box noise are generated in all these vibrating strings.
It is generated based on. In other words, resonance and box noise
If you want to add a reverberation effect to mimic the sound,
It is necessary to consider all natural frequencies of the vibrating strings.
There is. Therefore, this reverberation has one frequency
Not only the delay component of the tone signal, but also the tone of multiple types of frequencies
Since the delay component of the signal is included, as a whole
The frequency will change in a complicated manner. By contrast,
Just like the conventional method, there is only one tone frequency left
By creating a sound, these complex frequency changes are expressed.
I can not do it, but it is far from the actual resonance sound and box noise
did not become.

An object of the present invention is to compare the output acoustic signal with an audio signal.
Box sounds of natural musical instruments such as caustic piano
Of adding enough reverberation to mimic the resonance
It is about realizing an effector that can.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a vibrato effect for an acoustic signal to which an effect is applied.
The point is that it is given and input to the wet line of the effector.

With such processing, the reverberation sound is vibrato.
Based on a tone signal whose frequency changes with
This is generated, and the frequency is changed in a complicated manner.
As a result, it mimics a boxing or resonance sound that is more like a natural musical instrument.
can do.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram according to an embodiment of the present invention.

The CPU 101 stores the program stored in the ROM 102 connected via the bus 114 in the RAM.
By executing 103 as a work memory, an interface circuit (I / F) 109 from the keyboard 108,
Sound source 10 based on performance information input via the bus 114
4 and control of a DSP (Digital Signal Processing Processor: Digital Singnal Processor) 105 based on operation information of the pedal 110 input through the A / D converter 111.

The tone signal generated by the sound source 104 is D
Input to SP105. The DSP 105 uses the connected delay memory (E) 106 and the like and executes a predetermined operation program to give a desired time change to the read address of the digital tone signal data input from the sound source 104. Performs processing to modulate or add reverberation effects. The digital tone signal that has been modulated and added with the reverberation effect is converted into an analog tone signal of left and right channels by the D / A converter 107 and output, and then amplified by the amplifiers 112L and 112R for the right and left channels, respectively. , Sounds are emitted from the speakers 113L and 113R.

Next, FIG. 2 is a diagram showing an internal configuration of the DSP 105 of FIG. In the figure, a program memory 201 is a memory for storing a predetermined microprogram, and supplies a predetermined operation program to the control circuit 202 in accordance with an instruction from the CPU 101 of FIG.

The control circuit 202 includes a program memory 20.
Based on the output content of 1, outputs each register to be described later, data transfer and calculation between memories, various control signals for controlling opening and closing of each gate and latch, and a counter value SC incremented at each sampling timing, Perform desired signal processing operations.

The coefficient memory (P) 203 is shown in FIG.
As shown in FIG. 7, it is a register for storing various parameters for adding the reverberation effect, and these coefficients are stored in the CPU 1
Under the control of 01, it is read from the RAM 103 of FIG. 1 and stored.

The work memory (W) 204 is a working memory for temporarily saving the waveform signal created in the DSP 105, as shown in FIG. Further, the address offset memory (T) 205 is provided with a delay memory (E) 10 which will be described later, as shown in FIG.
6 is a register for storing the offset value of the address 6, and the offset value is read from the RAM 103 of FIG. 1 and stored under the control of the CPU 101.

The delay memory (E) 106 has its output and input connected in a ring shape via registers (EI) 230 and (EO) 229, and has a counter value SC incremented at each sampling timing and a delay memory. The value obtained by adding the offset value from the address offset memory 205 by the adder 227 is used as the address. The delay time of data written with a certain offset value is expressed by the difference between the offset delay and the offset delay of the address to be read. Data is read from and written to the delay memory 106 in registers (EO) 229 and (E) described later.
I) 230.

An input register (PI) 206 stores the digital input musical tone signal from the sound source 104 of FIG. 1 and supplies it to each section via an internal bus 207. The outputs of the coefficient memory (P) 203, the work memory (W) 204, and the output of the input register (PI) 206 are input to the gate terminals of gates 208 to 211 together with the outputs from the registers described later, and the gates 208 to 208 The outputs from 211 are registers (M0) 212, (M1) 213, (A0) 21.
4 and (A1) 215.

Registers (M0) 212, (M1) 213
Stores the data in the middle of calculation supplied to the multiplier 216, and registers (A0) 214 and (A1) 215 store the data in the middle of calculation supplied to the adder / subtractor 217.

The output of the register (M1) 213 and the output of the register (SR) 224, which will be described later, are supplied to the gate 218.
Is input to the multiplier 216 via the output of the register (A0) 214 and the register (MR) 2 described later.
The output of 21 is input to the adder / subtractor 217 via the gate 219, and the output of the register (A1) 215 and the output of the register (AR) 222 described later are output to the adder / subtractor 217 via the gate 220.

The multiplication result of the multiplier 216 is stored in the register (M
R) 221 and the output of the register (MR) 221 is supplied to the gate 209 and the gate 219.
The calculation result of the adder / subtractor 217 is stored in the register (AR) 222, and the output of the register (AR) 222 is the gate 22.
In addition to being supplied to 0, it is supplied to the register (SR) 224 via the clipper circuit 223 for preventing overflow (digit overflow). Register (SR) 224
Is supplied to the gate 218, and is also stored in the work memory (W) 204 via the internal bus 207 as the calculation result of the process for one sound.

The above calculation result is the work memory (W) 20.
4 and the series of processing is completed, the data stored in the memory is transferred to the output register (OR) 225 and is output from the register to the D / A converter 107 in FIG.

On the other hand, the address offset memory (T) 2
The output of 05 is input to the register (TR) 226, and the output of the register is input to the adder 227 together with the counter value SC that is incremented at each sampling timing. The calculation result of the adder 227 is the register (EA) 2
The digital input tone signal to be added with the reverberation effect is input to the register 28 and the value of the register is stored in the delay memory (E) 106 as an address, and is supplied to the register (EO) 229 via the internal bus 207. The output of the register is supplied to the delay memory (E) 106. The output from the delay memory (E) 106, which is delayed by a predetermined amount and modulated by the difference value between the write address and the read address, is output to the register (EI) 230.

The musical tone signal data added with the reverberation effect and stored in the register (EI) 230 is transferred to the register (A0) 214, (A) via the internal bus 207, for example.
1) Transferred to 215 and output as right channel output and left channel output.

FIG. 3 shows the sound source 104 of FIG. 1 and FIG.
3 is a block diagram of the operating principle of the DSP 105 of FIG. Sound source 10
4 has 16 sounding channels based on time division processing, and the output of each channel is a multiplier 301, 302, 303.
3 weighting parameters RLn and LL
n, ELn (n represents each sounding channel number of 0 to 16) and are added to adders 304 to 3 for every three groups.
It is accumulated at 06. The accumulation results of the adders 304, 305, and 306 are the DSP 1 as the right channel direct sound R, the left channel direct sound L, and the pedal effect feed sound E.
It is given to the work memory (W) 204 in 05 (see FIG. 2 and FIG. 18 described later). The above-mentioned three types of parameters RLn, LLn and ELn are given from the key follow table of FIG. 9 which will be described later and are stored in the ROM 102 of FIG. 1 according to the keynote to be sounded. In this key follow table, as will be described later, similar to the arrangement of strings on an acoustic piano, the direct sound of the left and right channels is sounded more to the right when the keynote is higher, and to the left when it is lower, and the resonance is the keynote. Is set higher for higher notes and lower for lower notes.

In the DSP 105, the vibrato effect adding section 3 first responds to the pedal effect feed sound E set in the work memory (W) 204 (FIG. 2) from the sound source 104.
In 07, a vibrato effect is added, and subsequently, the reverb effect adding section 308 adds a reverb effect to the vibrato output VO output therefrom, and the reverb right channel output R from the reverb effect adding section 308.
The OT and the reverb left channel output LOT are added with the right channel direct sound R and the left channel direct sound L by the adders 309 and 310, respectively, and are D / A converted in FIG. 1 as the right channel musical sound output ROUT and the left channel musical sound output LOUT. It is output to the device 107. Here, a reverb time RV, which will be described later, in the reverb effect adding unit 308.
The T and reverb depth RVD are the pedal 110 of FIG.
It is continuously variably controlled according to the amount of depression.

FIGS. 4A and 4B are block diagrams of the operation principle of the vibrato effect adding section 307 of FIG. The addition unit is composed of the vibrato calculation unit of FIG. 4 (a) and the vibrato address generation unit of FIG. 4 (b).

First, in the vibrato calculation section of FIG. 4A, the pedal effect feed sound E output from the sound source 104 of FIG. 3 is delayed by the delay memory 401 and output as the vibrato output VO. The writing address when the pedal effect feed sound E is written in the delay memory 401 is incremented at every sampling timing to a constant value vibrato write address offset VW stored in an address offset memory (T) 205 described later. It is given as a write address VWA generated by adding the counter value SC. Also,
The read address when the vibrato output is read from the delay memory 401 is given as two read addresses VRA1 and VRA2 generated by adding a vibrato effect from a vibrato address generating unit described below. Then, an interpolating operation is performed on the two memory outputs read from the two read addresses of the delay memory 401 using the adders 402 and 403 and the multiplier 404 to obtain a vibrato output.

Next, the vibrato address generator of FIG. 4B is a triangular wave generator 404, a low pass filter (LPF) 405 and a vibrato address calculator 40.
It consists of 6. Then, the triangular wave generator unit 40
Triangle wave LFO (low frequency oscillation) output TR generated from 4
Based on the sinusoidal LFO signal SIN obtained by smoothing I in the LPF unit 405, read addresses VRA1 and VRA
By periodically changing 2 and accessing the delay memory 401 with these addresses, a low-frequency modulated vibrato output can be obtained.

In the triangular wave generator section 404,
One sample delay unit 40 for each sampling timing
The sawtooth LFO output SAW at the time of the previous sampling is read from 7 and the adder 408 outputs a predetermined LFO to be described later.
A signal value that increases linearly is obtained by sequentially adding the rate corresponding values RAT. At this time, the sawtooth wave LFO output SAW has a constant bit width, and if the most significant bit (MSB) is the sign bit, the value of the same output is
At each sampling timing, the value increases from 0 by RAT and reaches the maximum positive value (the most significant bit is “0” and the other bits are “1”) at the next negative timing. It jumps to a value (a value where all bits are "1"), and from there it increases linearly by RAT towards the positive maximum value again. That is, the sawtooth wave LFO output from the adder 408
The output SAW becomes a sawtooth-shaped low frequency period (LFO) signal in which the operation of linearly increasing from the negative minimum value to the positive maximum value and then jumping to the negative minimum value is repeated.

Further, in the adder / subtractor 409, when the sawtooth wave signal SAW is positive, this signal value is added to a constant coefficient value of 0.5, and conversely when it is negative, the sawtooth wave signal is added to the coefficient value. Subtracted from 0.5. As a result, the adder / subtractor 40
As an output of 9, its value increases linearly by RAT from the negative minimum value to the positive maximum value, and when it reaches the positive maximum value, it decreases linearly by RAT toward the negative minimum value. ,
When the negative minimum value is reached, a triangular wave LFO output TRI is obtained which has the characteristic of increasing linearly toward the positive maximum value again.

Next, the triangular wave LFO output TRI is input to the LPF section 405 including the multipliers 410, 413, the adder 411 and the 1-sample delay section 412, and the harmonic components of the output are cut off by the LPF section 405. , Sine wave LF
O output SIN is obtained.

Subsequently, this sinusoidal LFO output SIN
Is input to the vibrato address calculation unit 406. Here, basically, the counter value S that is incremented by the adders 415 and 416 every sampling cycle is used.
By adding the vibrato read address offset VR to C, a read address VRA2 that changes in synchronization with the write address VWA while keeping a constant offset so as to follow it is generated.

Then, in the adder 415, the sinusoidal LFO output SIN which periodically changes around the value 0 is added to the address value calculated as described above, so that the address value is cyclically changed. Fluctuation is given. As a result, the low-frequency sinusoidal LFO output SI is output from the delay memory 401 of the vibrato calculator shown in FIG.
The vibrato output VO that is frequency-modulated by N and has the vibrato effect added is read. In this case, the width of change in the depth of the vibrato effect is determined by the sine wave L
Vibrato depth factor FMD multiplied by FO output SIN
Controlled by. The value of this coefficient corresponds to the type of chord detected based on the keynote of the performance information,
It is automatically set together with the LFO rate corresponding value RAT.

Here, the following interpolation calculation is performed in order to improve the accuracy of frequency modulation. That is, first, the adder 416 generates the read address VRA2 based on the vibrato write address offset VR, and the adder 417 generates the read address VRA2 based on the vibrato write address offset VR + 1.
Read address VR having an address value obtained by adding 1 to A2
A1 is generated. Next, in the subtractor 402 of FIG. 4A, the difference value between the two outputs read from the two adjacent addresses VRA2 and VRA1 of the delay memory 401 is obtained. Then, in the multiplier 404, the sinusoidal LFO output from the multiplier 414 is added to the difference value.
By multiplying the fractional value VL of the output SIN,
A change amount corresponding to the decimal value is calculated. Then, in the adder 403, the above-mentioned variation is added to the output value of the address VRA2, so that the accurately interpolated vibrato output VO is obtained.

The width of change in the speed of the vibrato effect is
The value is controlled by the value of the LFO rate corresponding value RAT, and this value is automatically changed and set according to the type of the performance code by the player as described above.

FIG. 5 shows the reverb effect adding section 308 of FIG.
3 is a block diagram of the operating principle of FIG. In this figure, the vibrato output VO of FIG. 3 or 4 is connected to # 1 connected in series.
Eight comb filters 50 of # 1 to # 8 connected in parallel via the two-stage all-pass filters 501 and 502 of # 2.
3 to 510.

First, the vibrato output VO is input to the first-stage all-pass filter (all-pass filter) 501, where the delay component of the vibrato output VO is increased and the output signal AO1 having a large number of delay components is input. Is output to the second-stage all-pass filter 502.

In the all-pass filter 502, the delay component is further increased in the signal AO1 having the increased delay component, and the resulting output signal AO2 is a plurality of comb filters 503 of # 1 to # 8 connected in parallel. To 510.

In this embodiment, an example in which two all-pass filters 501 and 502 are inserted as all-pass filters provided before the reverberation-comb-adding comb filters 503 to 510 has been shown. The number is not limited and may be one or three or more. In this case, according to the experiment conducted by the present inventor, the best effect can be obtained when the all-pass filters are inserted in two stages in series.

The all-pass filters 501 and 502
Is a delay element 529, a multiplier 530, 531 and an adder 532, 5 as shown in FIG.
It is composed of 33. As described above, the all-pass filters 501 and 502 are fed back through the multiplier 530 on the output side with the delay element 529 interposed therebetween, and the multiplier 531 on the input side is also multiplied by the coefficient 0.5. Because of the structure in which the signals are fed forward via the, when a signal is input to the all-pass filters 501 and 502, a large number of delay components are output based on the input signal. The configurations of all-pass filters 501 and 502 are not limited to the above-described configurations, and other types of all-pass filters may be applied.

The output signal data AO2 of the above-mentioned all-pass filter 502 is inputted to eight comb filters 503 to 510 provided in parallel with # 1 to # 8. The comb filters 503 to 510 are composed of a delay element 534, a multiplier 535, and an adder 536, as shown in FIG. Each comb filter 503-51
From 0, the above-mentioned signal data AO2 corresponds to each delay element 534.
Is delayed by an amount corresponding to a different offset address (described later), and the amount of feedback to the input is delayed by each multiplier 535.
Output signals CLOi and C for the left and right channels, which are determined corresponding to the common reverb time RVT
ROi (1 ≦ i ≦ 8) is output.

Then, the comb filter right channel output C
RO1, CRO2, ... CRO8 are multipliers 511 to
In 518, after being weighted by the common reverb depth RVD, it is accumulated in the accumulator 527 and output as the reverb right channel output ROT to the adder 309 in FIG.
Similarly, the left channel comb filter outputs CLO1 and CL
O2, ..., CLO8 are also weighted by the common reverb depth RVD in the multipliers 519 to 526, accumulated in the accumulator 528, and output to the adder 310 in FIG. 3 as the reverb left channel output.

Here, the reverb time RVD supplied to the comb filters 503 to 510 is varied depending on the depression amount of the pedal 110 of FIG. 1, as will be described later, whereby different reverberation effects are obtained.

The reverb right channel output ROT and the reverb left channel output LOT obtained as described above are
The right channel direct sound R and the left channel direct sound L are added by the adders 309 and 310, respectively, and are output as a right channel musical sound output and a left channel musical sound output in FIG.
It is output to the / A converter 107. The specific operation of the embodiment shown in FIGS. 1 to 5 will be sequentially described above. First, the operation of the CPU 101 of FIG. 1 will be described based on the operation flowcharts of FIGS. 6 to 8. Note that the operations of FIGS. 6 to 8 are realized as a process in which the CPU 101 of FIG. 1 executes the program stored in the ROM 102 using the RAM 103 as a work memory. In this case, the CPU
101 executes each timer process of FIGS. 6 to 8 at regular intervals by a timer interrupt.

First, the timer 1 processing of FIG. 6 will be described. Here, a sound generation start instruction to the sound source 104 and setting of various weighting parameters are performed. First, keyboard information is read from the keyboard 108 via the interface circuit 109 and the bus 114 (step S60).
1).

Next, it is judged whether or not the keyboard information has changed since the last time it was read (step S602). If it has not changed, no processing is performed and the timer 1 processing ends.

If the keyboard information has changed, it is determined whether or not the change is due to a key depression operation (step S603). If it is a key depression operation, first,
A chord code formed by pressing a key is detected (step S604). In this detection, the keynotes of all the pressed keys are collated with, for example, a chord structure note table in the ROM 102, which stores a keynote group that forms each chord (not shown), and the type of chord (code) ) Is detected.

Next, based on the detected code, LF
The O-rate corresponding value RAT and the vibrato depth coefficient FMD are set (step S605). Regarding the setting of the LFO rate corresponding value RAT and the vibrato depth coefficient FMD, for example, code names maj, min, 7th, m7
Code numbers 1, 2, 3, ... Are assigned to th, dim, aug, sus, .... The smaller the code number is, the larger the LFO rate corresponding value RAT is. That is, the vibrato effect is delayed and the vibrato depth coefficient FMD is set to be larger. On the other hand, the larger the code number, the smaller the LFO rate corresponding value RAT, that is, the vibrato effect is faster, and the vibrato depth coefficient F is larger.
MD is also set small. Of course, the reverse setting is also possible, that is, the smaller the code number, the smaller the LFO rate corresponding value RAT, while the larger the code number, the L
The FO rate corresponding value RAT may be set to be large.

Then, the LFO rate corresponding value RAT and the vibrato depth coefficient FMD set in the RAM 103 as described above are transferred to the DSP 105 (step S606).

In another embodiment described later, steps S604 and S60 surrounded by a broken line S600.
5 and S606 are omitted, and other processes are performed instead.

Subsequently, a vacant channel is selected from the 16 tone generation channels (see the explanation of FIG. 3), and the key depression channel "n" is set (step S607). Next, "1" is set to the gate flag KOn which is a variable on the RAM 103 corresponding to the key depression channel "n". This flag has 16 sound generation channels and its value is "1".
If this is the case, it indicates that the sound generation channel is in the key depression state. In addition, the RAM 10 corresponding to the key depression channel "n"
The keynote corresponding to the depressed key is set in the keynote KNn which is a variable above 3 (above, step S6
08). This keynote KNn is also provided with 16 sound generation channels.

The right channel panning weighting parameter RLn, the left channel panning weighting parameter LLn and the resonance volume weighting parameter ELn corresponding to the key note KNn are read from the key follow table in the ROM 102 and set in the RAM 103. (Step S609). FIG. 9 shows an example of conversion characteristics of the key follow table stored in the ROM 102. FIG. 10A is a right channel panning key follow table, and the weighting parameter RLn for right channel panning having a larger value is output as the key note KNn indicates a higher tone key. FIG. 11B shows a left channel panning key follow table, in which the left channel panning weighting parameter LLn having a smaller value is output as the key note KNn indicates a higher tone key. Further, FIG. 7C is a resonance volume key follow table, and the resonance volume weighting parameter ELn having a larger value is output as the key note KNn indicates a higher tone key.

The keynote KNn, the right channel panning weighting parameter RLn, the left channel panning weighting parameter LLn and the resonance volume weighting parameter ELn set in the RAM 103 as described above are transferred to the sound source 104 ( Step S6
10).

The sound source 104 time-divisionally generates a digital tone signal by the existing digital signal processing technique for each sounding channel. Then, the respective sounding channel outputs are multiplied by the three types of weighting parameters RLn, LLn, ELn transferred from the CPU 101 by the above-mentioned processing by the multipliers 301, 302, 303, and the adders 304 to Accumulated in 306,
Right channel direct sound R, left channel direct sound L
And pedal effect feed sound E are output.

Here, the above three types of parameters RL
n, LLn and ELn are keynotes KNn to be sounded
According to the conversion characteristics of the key follow table of FIG. Due to this characteristic, similar to the string arrangement of an acoustic piano, the left and right channel direct sounds are localized by being sounded to the right and higher of the key note, and lower to the left, and the resonance sound is raised as the key note is higher. The lower the tone, the lower the setting.

On the other hand, if it is determined in step S603 that the change in the key information is due to the key release operation and not the key release operation, the released keynote is RA.
The key release channel “n” is searched by comparing with the key note KNn of each tone generation channel during key depression registered in M103 (step S611).

Then, the RAM1 corresponding to the channel
The gate flag KOn on 03 is set to "0", and the sound source 104 is instructed to release the key (step S61).
2). Next, the timer 2 processing of FIG. 7 will be described. Here, setting of envelope data for the sound source 104 is performed.

Here, first, the gate flag KOn set in the RAM 103 (see step S608 in FIG. 6).
And pedal data PD indicating the amount of depression of the pedal 110 input via the A / D converter 111 and the bus 114.
Based on and, envelope data for controlling the tone volume and tone color of the musical tone is calculated (step S701). That is, the creation of envelope data is started for the sounding channel for which the gate flag KOn is newly set to "1", and it corresponds to each section of ADSR (attack, decay, sustain, release) from the sounding start to the mute at that time. Each value of the envelope including the rate value and the target level is variably controlled based on the pedal data.

Then, the envelope data thus obtained is transferred to the sound source 104 (step S70).
2). The sound source 104 generates an envelope signal based on this, and controls the volume or tone color envelope of the generated musical tone.

Next, the timer 3 processing of FIG. 8 will be described. Here, the reverb depth RVD and the reverb time RVT are set for the DSP 105. First, the depression amount of the pedal 110 is read from the A / D converter 111 as pedal data PD which is a variable on the RAM 103 (step S801).

Then, it is determined whether or not this pedal data PD has changed since the last reading (step S802). If it has not changed, no processing is performed and the timer 3 processing is ended.

If the pedal data PD has changed,
The reverb table on the ROM 102 is accessed according to the value, the corresponding reverb depth RVD and the reverb time RVT are read, and set in the RAM 103 (step S803). FIG. 10 shows an example of conversion characteristics of the reverb table.

Then, the reverb depth RVD and the reverb time RVT thus obtained are calculated by the DSP 10
5 in the coefficient memory (P) 203 (see FIG. 2 and FIG.
7)) (step S804).

Here, the reverb depth RVD and the reverb time RVT are supplied to the comb filters 503 to 510 and the multipliers 511 to 526 as described with reference to FIG. 5, and these are based on the table characteristics shown in FIG. Different reverberation sounds can be obtained by varying the pedal depression amount. That is, the greater the depression amount of the pedal 110, the deeper the reverberation is and the longer the reverberation time is. Of course, this characteristic can be changed arbitrarily.

Next, the DSP 105 of FIG. 1, FIG. 2 or FIG.
The operation will be described based on the operation flowcharts of FIGS. 11 to 16. Note that these operations are realized as a process in which the DSP 105 shown in FIG. 1 or 2 executes the microprogram stored in the program memory 201.

In each operation flowchart, for example, P
(RAT) is stored in the coefficient memory (P) 203 of FIG. 2 and indicates the content of the coefficient (constant) whose name is RAT. Similarly, for example, W (SAW), T (VW)
Are stored in the work memory (W) 204 and the address offset memory (T) 205 of FIG. 2, respectively, and indicate the contents of variables (may be constants) whose names are SAW and VW. Here, the addresses, names and contents of the coefficients (constants) or variables stored in each memory are as shown in FIGS. 17 to 19. Furthermore, E
It is assumed that (EA) indicates the address content designated by the address value of the register (EA) 228 of the delay memory (E) 106 of FIG.

First, referring to the operation flowcharts of FIGS. 11 to 13, the reverb effect adding unit 308 of FIG. 3 or FIG.
1 or 2 for realizing the function of FIG.
The operation of will be described.

FIG. 11 shows the DS of FIG. 1 or 2 in order to realize the function of the triangular wave generator 404 of FIG. 4 (b).
It shows the processing operation executed by P105. First, the contents of the sawtooth LFO output SAW (see FIG. 18) are read from the work memory (W) 204 and set in the register (A0) 214 (step S110).
1). The initial value of this value may be any value.

Next, from the coefficient memory (P) 203 to the LFO
The content (see FIG. 17) of the rate corresponding value RAT is read and set in the register (A1) 215 (step S1102).

Then, the adder / subtractor 217 adds the value to the register (A0) 214 and the value of the register (A1) 215, and the addition result is obtained in the register (AR) 222. It is stored in the SR) 224 (step S1103). As a result, processing equivalent to the function of the adder 408 in FIG. 4B is realized.

At the same time, the constant 0.5 (see FIG. 17) stored in the coefficient memory (P) 203 is set in the register (A
0) 214 (also step S110)
3). Subsequently, the sign of the addition result obtained in the register (AR) 222 is determined (step S1104).

In step S1104, the register (A
If it is determined that the contents of R) 222 have a positive value,
Contents of register (SR) 224 (= register (AR) 2
22) is stored in the work memory (W) 204 as a new sawtooth LFO output SAW, and the adder / subtractor 2
At 17, the content of the register (AR) 222 is added to the constant 0.5 stored in the register (A0) 214, and the addition result is newly obtained in the register (AR) 222 (step S1105).

On the other hand, if it is determined in step S1104 that the content of the register (AR) 222 has a negative value, the content of the register (SR) 224 (= the content of the register (AR) 222) is changed to a new sawtooth wave. LFO output SAW
Is stored in the work memory (W) 204 as
In the adder / subtractor 217, the content of the register (AR) 222 is subtracted from the constant 0.5 stored in the register (A0) 214, and the addition result is newly added to the register (A
R) 222 (step S1106).

By the above operation, the adder / subtractor 4 of FIG.
Processing equivalent to the function of 09 is realized. The value thus obtained in the register (AR) 222 is stored in the register (S).
R) 224 and then stored in the work memory (W) 204 (see FIG. 18) as the triangular wave LFO output TRI (step S1107).

Next, FIG. 12 shows the LPF section 40 of FIG.
5 to realize the function of FIG.
5 shows the processing operation executed by the control unit 5. First, the LFO filter coefficient G of the coefficient memory (P) 203
(See FIG. 17) is read to the register (M0) 212. Further, the contents of the triangular wave LFO output TRI stored in the work memory (W) 204 by the processing of FIG. 11 described above are read to the register (M1) 213 (step S1201).

Then, in the multiplier 216, the value of the register (M0) 212 and the value of the register (M1) 213 are multiplied, and the multiplication result is registered in the register (MR) 221.
(Step S1202). As a result, FIG.
Processing equivalent to the function of the multiplier 410 in (b) is realized.

Along with this, L of the coefficient memory (P) 203
The FO filter coefficient 1-G (value obtained by subtracting the value G from the value 1) is read out to the register (M0) 212, and the sinusoidal LFO output SIN on the work memory (W) 204 is read.
(See FIG. 18) is read to the register (M1) 213 (also step S1202).

Next, the result of multiplying the triangular wave LFO output TRI obtained in the register (MR) 221 by the coefficient G is transferred to the register (AR) 222 via the adder / subtractor 217 (step S1203).

Further, in the multiplier 216, step S
The value of the register (M0) 212 set in 1102 is multiplied by the value of the register (M1) 213, and the multiplication result is obtained in the register (MR) 221 (also step S1203). As a result, the multiplier 413 of FIG.
Processing equivalent to the function of is realized.

Then, in the adder / subtractor 217, the register (A
The value of R) 222 and the value of register (MR) 221 are added, and the addition result is newly set in register (AR) 222 (step S1204). This content is further stored in the register (SR) 224 (step S1).
205). As a result, processing equivalent to the function of the adder 411 shown in FIG. 4B is realized.

In this way, the register register (SR)
The value obtained in 224 is the new sinusoidal LFO output SI.
It is stored in the work memory (W) 204 as N (step S1206).

Next, FIG. 13 shows a process executed by the DSP 105 of FIG. 1 or 2 in order to realize the functions of the vibrato address operation unit 406 of FIG. 4B and the vibrato operation unit of FIG. 4A. It shows an operation.

First, as explained in FIG. 3, the sound source 104
And the work memory (W) 20 in the DSP 105
4 (FIG. 2), the pedal effect feed sound E (see FIG. 18) is read into the register (EO) 229. Also,
The adder 227 adds the vibrato write address offset VW (see FIG. 19) read from the address offset memory (T) 205 to the counter value SC generated from the control circuit 202 at each sampling timing. Is set in the register (EA) 228 as the write address VWA (step S130).
1).

Next, the pedal effect feed sound E read out to the register (EO) 229 is stored in the delay memory (E) 106.
It is written to the write address VWA set in the upper register (EA) 228 (step S1302). As a result, a process equivalent to the function of writing the pedal effect feed sound E in the delay memory 401 in FIG. 4A is realized.

Next, the vibrato depth coefficient FMD stored in the coefficient memory (P) 203 is stored in the register (M0).
It is read by 212. In addition, the sinusoidal LFO obtained in the work memory (W) 204 by the processing of FIG.
The output SIN is read by the register (M1) 213 (step S1303).

Then, the value of the multiplier 216 and the register (M
1) The value of 213 is multiplied, and the multiplication result is obtained in the register (MR) 221 (step S1304). As a result, processing equivalent to the function of the multiplier 414 of FIG. 4B is realized.

Next, the integer part (upper bit) of the multiplication result obtained in the register (MR) 221 is added / subtracted by the adder / subtractor 21.
7 and the register (AR) 222 through the register (L
F) 231 is stored. In addition, the above register (MR)
The value of 221 is the address 0 of the work memory (W) 204.
8 is stored as interpolation LFO data VL (FIG. 18).
(See step S1305).

Subsequently, the adder 227 adds the integer part of the multiplication result read by the register (LF) 231 to the counter value SC generated from the control circuit 202 at each sampling timing, and once, Register (ER)
232, and the adder 227 also adds the vibrato read address offset VR (see FIG. 19) read from the address offset memory (T) 205 to the value of the register (ER) 232. Register (EA) whose value is read address VRA2
It is set to 228 (step S1306). As a result, processing equivalent to the functions of the adders 415 and 416 in FIG. 4B is realized.

Then, as described above, the register (EA) 2
The delay memory (E) 106 is accessed by the read address VRA2 set to 28, the waveform data (see step S1302) written at the sampling timing before the previous time is read from the address, and the register (EI) 230 is read. Stored (step S130)
7). As a result, a process equivalent to the function of reading data from the address VRA2 of the delay memory 401 in FIG. 4A is realized.

Further, in the adder 227, the counter value S generated from the control circuit 202 at each sampling timing is added.
The integer part of the above-mentioned multiplication result read to the register (LF) 231 is added to C, and once the register (E
R) 232, and also in the adder 227,
The vibrato read address offset VR + 1 (see FIG. 19) read from the address offset memory (T) 205 is added to the value of the register (ER) 232, and the added value is set in the register (EA) 228 as the read address VRA1. Yes (also step S1
307). As a result, the adders 415 and 4 of FIG.
Processing equivalent to the 17 functions is realized.

Then, in step S1307, the output value from the address VRA2 obtained in the register (EI) 230 is saved in the register (A0) 214 and then set in the register (EA) 228 as described above. The delay memory (E) 106 is accessed by the read address VRA1, and the waveform data written from that address at the sampling timing before the previous time (step S1302).
(Reference) is read and stored in the register (EI) 230 (step S1308). As a result, processing equivalent to the function of reading data from the address VRA1 of the delay memory 401 in FIG. 4A is realized.

The output from the address VRA1 thus obtained in the register (EI) 230 is the register (A
1) It is stored in 215 (step S1309). Next, in the adder / subtractor 217, the output value from the address VRA2 stored in the register (A1) 215 as described above is subtracted, and the subtraction result is registered in the register (AR) 22.
2 is obtained (step S1310). As a result, processing equivalent to the function of the subtractor 402 shown in FIG. 4A is realized.

The contents of the register (AR) 222 are further stored in the register (SR) 224 (step S1).
311). Also, the interpolation LFO data VL stored in the work memory (W) 204 in the process of step S1305.
The fractional part (lower bit) of is read into the register (M0) 212 (also step S1311).

Then, in the multiplier 216, the value of the register (M0) 212 is multiplied by the difference value obtained in the register (SR) 224, and the multiplication result is obtained in the register (MR) 221 (step S1312). ). As a result, processing equivalent to the function of the multiplier 404 shown in FIG. 4A is realized.

Along with this, the address VRA2 stored in the register (A0) 214 in step S1308
The output value from is transferred to the register (A1) 215 (also step S1312).

Then, in the adder / subtractor 217, the value of the register (MR) 221 and the register (A1) 21 are added.
The value of 5 is added, and the result of the addition is added to the register (A
R) 222 (step S1313). As a result, processing equivalent to the function of the multiplier 403 of FIG. 4 (a) is realized.

Then, the addition result obtained in the register (AR) 222 is the address 0 of the work memory (W) 204.
9 and is stored as the vibrato output VO (see FIG. 18) (step S1314).

As described above, the DSP 10 of FIG. 1 or FIG.
5 repeats the program of the processing shown in the operation flowcharts of FIGS. 11 to 13 at every sampling timing, so that the vibrato effect adding unit 3 of FIG.
The 07 function is realized.

Next, referring to the operation flowcharts of FIGS. 14 to 16, the reverb effect adding section 308 of FIG. 3 or 5 will be described.
1 or 2 for realizing the function of FIG.
The operation of will be described.

FIG. 14 shows the all-pass filter 50 of FIG.
1 to realize the function of FIG.
5 shows the processing operation executed by the control unit 5. First, in the adder 227, the read address offset AR1 of the all-pass filter 501 read from the address offset memory (T) 205 is added to the counter value SC generated from the control circuit 202 at each sampling timing.
(See FIG. 19) is added, and the added value is set in the register (EA) 228 as an address value (step S1401).

Next, as described above, the register (EA) 22
The delay memory (E) 10 with the address value set to 8
6 is accessed, the waveform data written at the previous sampling timing is read from that address,
It is stored in the register (EI) 230 (step S14).
02).

Next, the above-mentioned waveform value stored in the register (EI) 230 is transferred to the register (M1) 213 and the register (A0) 214. At the same time, the coefficient value 0.5 is read from the coefficient memory (P) 203 and set in the register (M0) 212 (the above is step S).
1403).

Then, in the multiplier 216, the value of the register (M0) 212 in which the coefficient value 0.5 is set, and the register (M1) 213 in which the waveform value from the delay memory (E) 106 is set. Is multiplied by the value of and the value is set in the register (MR) 221 (step S
1404).

Through the operations in steps S1401 to S1404, the waveform value of one sampling period before is read from the delay element 529 in the all-pass filter 501 of FIG. 5, and the multiplier 529 multiplies the waveform value by 0.5. Processing equivalent to the function is realized.

At the same time, the vibrato output VO generated by the above-described processing by the vibrato effect adding unit 307 is read from the work memory (W) 204 and set in the register (A1) 215 (also in step S1).
404).

Next, in the adder / subtractor 217, the vibrato output V set in the above-mentioned register (A1) 215 is set.
The value of the register (MR) 221 in which the above-mentioned multiplication value is set is added to the value of O, and this added value is set in the register (AR) 222 (step S140).
5). Then, the addition result of this register is moved to the output register (SR) 224 (step S140).
6). As a result, processing equivalent to the function of the adder 532 of the all-pass filter 501 in FIG. 5 is realized.

Then, the value of the register (SR) 224 is stored in the register (EO) 229. The adder 227 reads the sampling counter value SC from the address offset memory (T) 205 and writes the write address offset AW1 of the all-pass filter 501.
Is added and set in the register (EA) 228 (step S1407).

At the same time, the multiplier 216 causes the coefficient values 0.
The value of the register (M0) 212 in which 5 is set and the value of the register (SR) 22 set in step S1406
4 is multiplied and the value is multiplied by the register (MR) 221.
Is set to (also step S1407). Thereby, the multiplier 531 of the all-pass filter 501 of FIG.
The processing equivalent to the processing in (3) is realized.

Further, the delay memory (E) 106 stored in the register (A0) 214 in step S1403.
Waveform data of the previous sampling timing from
Moved to register (A1) 215 (also step S
1407).

Next, in step S1407, the register (E
The value set in (O) 229 is stored in the delay memory (E) 106 using the value stored in the register (EA) 228 calculated in step S1407 as an address (step S1408). As a result, the output of the adder 532 of the all-pass filter 501 of FIG.
Processing equivalent to the function stored in 29 is realized.

In addition, in the adder / subtractor 217, the multiplication result also obtained in the register (MR) 221 is subtracted from the waveform data set in the register (A1) 215 in step S1407, and the result is registered in the register (AR) 22.
2 (also step S1408), and the register value is further transferred to the output register (SR) 224 (step S1409). As a result, processing equivalent to the function of the adder 533 of the all-pass filter 501 of FIG. 5 is realized.

Finally, the output result obtained in the above register (SR) 224 is stored in the work memory (W) 204 as the data AO1 (step S1410). As a result, the output signal AO1 of the all-pass filter 501 of FIG. 5 is obtained.

As described above, the DSP 10 of FIG. 1 or FIG.
5 repeats the program of the process shown in the operation flowchart of FIG. 14 at each sampling timing, whereby the function of the all-pass filter 501 of FIG. 5 is realized.

Next, in order to realize the function of the all-pass filter 502 of FIG. 5, the DSP 105 has only to execute the same processing program as the operation flowchart of FIG. 14 on the output AO1 of the all-pass filter 502. , By this, output to the work memory (W) 204 AO
2 is obtained (see FIG. 18).

Next, FIG. 15 shows the comb filter 5 of FIG.
In order to realize the function of 03, DSP1 of FIG. 1 or FIG.
5 shows processing operations executed by 05. First, in the adder 227, the counter value SC generated from the control circuit 202 at each sampling timing is added to the right channel read address offset CRR1 of the comb filter 503 read from the address offset memory (T) 205 (see FIG. 19). Is added, and the added value is set as an address value in the register (EA) 228 (step S1501).

Next, as described above, the register (EA) 22
The delay memory (E) 10 with the address value set to 8
6 is accessed, the waveform data written at the previous sampling timing is read from that address,
The waveform data for the right channel is stored in the register (EI) 230 (step S1502).

Next, in the adder 227, the counter value S generated from the control circuit 202 at each sampling timing is added.
The left channel read address offset CLR1 of the comb filter 503 read from the address offset memory (T) 205 is added to C, and the added value is set in the register (EA) 228 as an address value (step S1503).

In step S1503, the register (E
I) The right channel waveform data set in 230 is transferred to the register (M0) 212, and stored in the work memory (W) 204 at the address 0C shown in FIG. 18 as the right channel output CRO1 of the comb filter 503. (Also step S1503). This allows
Processing equivalent to the function of outputting the right channel output CRO1 from the delay element 534 of the comb filter 503 of FIG. 5 is realized.

Further, the reverb time RVT is read from the coefficient memory (P) 203 (see FIG. 17) and set in the register (M1) 213 (also step S15).
03).

Next, in step S1503, the register (E
A) The memory for delay (E) 106 is accessed with the address value for the left channel set in 228, the waveform data written at the previous sampling timing is read from that address, and left in the register (EI) 230. It is stored as the waveform data for the channel (step S1504).

Then, in the multiplier 216, step S15
The waveform data for the right channel set in the register (M0) 212 in 03 and the register (M1) 213
Is multiplied by the reverb time RVT set in (1), and the multiplication result is stored in the register (MR) 221 (step S1504). As a result, processing equivalent to the function of the multiplier 535 of the comb filter 503 of FIG. 5 is realized.

At the same time, the output AO2 of the all-pass filter 502 (FIG. 5) stored in the work memory (W) 204 is read by the register (A1) 215 (also step S1504).

Next, in step S1504, the register (E
I) The left channel waveform data set in 230 is output to the left channel output C of the comb filter 503 at the address 14 shown in FIG. 18 of the work memory (W) 204.
It is stored as LO1 (step S1505). As a result, the delay element 534 of the comb filter 503 of FIG.
The processing equivalent to the function of outputting the output CLO1 for the left channel is realized.

Further, in the adder / subtractor 217, the multiplication result obtained in the register (MR) 221 in step S1504 and the output AO2 of the all-pass filter 502 stored in the register (A1) 215 in step S1504 are added, and the addition is performed. The result is obtained in the register (AR) 222 (step S1503). Then, the register value is stored in the output register (SR) 224 (step S1506). As a result, the comb filter 5 of FIG.
A process equivalent to the function of the adder 536 of 03 is realized.

Then, in the adder 227, the address offset memory (T) is added to the sampling counter value SC.
The write address offset CW1 of the comb filter 503 read from 205 is added to the register (EA).
228 is set. In addition, the register (SR) 224
The above addition result stored in the register is the register (EO) 229.
Is stored in (step S1507).

Then, the value set in the register (EO) 229 is stored in the delay memory (E) 106 using the value stored in the register (EA) 228 as an address (step S1508). As a result, the output of the adder 536 of the comb filter 503 of FIG.
Processing equivalent to the function stored in 34 is realized.

As described above, the DSP 10 of FIG. 1 or FIG.
5 repeats the program of the processing shown in the operation flowchart of FIG. 15 at each sampling timing, whereby the function of the comb filter 503 of FIG. 5 is realized.

Next, the other comb filters 504 to 5 shown in FIG.
In order to realize the 10 functions, the DSP 105 may execute a program of processing similar to that of the operation flowchart of FIG. 15 on the output AO2 of the all-pass filter 502. The comb filter outputs CRO2 to CRO8 for the right channel and outputs CLO2 to CLO8 for the left channel are obtained (see FIG. 18).

Finally, FIG. 16 shows the multipliers 511 to 511 of FIG.
3 illustrates processing operations performed by the DSP 105 of FIG. 1 or 2 to implement the accumulation function of 518 and accumulator 527.

First, the reverb depth RVD corresponding to the weighting coefficient to be applied to each channel output from each comb filter is read from the coefficient memory (P) 203 and set in the register (M0) 212. Further, the output CRO1 for the right channel of the comb filter 503, which is obtained based on the operation flowchart of FIG. 15, is read from the work memory (W) 204 and set in the register (M1) 213 (above, step S1601). .

Next, in the multiplier 216, the register (M0)
The reverb depth RVD set in 212 is multiplied by the right channel output CRO1 of the comb filter 503 set in the register (M1) 213, and the multiplication result is set in the register (MR) 221 (step S
1602). As a result, processing equivalent to the function of the multiplier 511 of FIG. 5 is realized.

Further, the right channel output CRO2 of the comb filter 504 is read from the work memory (W) 204 to the register (M1) 213 (also step S1).
602).

Subsequently, after the contents of the register (MR) 221 are transferred to the register (AR) 222, the multiplier 216
At the right channel output CRO2 of the comb filter 504 set in the register (M1) 213, the reverb depth RV set in the register (M0) 212 is set.
D is multiplied, and the multiplication result is the register (MR) 221.
(Step S1603). As a result, FIG.
A process equivalent to the function of the multiplier 512 of is realized.

Hereinafter, each of the comb filters 505 to 51 shown in FIG.
For the right channel outputs CRO3 to CRO8 of 0,
Similarly, the reverb depth RVD is multiplied. Then, each multiplication result obtained in the register (MR) 221 is
In the adder / subtractor 217, the accumulated value obtained in the register (AR) 222 is sequentially accumulated, and a new register (A
R) 222 (steps S1604 to S16)
10). In this way, the multipliers 513 to 518 of FIG.
And a function equivalent to the function of the accumulator 527 are realized.

The right channel outputs CRO1 to CRO8 of the comb filters 503 to 510 are weighted with the reverb depth RVD, and the accumulated results are stored in the register (A
When the contents are obtained by the R) 222, the contents are transferred to the output register (SR) 224 (step S1611), and the contents of the register (SR) 224 are stored in the work memory (W) 204
Output R for the reverb right channel at address 1D in FIG.
It is stored as OT (step S1612).

This reverb right channel output R
The OT is set in the signal output register (OR) 225, and is output as the reverb right channel output ROT from the reverb effect adding unit 308 of FIG. 3 (step S1613).

As described above, the DSP 105 of FIG. 1 or FIG.
However, the accumulating function of the multipliers 511 to 518 and the accumulator 527 of FIG. 5 is realized by repeating the program of the process shown in the operation flowchart of FIG. 16 at each sampling timing.

Next, in order to realize the accumulation function of the multipliers 519 to 526 and the accumulator 528 of FIG.
It suffices for 105 to execute a program of the same processing as the operation flowchart of FIG. 16 for each of the left channel outputs CLO1 to CLO8 of the comb filters 503 to 510, whereby the work memory (W) 204 of FIG. The reverb left channel output LOT is obtained at the address 1E of 1. and is set in the signal output register (OR) 225, and is output as the reverb left channel output LOT from the reverb effect adding unit 308 of FIG.

As described above, the DSP 10 of FIG. 1 or FIG.
5 repeats the program of the processing shown in the operation flowcharts of FIGS. 14 to 16 at each sampling timing, so that the reverb effect adding unit 30 of FIG.
8 functions are realized.

Finally, the operation of the DSP 105 of FIG. 1 or 2 for realizing the functions of the adders 309 and 310 of FIG. 3 will be described. That is, the DSP 105 of FIG.
First, as described above, the sound source 104 to the DSP 105
The right channel direct sound R obtained in the work memory (W) 204 therein is read out to the register (A0) 214, and the reverb right channel similarly obtained in the work memory (W) 204 by the processing of FIG. Output RO
T is read into the register (A1) 215. And
In the adder / subtractor 217, the contents of both registers are added, and the addition result is stored in the address 1F of the work memory (W) 204 as the right channel tone output ROUT via the register (AR) 222 and the register (SR) 224. After that, it is transferred to the output register (OR) 225 and is output from the same register to the D / A converter 107 in FIG.
As a result, processing equivalent to the function of the adder 309 in FIG. 3 is realized.

Similarly, for the left channel, the left channel direct sound L from the sound source 104 on the work memory (W) 204, the reverb left channel output LOT and the adder / subtractor 217 are added, and the addition result is the work memory. (W) Left channel tone output L at address 20 of 204
After being stored as OUT, the output register (OR) 22
5 to the D / A converter 10 of FIG.
7 is output. As a result, processing equivalent to the function of the adder 310 in FIG. 3 is realized.

In the above embodiment, the value of the vibrato depth coefficient FMD for controlling the change width of the depth of the vibrato effect and the LFO for controlling the change width of the speed of the vibrato effect.
The value of the rate corresponding value RAT is automatically changed and set according to the type of chord detected based on the keynote of the performance information. That is, the depth and speed of the vibrato effect are changed in association with the key depression operation of the chord sound on the keyboard. On the other hand, the value of the vibrato depth coefficient FMD and the value of the LFO rate corresponding value RAT may be configured to change according to the depression amount of the pedal as in the case of the reverb effect. The specific operation of another embodiment having such a configuration will be described below.

First, the configuration is exactly the same as the configurations of FIGS. 1 to 5 in the above-described embodiment. Next, regarding the specific operation, among the processing described in the operation flowcharts of the CPU of FIGS. 6 to 8, the processing of steps S604, S605, and S606 surrounded by the broken line S600 of the timer 1 processing of FIG. Not executed and timer 3 in FIG.
The process is replaced by the timer 3 process in FIG. The operation of this part will be described below. It should be noted that description of the configuration and operation of the same parts as those in the above-described embodiment will be omitted.

A timer 3 in another embodiment shown in FIG.
In the processing, the processing of steps S2001 to S2003 is the same as the processing of steps S803 to S803 in the timer 3 processing of the embodiment shown in FIG.

In step S2003 of FIG. 20,
As described in the above-described embodiment, the reverb table on the ROM 102 is accessed according to the changed value of the pedal data PD, and the corresponding reverb depth RVD and reverb time RVT are read and set in the RAM 103. .

Similarly, in accordance with the changed value of the pedal data PD, a vibrato table (not shown) on the ROM 102 is accessed, the corresponding vibrato depth coefficient FMD and the LFO rate corresponding value RAT are read, and the RAM 103 is read. Is set to (step S200
4). This vibrato table is the same table as the reverb table shown in FIG. 10, and the vibrato depth coefficient FMD is set to the reverb depth RVD in the figure to LF.
The O-rate corresponding value RAT is configured to correspond to the reverb time RVT shown in FIG.

Then, in this way, the above step S2
Reverb depth RV obtained in 003 and S2004
D, reverb time RVT, vibrato depth coefficient FMD
And the LFO rate corresponding value RAT are transferred to the coefficient memory (P) 203 in the DSP 105 (step S200).
5).

Here, the reverb depth RVD and the reverb time RVT are supplied to the comb filters 503 to 510 and the multipliers 511 to 526 as described with reference to FIG. 5, and based on the table characteristics shown in FIG. Different reverberation sounds can be obtained by varying the pedal depression amount. That is, the larger the depression amount of the pedal 110 is, the deeper the reverberation is and the longer the reverberation time is, as described in the above-described embodiment.

Also, vibrato depth coefficients FMD and LF
As described with reference to FIG. 4, the O-rate corresponding value RAT is supplied to the multiplier 414 of the vibrato address operation unit 406 and the adder 408 of the triangular wave generator unit 404, which is similar to the reverb table of FIG. Different fluctuation effects can be obtained by varying the pedal depression amount based on the table characteristics determined by the working table. That is, the larger the depression amount of the pedal 110, the deeper the fluctuation and the longer the fluctuation time. In this case, the right pedal may control the vibrato effect and the left pedal may control the reverb effect. Of course, the reverse is also possible.

Thus, according to the above-mentioned other embodiment,
The control of the vibrato effect can be realized by the information on the depression amount from the pedal 110. Note that the operation of the DSP 105 of FIG. 1, FIG. 2 or FIG. 3 in this embodiment is exactly the same as that described based on the operation flowcharts of FIGS.

[0149]

According to the present invention, a vibrato effect is applied to an acoustic signal to which a reverberation effect is applied.
Therefore, the frequency of the reverberant sound generated changes intricately.
As a result, it is possible to realize an effector capable of adding a reverberation effect sufficient to imitate the box sound or resonance sound of a natural musical instrument such as an acoustic piano to the output acoustic signal.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a DSP.

FIG. 3 is a block diagram of an operation principle of a sound source and a DSP.

FIG. 4 is a block diagram of an operation principle of a vibrato effect adding section.

FIG. 5 is a block diagram of an operation principle of a reverb effect adding unit.

FIG. 6 is an operation flowchart of CPU timer 1 processing.

FIG. 7 is an operation flowchart of a timer 2 process of the CPU.

FIG. 8 is an operation flowchart of a timer 3 process of the CPU.

FIG. 9 is a diagram showing a key follow table.

FIG. 10 is a diagram showing a reverb table.

FIG. 11 is an operation flowchart of a triangular wave generator unit.

FIG. 12 is an operation flowchart of the LPF unit.

FIG. 13 is an operation flowchart of a vibrato calculator.

FIG. 14 is an operation flowchart of the DSP that realizes the function of the all-pass filter of the reverb effect adding unit.

FIG. 15 is an operation flowchart of the DSP that realizes the function of the comb filter of the reverb effect adding unit.

FIG. 16 is an operation flowchart of the DSP that realizes the right channel accumulation operation in the reverb effect adding unit.

FIG. 17 is a diagram showing a coefficient memory map.

FIG. 18 is a diagram showing a work memory map.

FIG. 19 is a diagram showing an address offset memory map.

FIG. 20 is an operation flowchart of another embodiment of the timer 3 processing of the CPU.

[Explanation of symbols]

 101 CPU 102 ROM 103 RAM 104 Sound Source 105 DSP 106 Delay Memory 108 Keyboard 110 Pedal

Claims (6)

[Claims] 1. A generator for generating an acoustic signal , and a vibra for the acoustic signal generated by the generator.
A first output means for imparting over-effective, and second output means for outputting the relative output signal of the first output means to impart reverberation effect, the output of the second output means An effector comprising: a third output means for synthesizing and outputting a signal and an acoustic signal generated by the generating means. 2. A first performance operator is further provided, and the first performance operator is provided .
2. The effector according to claim 1, further comprising: first control means for controlling a characteristic of the vibrato effect imparted by the first output means based on an operation of the performance operator. 3. further comprising a second performance operators, the second
2. The musical tone generating apparatus according to claim 1, further comprising second control means for controlling the characteristic of the reverberation effect imparted by the second output means based on the operation of the performance operator. 4. The first control means adds vibrato effect by the first output means based on information indicating the type of chord input by the operation of the first performance operator .
2. The musical tone generating apparatus according to claim 1 , wherein the characteristic of control is controlled . Wherein said first performance operators, the effector of claim 2 or 4, characterized in that a keyboard. 6. The second performance operator is a pedal.
The effector according to claim 3, wherein: