JPH0786787B2 - Microcomputer - Google Patents

Description

The present invention relates to a microcomputer, and more particularly to a microcomputer capable of selecting from a plurality of clock signals as a clock source signal of a CPU.

[Conventional technology]

Microcomputers are applied in various fields such as consumer fields and industrial fields, and the performances such as processing speed and power consumption required for microcomputers also vary depending on these fields of application. Furthermore, the contents controlled by the microcomputer in one system are various. For example, in application to a camera, low power consumption is an absolute requirement, but during mechanical control, high-speed processing is required and power consumption increases. On the other hand, high-speed processing is not required for detection of pressing of switches and buttons during non-shooting, date display, and the like. Therefore, if the average power consumption is reduced as much as possible by changing the processing speed during mechanical control and when not, it is very effective in extending the life of the battery or battery.

These problems such as speed and power depend on the operating clock of the microcomputer, and it is important to be able to change the operating clock according to the processing content.

Here, in the conventional microcomputer, the signal of the oscillation circuit or the input clock from the outside is generated as it is or by dividing the frequency to generate the operation clock. Usually, the frequency of the oscillator connected to the oscillation circuit is changed or The operating speed cannot be changed unless the frequency of the input clock is changed,
It is impossible to change the speed according to the processing content.

On the other hand, in recent years NEC Corporation μPD75
A mode register for switching the operating speed of the CPU like 19 is built in, and one frequency division output is selected from the frequency division stage output of the frequency division circuit that divides the oscillation circuit output or external input clock by instruction operation. Then, a microcomputer that can change the operating clock of the CPU has also appeared.

[Problems to be Solved by the Invention]

In the former case, the operating speed cannot be switched, so of the various processing contents of the microcomputer, there is no choice but to set the oscillation frequency or the external input clock frequency so that the processing requiring the highest speed operation can be achieved as intended.
Therefore, since the operating power supply voltage range is limited to around 5V,
There is a drawback that the application range of the microcomputer becomes narrow, and there is a drawback that the average power consumption of the whole becomes large.

On the other hand, in the latter case, the speed can be switched by command operation, so by setting to the low-speed processing mode, it is possible to operate at low power supply voltage and the application range is widened, but it is low speed because it is changed by command operation. Even if an interrupt that requires high-speed processing occurs during operation, the previous low-speed operation continues until the end of the instruction that changes the operation speed that is executed first in interrupt processing. It has a drawback that the response speed until it becomes slow.
In particular, in an application in which the response speed is a problem, there is a drawback that the high speed operation mode must be set even in the normal operation, and the average power consumption also increases.

[Means for Solving the Problems]

A microcomputer of the present invention is a microcomputer capable of selecting a plurality of clocks having different frequencies as an operating clock of a CPU according to a processing speed, and a memory storing information designating a clock corresponding to an interrupt signal. A means for extracting the information from the memory and inputting it to a clock designation register in response to the input of the interrupt signal, and a clock selector for selecting a necessary clock based on the contents of the clock designation register, It is characterized in that the clock is automatically switched to a desired clock in response to the input of the interrupt signal without using an instruction for changing the clock in the interrupt processing.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention, in which a 14-bit program counter 1, a 16 Kbyte program memory (hereinafter referred to as ROM) 2 accessed by the program counter 1 and a ROM 2 are read. An instruction decoder 3 that decodes the generated instruction and generates various control signals; an oscillator circuit 4 that supplies a clock source for the entire microcomputer;
A frequency divider circuit 5 for dividing the output of the oscillation circuit to output four types of divided clocks and an interrupt operation based on the input of an interrupt signal a to an interrupt signal d when an internal or external interrupt occurs. An interrupt controller 6, a 2-bit CPU clock designation register 7 for designating a CPU operating clock, and one of four types of output clocks of the frequency divider circuit 5 based on the contents of the CPU clock designation register 7. , A clock selector 8 for supplying a CPU clock to each part of the CPU not shown in FIG. 1, an internal bus 9, a data memory (hereinafter referred to as ROM) 10 for storing data to be processed, and Program counter 1 when an interrupt occurs and when the interrupt returns
And a stack pointer 11 which serves as a data pointer when the contents of the CPU clock designation register 7 are saved and restored in the RAM 10.

When the output of the CPU clock specification register 7 is 00, the clock selector 8 is _x / 16,01 when it is _x / 8,10 when it is _x / 4,1
When set to 1, select _x / 2.

FIG. 3 is a diagram for explaining the contents of the interrupt vector table assigned to a partial area of ROM2. There are interrupt vector table a to interrupt vector table d corresponding to the interrupt signal a to interrupt signal d, each of which has a 2-byte structure, and includes 0010H to 0017H (H indicates hexadecimal notation). Address is assigned. With respect to the contents of each interrupt vector table, 2 bytes, that is, 14 bits out of 16 bits are assigned as a start address of each interrupt processing, and the remaining 2 bits are assigned as CPU clock designation bits. Therefore, four types of CPU clocks can be specified.

Next, a more detailed description will be given with reference to FIGS. 1 and 2. In the initial state of the microcomputer, that is, when the reset signal is input, the CPU clock designation register is cleared to 00 by the reset signal, and the slowest clock _x / 16 is selected and output as the CPU clock. For example, oscillation circuit output _x is 4MHz
Then _x / 16 = 250 KHz. If an interrupt occurs and the interrupt signal a is input to the interrupt controller 6 while the CPU is operating based on the _x / 16 clock, the CPU clock is specified by the signal from the interrupt controller 6. The current contents of the register 7 are saved in the ROM 10 addressed by the stack pointer 11 via the internal bus 9. At this time, the contents of the program counter 1 are also saved in the RAM 10. Further, the interrupt controller 6 generates an interrupt vector address corresponding to the interrupt signal a and transfers it to the program counter 1 via the internal bus 9. When the interrupt vector table a is addressed by the program counter 1, 14 bits of the interrupt a start address are transferred to the internal bus 9
The contents of the clock designating 2 bits CL11 and CL10 are transferred to the CPU clock designating register 7, the interrupt a start address is loaded into the program counter 1, and the clock designating 2 bits are loaded into the CPU clock designating register 7. , The register contents are output to the clock selector 8 in response to a signal from the interrupt controller 6. Assuming that the contents of the CPU clock designation register 7 are now 11, the clock selector 8 selects _x / 2 of the outputs of the frequency dividing circuit 5 and outputs it as the CPU clock. Thereafter, the CPU operates the interrupt processing routine corresponding to the interrupt signal a from the interrupt a start address based on the CPU clock selected by the clock selector 8. When the interrupt return instruction is executed at the end of the interrupt processing routine corresponding to the interrupt signal a, the contents of the old program counter saved from the RAM 10 are returned to the program counter 1 via the internal bus 9 and the old CPU The contents of the clock designation register are restored to the CPU clock register 7 via the internal bus 9, and the clock source signal before interruption is supplied as the CPU clock.

Even when the interrupt signals b to d are generated and the corresponding interrupt processing is executed, the clock designation bit previously written as ROM data in each interrupt vector table as in the case of the interrupt signal a. The 2-bit contents are transferred to the CPU clock designation register 7, and based on this, one of the outputs of the frequency dividing circuit 5 is selected by the clock selector 7 and supplied as the CPU clock. Therefore, each interrupt process operates at the operating speed based on the CPU clock specified in the interrupt vector table,
After executing the return instruction from the interrupt, it will return to the CPU clock before the interrupt and operate.

In this embodiment, the CP stored in the interrupt vector table
Although the U clock designation bit is 2 bits, it is needless to say that it is not limited to this. It may be determined according to the type of CPU clock and the word length of the program memory. Further, the frequency dividing circuit 5 is not always necessary, and it can be applied to a microcomputer in which two systems of oscillation circuits having different oscillation frequencies are built in and their outputs are selected.

Furthermore, an interrupt vector table for reset input may be incorporated to automatically set the operation speed after reset.

Although the clock source signal is selected according to the value stored in the ROM in the first embodiment, there are cases where it is desired to change the processing speed to the operating state at that time even with the same interrupt signal. A second embodiment capable of such an operation will be described below with reference to FIG.

Since the parts indicated by the same numbers as in FIG. 1 have the same functions, the description thereof will be omitted. ROM2 is the same as the first embodiment, but the second
In the area corresponding to the interrupt vector tables a to d in the figure, CP
All 16 bits are used as program address information without including U clock designation information. The interrupt-corresponding clock designation register 12 is composed of 2-bit registers # 1 to # 4 corresponding to the interrupt signals a to d, and is converted into the interrupt signals a to d by an instruction operation via the internal bus 9. You can write the information to specify the corresponding CPU clock.

When the interrupt signal 1 is input to the interrupt controller 6, the current contents of the CPU clock designation register 7 are saved in the RAM 10 via the internal bus 9 by the signal from the interrupt controller 6 as in the first embodiment. . When the interrupt controller 6 outputs a register selection signal indicating which of the interrupt signals a to d, the register selector 13 selects the corresponding register output of the interrupt-corresponding clock specification register 12 to specify the CPU clock. Output to register 7. When executing a return instruction from an interrupt, the RAM 10 is replaced by the old CPU as in the first embodiment.
The contents of the clock specification register are restored.

〔The invention's effect〕

As described above, the present invention, when an interrupt occurs, by automatically switching the operating clock of the CPU at the time of interrupt processing based on the information set in advance corresponding to the interrupt factor, The operation speed during each interrupt process can be set easily and in real time. Especially when an interrupt that requires high-speed processing occurs during operation at a slow operation speed, it can be changed in real time compared to changing the operation speed by an instruction, so the operation speed can be changed according to the target processing, There is also an effect of reducing the average power consumption of the entire microcomputer.

[Brief description of drawings]

1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a diagram showing an interrupt vector table in a program memory, and FIG. 3 is a block diagram of the second embodiment. 1 ... Program counter, 2 ... Program memory,
3 ... Instruction decoder, 4 ... Oscillation circuit, 5 ... Dividing circuit, 6 ... Interrupt controller, 7 ... CPU clock designation register, 8 ... Clock selector, 9 ... Internal bus,
10 …… RAM, 11 …… Stack pointer, 12 …… Interrupt-compatible clock specification register, 13 …… Register selector.

Claims (1)

[Claims] 1. A microcomputer capable of selecting a plurality of clocks having different frequencies as an operating clock of a CPU according to a processing speed, a memory storing information designating a clock corresponding to an interrupt signal, and An interrupt has a means for extracting the information from the memory and inputting it to the clock specifying register in response to the input of an interrupt signal, and a clock selector for selecting a necessary clock based on the contents of the clock specifying register. A microcomputer characterized in that it automatically switches to a desired clock in response to the input of the interrupt signal without using an instruction to change the clock in the processing.