JPH0786788B2 - Clock switching device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching device that doubles clocks supplied to a synchronous logic circuit and switches from one clock to the other without any trouble.

[Conventional technology]

FIG. 8 is a block diagram showing a conventional clock switching device disclosed in, for example, Japanese Patent Laid-Open No. 1-189220. In the figure, 1 is an input terminal for inputting a 1-system clock in a duplicated clock, 2 is an input terminal for similarly inputting a 2-system clock, and 3 is either the 1-system clock or the 2-system clock. The input terminal receives a selection signal for selecting one. Reference numeral 4 denotes a D flip-flop that latches the selection signal input from the input terminal 3,
Is an inverter for inverting the polarity of the output of the D flip-flop 4. 6 selects one of the 1-system clock and the 2-system clock input from the input terminals 1 and 2 based on the output of the inverter 5 and supplies it to the D flip-flop 4 as a trigger for giving a latch timing. This is the first selector that does. A second selector 7 selects one of the 1-system clock and the 2-system clock input from the input terminals 1 and 2 based on the output of the D flip-flop 4 and outputs it as an output clock. Reference numeral 8 is an output terminal from which the output clock from the second selector 7 is output.

Next, the operation will be described. Here, FIG. 9 is a timing chart for explaining the operation. In the first selector 6 and the second selector 7, the 1-system clock shown in FIG. 9 (a) is input from the input terminal 1, and the 2-system clock shown in FIG. 9 (b) is input from the input terminal 2. It has been entered. The D flip-flop 4 uses the output of the first selector 6 as a trigger to latch the selection signal input from the input terminal 3 and shown in FIG.
To the inverter 5. The inverter 5 inverts the polarity of the output of the D flip-flop 4 and outputs the first selector 6
Output to. The first selector 6 selects one of the 1-system clock from the input terminal 1 and the 2-system clock from the input terminal 2 by using the output of the inverter 5 as a select signal, and outputs the selected latch timing to the D flip-flop 4. Supply as a trigger to give. The second selector 7 selects either the 1-system clock from the input terminal 1 or the 2-system clock from the input terminal 2 using the output of the D flip-flop 4 directly as a selector signal, and outputs it from the output terminal 8 as the output clock. Output.

Here, since the select signals of the second selector 7 and the first selector 6 have a complementary relationship in which their polarities are mutually inverted, one of the 1-system clock and the 2-system clock is the second.
Is output from the selector 7 to the output terminal 8 as an output clock, and the other is sent from the first selector 6 to the D flip-flop as a trigger for giving a latch timing.
Therefore, the selection signal input from the input terminal 3 is latched by the D flip-flop 4 using the clock of the system not selected as the output clock as a trigger. Therefore, when the selection signal changes, the change is synchronized with the clock of the system that is not selected as the output clock, and this synchronized selection signal, that is, the system that is not selected at the change timing of the output of the D flip-flop 4. Will be selected as the output clock.

In FIG. 9, the 1-system clock is selected as the output clock before the switching timing, and changes in the selection signal shown in FIG. 9 (c) are synchronized with the 2-system clock and latched by the D flip-flop 4. . FIG. 9 (d) shows the output of the D flip-flop 4. When the output of the D flip-flop 4 changes, the second selector 7 is switched and the output clock to the output terminal 8 is switched from the 1-system clock to the 2-system clock as shown in FIG. 9 (e). Shows.

[Problems to be Solved by the Invention]

Since the conventional clock switching device is configured as described above, even if the input clock itself is duplicated, the clock switching function is not duplicated, and when a failure occurs in this clock switching function part Had a problem that the clock supply was cut off until it was repaired or replaced.

The present invention has been made in order to solve the above problems, and not only the input clock but also the clock switching function part is duplicated, and even if one of them fails, the other independently operates the clock. It is an object to obtain a clock switching device that can be supplied.

[Means for Solving the Problems]

A clock switching device according to the present invention operates in synchronization with a duplicated clock of each system or a signal synchronized therewith, and latches a switching signal of each system.
System sequential circuit and a first two-system sequential circuit, and
1-system switching logic that generates a switching logic circuit output for each system that determines the system of the clock to be output based on the outputs of the 1-system sequential circuit and the 1st 2-system sequential circuit, and the states of the respective system forced operation signals A circuit and a 2-system switching logic circuit, and a second 1-system sequential circuit that operates in synchronization with a clock of each system or a signal synchronized with the clock and latches the 1-system switching logic circuit output or the 2-system switching logic circuit output. A second 2-system sequential circuit, a 1-system delay circuit and a 2-system delay circuit for delaying the outputs of the second 1-system sequential circuit or the second 2-system sequential circuit, and a 1-system delay circuit or a 2-system delay circuit 1 system clock output buffer and 2 system clock output buffer that control the passage of the clock of the corresponding system based on the output of the system, and the clock of the system that has passed either of these system clock output buffers. There is obtained a clock transmission line which is output as the output clock.

[Work]

In the clock switching device according to the present invention, the clock switching function portion includes a first 1-system sequential circuit, a 1-system switching logic circuit,
A 1-system switching circuit including a second 1-system sequential circuit, a 1-system delay circuit, and a 1-system clock output buffer, a first 2-system sequential circuit, a 2-system switching logic circuit, a second 2-system sequential circuit, and a 2-system A delay circuit and a 2-system switching circuit with a 2-system clock output buffer are duplicated, and in the switching circuit of each system, the first sequential circuit that operates in synchronization with the clock of the own system or a signal in synchronization with the own system Of the switching logic circuit that determines the system of the output clock based on the output of the first sequential circuit of both systems and the state of the forced operation signal of its own system, and outputs the switching logic circuit output. The second sequential circuit is made to latch in synchronization with the clock of its own system or the signal synchronized with it, and the clock output buffer is controlled by the signal whose output is delayed by a predetermined time to output the clock of either system. By outputting from the clock transmission line as a clock, even if a failure in one of the switching circuit occurs, realizing a clock switching apparatus which can other switching circuit continues to supply the clock alone.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 1 and 2 are input terminals to which the 1-system clock or the 2-system clock in the duplicated clock is input. Further, 10 is an input terminal to which a 1-system switching signal is externally input, 11 is an input terminal to which a 2-system switching signal is similarly input, 12 is an input terminal to which a 1-system forced operation signal is externally input, 13 Is also an input terminal to which a 2-system forced operation signal is input.

Reference numeral 14 denotes a first 1 that operates in synchronization with the 1-system clock input from the input terminal 1 and latches the 1-system switching signal input from the input terminal 10 to output it as the 1st 1-system sequential circuit output.
Reference numeral 15 denotes a system sequential circuit, which operates in synchronization with a 2 system clock input from the input terminal 2 and latches a 2 system switching signal input from the input terminal 11 to output as a first 2 system sequential circuit output. It is a first 2-system sequential circuit. The first 1-system sequential circuit 14 and the first 2-system sequential circuit 15 are composed of, for example, D flip-flops.

Reference numeral 16 is the first 1-system sequential circuit 14 and the first 2-system sequential circuit
15 and the output of the first 1-system sequential circuit and the first 2
The system sequential circuit output and the 1-system forced operation signal input from the input terminal 12 are input, and the 1-system switching logic circuit output that determines the selection of the 1-system clock and the 2-system clock based on the states thereof is generated 1 This is a system switching logic circuit. Similarly, 17 is input from the input terminal 13 with the first 1-system sequential circuit output and the first 2-system sequential circuit output that are output from the first 1-system sequential circuit 14 and the first 2-system sequential circuit 15. It is a 2-system switching logic circuit that receives a 2-system forced operation signal and generates a 2-system switching logic circuit output that determines the selection of the 1-system clock and the 2-system clock based on their states.

Reference numeral 18 is a second 1-system sequence that operates in synchronization with the 1-system clock to latch the 1-system switching logic circuit output from the 1-system switching logic circuit 16 and output it as a second 1-system sequential circuit output. A circuit 19 similarly operates in synchronization with the 2 system clock to latch the 2 system switching logic circuit output from the 2 system switching logic circuit 17, and outputs it as the second 2 system sequential circuit output. 2 is a 2-system sequential circuit. This second 1-system sequential circuit 18
The second 2-system sequential circuit 19 is also composed of, for example, a D flip-flop.

Reference numeral 20 is a 1-system delay circuit that delays the second 1-system sequential circuit output from the second 1-system sequential circuit 18 and outputs it as a 1-system delay circuit output, and 21 is a second 2 system Sequential circuit
This is a 2-system delay that delays the second 2-system sequential circuit output from 19 and outputs it as a 2-system delay circuit output. twenty two
Is a 1-system clock output buffer that controls passage of the 1-system clock input from the input terminal 1 based on the 1-system delay circuit output from the 1-system delay circuit 20, and 23 is the same as
This is a 2-system clock output buffer that controls passage of the 2-system clock input from the input terminal 2 based on the 2-system delay circuit output from the 2-system delay circuit 21. As the 1-system clock output buffer 22 and the 2-system clock output buffer 23, for example, tri-state type buffers are used.

24 is the first 1-system sequential circuit 14, 1-system switching logic circuit 16,
A 1-system switching circuit formed by a second 1-system sequential circuit 18, a 1-system delay circuit 20, and a 1-system clock output buffer 22, wherein 25 is the first 2-system sequential circuit 15 and 2-system switching logic circuit. A second system switching circuit formed by 17, a second system sequential circuit 19, a second system delay circuit 21, and a second system clock output buffer 23. Reference numeral 26 denotes clock transmission in which the 1-system clock that has passed through the 1-system clock output buffer 22 of the 1-system switching circuit 24 or the 2-system clock that has passed through the 2-system clock output buffer 23 of the 2-system switching circuit 25 is output as an output clock. And 27 is a pull-up resistor that pulls up the clock transmission line 26.

Next, the operation will be described. Here, FIG. 2 and FIG.
The figure is a timing chart for explaining the operation, FIG. 2 shows the switching operation from the 2 system clock to the 1 system clock, and FIG. 3 shows the switching operation from the 1 system clock to the 2 system clock. There is. Further, it is assumed that "H" is significant for the signal switching, and first, the switching operation from the 2 system clock to the 1 system clock will be described with reference to FIG.

The first 1-system sequential circuit 14 and the second 1-system sequential circuit 18 operate in synchronization with the 1-system clock shown in FIG.
The 2-system sequential circuit 15 and the second 2-system sequential circuit 19 operate in synchronization with the 2-system clock shown in FIG. Therefore, the first 1-system sequential circuit 14 latches the 1-system switching signal shown in FIG. 2 (b) which is input from the input terminal 10, and outputs the 1-system switching signal shown in FIG. 2 (c). It is output as a sequential circuit output to the 1-system switching logic circuit 16 and the 2-system switching logic circuit 17.
Similarly, the first 2-system sequential circuit 15 also latches the 2-system switching signal shown in FIG. 2 (e) input from the input terminal 11, and transfers it to the first system shown in FIG. 2 (f). It is output to the 1-system switching logic circuit 16 and the 2-system switching logic circuit 17 as a 2-system sequential circuit output.

The 1-system switching logic circuit 16 determines the 1-system clock output buffer 22 based on the outputs of the first 1-system sequential circuit output and the 1st 2-system sequential circuit output and the 1-system forced operation signal input from the input terminal 12. It outputs the 1-system switching logic circuit for determining the opening and closing of the. Similarly, the 2-system switching logic circuit 17 also outputs the 2-system clock output buffer 23 according to the outputs of the first 1-system sequential circuit output and the first 2-system sequential circuit output and the 2-system forced operation signal input from the input terminal 13. It outputs the output of the 2-system switching circuit for determining the opening and closing of.

The function of the 1-system switching logic circuit 16 is shown in FIG. 4, and the function of the 2-system switching logic circuit 17 is shown in FIG. 1-system switching logic circuit
As shown in FIG. 4, reference numeral 16 indicates that when the first 1-system sequential circuit output is "H" and the first 2-system sequential circuit output is "L", or when the 1-system forced operation signal is "H". Sometimes the 1-system switching logic circuit output is set to "H", the first 1-system sequential circuit output is "L", the 1st 2-system sequential circuit output is "H", and the 1-system forced operation signal is "L". In the case of ", the 1-system switching logic circuit output is set to" L ", and in the other states, the 1-system switching logic circuit output is held in the previous state.

Similarly, as shown in FIG. 5, the 2-system switching logic circuit 17 operates when the first system sequential circuit output is "H" and the first 1-system sequential circuit output is "L", or When the forced operation signal is "H", the output of the 2-system switching logic circuit is set to "H". Also, the first
2 system sequential circuit output is “L”, the first 1 system sequential circuit output is “H” and the 1 system forced operation signal is “L”, the 2 system switching logic circuit output is set to “L” and other In the state, the 2-system switching logic circuit output is held in the previous state.

In FIG. 2, both the 1-system forced operation signal and the 2-system forced operation signal are treated as “L”, that is, not in the forced operation mode. In the 1-system, the first 1-system sequential circuit output is “H”, When the output of the 2-system sequential circuit of "L" becomes 1
The output of the system switching logic circuit becomes "H" as shown in FIG. 2 (g), and the output of the system switching logic circuit becomes "L" as shown in FIG. 2 (j).

The second 1-system sequential circuit 18 latches the 1-system switching logic circuit output from the 1-system switching logic circuit 16 in synchronization with the 1-system clock,
It is output to the 1-system delay circuit 20 as the output of the second 1-system sequential circuit shown in FIG. 2 (h). The 1-system delay circuit 20 is the second 1
As shown in Fig. 2 (i), the system sequential circuit output is delayed by 1/4 phase with respect to the 1-system clock, and the opening / closing timing of the 1-system clock output buffer is at the center of "H" of the 1-system clock. 1-system delay circuit output is generated. When the 1-system clock output buffer 22 outputs "H" for the 1-system delay circuit,
As shown in FIG. 2 (m), the output of the 1-system clock input from the input terminal 1 to the clock transmission line 26 is started.

Similarly, in the second 2-system sequential circuit 19, the 2-system switching logic circuit output is latched in synchronization with the 2-system clock, and the 2-system delay circuit is output as the second 2-system sequential circuit output shown in FIG. 2 (k). Send to 21. The 2nd system delay circuit 21 outputs the received second 2nd system sequential circuit output to the 2nd system clock so that the opening / closing timing of the 2nd system clock output buffer 23 is at the center of "H" of the 2nd system clock. A 4-phase delay is applied to generate the delay circuit output shown in FIG. 2 system clock output buffer 23
When the output of the system delay circuit becomes "L", the output of the system 2 clock input from the input terminal 2 to the clock transmission line 26 is stopped as shown in FIG. 2 (m).

Next, the switching operation from the 1-system clock to the 2-system clock will be described with reference to FIG. In this case, the 1-system switching signal input from the input terminal 1 is "H" → as shown in Fig. 3 (b).
"L", the 2-system switching signal input from the input terminal 2 changes from "L" to "H" as shown in FIG. 3 (e), and the operation thereafter is the same as in the case of FIG. A system 1 clock output buffer 22 and a system 2 clock output buffer 23 are provided on the transmission line 26.
A state occurs in which neither of them outputs the output clock. In such a case, "H" is maintained by the pull-up resistor 27 that pulls up the clock transmission line 26.
2 and 3, if the phase difference between the 1-system clock and the 2-system clock is within 1/4 phase, clock switching can be performed without generating spikes on the clock transmission line 26.

Next, the processing when a failure occurs in either the 1-system switching circuit 24 or the 2-system switching circuit 25 will be described. When a failure occurs in the 1-system switching circuit 24, it is input from the input terminal 2
Set the system forced operation signal to "H". As a result, the output of the 2-system logic circuit output from the 2-system switching logic circuit 17 becomes "H", so that the 2-system clock output buffer 23 is forcibly opened and the 2-system clock is output to the clock transmission line 26. .
In this state, the system 1 switching circuit 24 is separated from the clock transmission line 26 and the system 2 switching circuit 25 for repair or replacement.
1-system switching circuit 24, 2-system switching circuit 25 and clock transmission line
The 26 can be easily separated by connecting them with a connector. When the 2-system switching circuit 25 fails, the 2-system switching circuit can be repaired or replaced by the same operation.

In the above embodiment, the output of the second 1-system sequential circuit changes at the center of "H" of the 1-system clock, and the second 2-system sequential circuit output also changes at the center of "H" of the 2 system clock. Although the setting is made so as to be set, it may be set so as to change in the center of “L”. In this case, the delay amounts of the 1-system delay circuit 20 and the 2-system delay circuit 21 are compared with the 1-system clock and the 2-system clock.
The number of phases is 3/4, and the clock transmission path 26 is pulled down in order to stop the output of the 1-system clock output buffer 22 and the 2-system clock output buffer 23 at the same time.

In the above embodiment, the 1-system clock output buffer 22,
Although a tri-state type buffer is used as the 2 system clock output buffer 23, an open collector type buffer can also be used.

Further, in the embodiment, the first 1-system sequential circuit 14 and the second 1-system sequential circuit 18 operate by using the 1-system clock as a trigger.
Although the two-system sequential circuit 15 and the second two-system sequential circuit 19 of FIG. 6 operate by using the two-system clock as a trigger, as shown in FIG. 6, the trigger of the first one-system sequential circuit 14 is Input terminal
A pulse synchronized with the 1-system clock input from 28,
The trigger of the first two-system sequential circuit 15 may be a pulse synchronized with the two-system clock input from the input terminal 29, and it is even better if the phases of both pulses are substantially the same. The trigger of the second 1-system sequential circuit 18 is also a pulse synchronized with the 1-system clock input from the input terminal 30, and the second 2
The trigger of the system sequential circuit 19 may be a pulse synchronized with the two-system clock input from the input terminal 31, and it is more preferable that the phases of both pulses are substantially the same.

FIG. 7 is a timing chart for explaining the operation of the embodiment shown in FIG. 7 (a) and 7 (d) are a 1-system clock and a 2-system clock, and FIG. 7 (b) is an input terminal.
FIG. 7 (c) shows a trigger of the second 1-system sequential circuit 18 input from the input terminal 30, and a trigger of the first 1-system sequential circuit 14 input from 28. Also, FIG. 7 (e) shows an input terminal.
This is a trigger for the first 2-system sequential circuit 15 input from 29, and FIG. 7 (f) shows the second 2 sequence input from the input terminal 31.
This is a trigger for the system sequential circuit 19.

In the embodiment shown in FIG. 1, in the 1-system switching logic circuit 16 and the 2-system switching logic circuit 17, even if the 1-system clock from the input terminal 1 and the 2-system clock from the input terminal 2 are in phase with each other. 1
The output of the switching logic circuits of both systems must be output within one bit, but in the embodiment shown in FIGS. 6 and 7,
1 system switching logic circuit output and 2 system switching logic circuit output are 2
It is only necessary to output within 1 bit, and it is possible to allow the processing speed of the 1-system switching logic circuit 16 and the 2-system switching logic circuit 17 to have a margin.

Further, in the embodiment shown in FIG. 1, all the first and second sequential circuits of both systems are composed of D flip-flops. However, as in the examples shown in FIG. 6 and FIG. Sequential circuit and second
If there is no overlap in the trigger pulses of the sequential circuit of, they can also be configured by latches.

Further, although the case where the clocks are switched has been described in the above embodiment, it may be applied to the switching of normal data and timing signals.

Further, in the embodiment shown in FIGS. 1 and 6, the first
When the signal that triggers the first and second sequential circuits is cut off, the switching operation cannot be performed, but the configuration is as shown in FIG.
Each sequential circuit is composed of latches, and first and second of both systems
If the signal that triggers the sequential circuit is disconnected, the latch operation is stopped by adding a circuit that forcibly enables the latch, and the latch input signal becomes the output signal directly. Timing cannot be guaranteed, but switching operation is possible.

〔The invention's effect〕

As described above, according to the present invention, the device is provided with the first 1-system sequential circuit, the 1-system switching logic circuit, the second 1-system sequential circuit, the 1-system delay circuit, and the 1-system clock output buffer.
A system switching circuit and a two-system switching circuit including a first two-system sequential circuit, a two-system switching logic circuit, a second two-system sequential circuit, a two-system delay circuit, and a two-system clock output buffer are duplicated. With this configuration, even if a failure occurs in one of the switching circuits, the other normal switching circuit can continue to supply the clock independently, and the switching circuits of both systems are operating normally. Even if the clock is switched at any time, if the phase difference between the duplicated system clocks is within the range of 1/4 phase, the clock can be switched without generating spikes in the clock transmission line, and reliability can be improved. There is an effect that a high clock switching device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock switching device according to an embodiment of the present invention, FIGS. 2 and 3 are timing diagrams for explaining the operation thereof, and FIGS. 4 and 5 are 1-system switching logic circuits. And an explanatory view showing the function of the 2-system switching logic circuit, FIG. 6 is a block diagram showing another embodiment of the present invention,
FIG. 7 is a timing chart for explaining the operation, and FIG.
FIG. 9 is a block diagram showing a conventional clock switching device, and FIG. 9 is a timing diagram for explaining its operation. 14 is the first 1-system sequential circuit, 15 is the first 2-system sequential circuit, 16
Is a 1-system switching logic circuit, 17 is a 2-system switching logic circuit, and 18 is a second
1 system sequential circuit, 19 2nd 2 system sequential circuit, 20 1 system delay circuit, 21 2 system delay circuit, 22 1 system clock output buffer, 23 2 system clock output buffer, 26 clock transmission Road. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A clock which is duplicated with a 1-system clock and a 2-system clock, operates in synchronization with the 1-system clock or a signal synchronized with the 1-system clock, and latches an input 1-system switching signal. Then, the first 1-system sequential circuit that outputs as the first 1-system sequential circuit output operates in synchronization with the 2nd system clock or a signal synchronized with the 2nd system clock, and receives the 2nd system switching signal. A first 2-system sequential circuit that latches and outputs as a first 2-system sequential circuit output, the first 1-system sequential circuit output, the first 2-system sequential circuit output, and the input 1-system forced operation A first-system switching logic circuit that generates a first-system switching logic circuit output that determines selection of the first-system clock and the second-system clock based on a state of a signal;
Of the 1-system sequential circuit output, the 1st 2-system sequential circuit output, and the state of the input 2-system forced operation signal
A 2-system switching logic circuit that generates a 2-system switching logic circuit output that determines the selection of a system clock and a 2-system clock, and operates in synchronization with the 1-system clock or a signal synchronized with the 1-system clock, and switches the 1-system switching Second by latching the output of the logic circuit
And a second 1-system sequential circuit that outputs as a 1-system sequential circuit output of the first system, and operates in synchronization with the second system clock or a signal synchronized with the second system clock and latches the second system switching logic circuit output. A second 2-system sequential circuit for outputting as a 2-system sequential circuit output 2; a 1-system delay circuit for delaying the second 1-system sequential circuit output and outputting as a 1-system delay circuit output; A 2-system delay circuit that delays the 2-system sequential circuit output and outputs it as a 2-system delay circuit output, and 1 that controls passage of the 1-system clock by the 1-system delay circuit output
System clock output buffer, 2 system clock output buffer that controls passage of the 2 system clock by the 2 system delay circuit output, 1 system clock that has passed the 1 system clock output buffer, or 2 system clock output buffer And a clock transmission path through which the above-mentioned two-system clock that has passed through is output as an output clock.