JPH0787233B2 - Electronic component having a gold conductive layer - Google Patents
Electronic component having a gold conductive layerInfo
- Publication number
- JPH0787233B2 JPH0787233B2 JP61204719A JP20471986A JPH0787233B2 JP H0787233 B2 JPH0787233 B2 JP H0787233B2 JP 61204719 A JP61204719 A JP 61204719A JP 20471986 A JP20471986 A JP 20471986A JP H0787233 B2 JPH0787233 B2 JP H0787233B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- gold conductive
- metal layer
- solder
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Other Surface Treatments For Metallic Materials (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は金属面上に金の導電層を有する電子部品に関
し、より詳細には半導体集積回路素子を収納する半導体
素子収納用パッケージや多層配線基板等の電子部品にお
ける金の導電層の下地金属層の改良に関するものであ
る。Description: TECHNICAL FIELD The present invention relates to an electronic component having a gold conductive layer on a metal surface, and more particularly to a semiconductor element storage package for storing a semiconductor integrated circuit element and a multilayer wiring. The present invention relates to improvement of a base metal layer of a gold conductive layer in an electronic component such as a substrate.
金は(i)高導電性、(ii)耐酸化性が良いこと、(ii
i)耐変色性(耐腿色性)が高いこと、(iv)半導体チ
ップのシリコン(Si)と容易に合金化しAu−Si共晶合金
を作って堅固な接合強度を発揮すること等の優れた物理
的性質により各種の電子部品に広く利用されている。例
えば半導体集積回路素子を収納するための半導体素子収
納用パッケージにおいては、半導体集積回路素子を取着
するダイアタッチ部、半導体集積回路素子の電極と外部
リード端子とを接続するためのワイヤを取着するワイヤ
ボンディング部あるいは半導体集積回路素子を外部電気
回路に接続するための外部リード端子等がある。これ等
は絶縁基体にタングステン(W)、モリブデン(Mo)、
マンガン(Mn)等の高融点金属をメタライズした金属面
上に、あるいは該メタライズ金属面上にロウ材を介し取
着されたコバール(Fe−Ni−Co),42Alloy等の金属板か
ら成る外部リード端子の表面にめっき、蒸着、スパッタ
リング等により被着形成されている。Gold has (i) high conductivity, (ii) good oxidation resistance, (ii)
i) High resistance to discoloration (thigh color resistance), (iv) Excellent in that it can be easily alloyed with silicon (Si) of a semiconductor chip to form an Au-Si eutectic alloy and exhibit a strong joint strength. It is widely used in various electronic parts due to its physical properties. For example, in a semiconductor element housing package for housing a semiconductor integrated circuit element, a die attach portion for mounting the semiconductor integrated circuit element, a wire for connecting an electrode of the semiconductor integrated circuit element and an external lead terminal are mounted. There is a wire bonding portion or an external lead terminal for connecting the semiconductor integrated circuit element to an external electric circuit. These are tungsten (W), molybdenum (Mo),
External lead made of a metal plate such as Kovar (Fe-Ni-Co) or 42Alloy attached to a metal surface metallized with a refractory metal such as manganese (Mn) or a brazing material on the metallized metal surface. It is formed on the surface of the terminal by plating, vapor deposition, sputtering or the like.
しかし乍ら、例えば外部リード端子表面に被着された金
の層は半導体素子収納用パッケージを外部電気回路に半
田等を介しロウ付け接合する際、該金の層が溶融状態の
半田(Sn−Pb合金)中に極めて速やかに溶解してしま
い、その結果、半田等のロウ材が該半田等と反応性(濡
れ性)の悪い42Alloy、コバール金属から成る外部リー
ド端子に直接接触してしまい、半導体素子収納用パッケ
ージを外部電気回路に強固に接合することが困難であっ
た。However, for example, when a gold layer deposited on the surface of an external lead terminal is brazed and bonded to a package for storing a semiconductor element to an external electric circuit via solder or the like, the gold layer is a molten solder (Sn- Pb alloy) is very quickly dissolved, and as a result, the brazing material such as solder directly contacts the external lead terminal made of 42Alloy or Kovar metal, which has poor reactivity (wettability) with the solder, It was difficult to firmly bond the semiconductor element housing package to the external electric circuit.
そこで、かかる欠点を解消するために、溶融状態の半田
にほとんど溶解せず、半田との反応性(濡れ性)が良好
なニッケル(Ni)の金属層を金の導電層の下地として被
覆したものが提案されている。Therefore, in order to eliminate such drawbacks, a metal layer of nickel (Ni), which hardly dissolves in molten solder and has good reactivity (wettability) with solder, is coated as a base of the gold conductive layer. Is proposed.
しかし乍ら、上記金の導電層の下地として被覆されたニ
ッケルの金属層は半導体素子収納用パッケージに半導体
集積回路素子を取着する際、あるいはパッケージを気密
封止する際等の加熱により、金の導電層を容易に拡散し
て該金の導電層の表面に析出し、これが酸化されて半田
との反応性(濡れ性)が極めて悪いニッケルの酸化物や
水酸化物を生成し、その結果、半導体素子収納用パッケ
ージを外部電気回路へ取着するのが困難となり、更に金
の導電層表面を変色させると同時に導電性を劣化させる
等の問題を有してしいた。However, the nickel metal layer coated as an underlayer of the gold conductive layer is formed by heating when mounting a semiconductor integrated circuit device in a package for housing a semiconductor device, or when hermetically sealing the package. Easily diffuses into the surface of the conductive layer of gold and is oxidized to form nickel oxide or hydroxide, which has extremely poor reactivity (wettability) with solder. However, it is difficult to attach the semiconductor element housing package to the external electric circuit, and further, there is a problem that the surface of the gold conductive layer is discolored and at the same time the conductivity is deteriorated.
そこで、斯かる欠点を解消するために、金の導電層の下
地としてニッケルより金への熱拡散が極めて遅いコバル
トの金属層を設けることを本出願人は先に提案した。Therefore, in order to eliminate such a drawback, the applicant previously proposed to provide a metal layer of cobalt, which is extremely slow in heat diffusion from nickel to gold, as a base of the gold conductive layer.
しかし乍ら、金の導電層の下地としてコバルトより成る
金属層を形成した場合、金の導電層表面に半田と反応性
(濡れ性)が悪いコバルトの酸化物、水酸化物等の生成
は少ないものの半導体集積回路素子の特性のチェックす
るバーンインテスト(半導体集積回路素子に高温の熱履
歴を加えて特性変化を調べるテスト)等を行った場合、
半田に含有される錫(Sn)が金の導電層を通して下地の
コバルトから成る金属層に一方的に拡散してしまい、そ
の結果、半導体素子収納用パッケージを外部電気回路等
に取着する際等において外部リード端子に外部より機械
的な応力が印加されると該応力によって外部リード端子
と半田とが容易に剥離し、電気的接続の信頼性が低下す
るという欠点を有することが判明した。However, when a metal layer made of cobalt is formed as an underlayer of the gold conductive layer, formation of cobalt oxide, hydroxide, etc., which has poor reactivity (wettability) with solder on the gold conductive layer surface is small. If a burn-in test (a test to check the characteristic change by adding high temperature heat history to the semiconductor integrated circuit element) is performed to check the characteristics of the semiconductor integrated circuit element,
Tin (Sn) contained in the solder unilaterally diffuses through the gold conductive layer to the underlying metal layer made of cobalt, and as a result, when mounting the semiconductor element storage package to an external electric circuit, etc. It was found that the external lead terminal and the solder are easily separated from each other by the mechanical stress applied to the external lead terminal from the outside, and the reliability of the electrical connection is lowered.
本発明は前記欠点に鑑み案出されたもので、その目的は
半導体集積回路素子をチェックするためのバーンインテ
スト等を行ったとしても半田の錫がコバルトから成る金
属層に拡散することはなく外部応力が印加されても絶縁
基体に設けたメタライズ金属層や外部リード端子と半田
との接合に剥離を生じることがなく、しかも半導体集積
回路素子を取着する際、あるいは取着後の気密封止の際
等に熱が印加され、かつ高温多湿等の酸化条件下に曝さ
れてもロウ材との反応性(濡れ性)が劣化することのな
い金の導電層を有する電子部品を提供することにある。The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to prevent solder tin from diffusing into a metal layer made of cobalt even if a burn-in test for checking a semiconductor integrated circuit element is performed. Even if stress is applied, peeling does not occur in the joint between the metallized metal layer provided on the insulating substrate and the external lead terminal and the solder, and furthermore, when the semiconductor integrated circuit element is mounted or after it is hermetically sealed. To provide an electronic component having a gold conductive layer that does not deteriorate in reactivity (wettability) with a brazing material even when heat is applied during heating and the like and is exposed to oxidizing conditions such as high temperature and high humidity. It is in.
本発明は金属面上に金の導電層を有する電子部品におい
て、該金の導電層の下地として、コバルト98.5〜99.999
重量%、硫黄0.001〜1.5重量%の合金から成る金属層を
設けことを特徴とするものである。The present invention relates to an electronic component having a gold conductive layer on a metal surface, and cobalt 98.5 to 99.999 is used as a base of the gold conductive layer.
The present invention is characterized in that a metal layer made of an alloy containing 0.001 to 1.5% by weight of sulfur and 0.001 to 1.5% by weight of sulfur is provided.
本発明の硫黄の含有量が0.001重量%未満であると、半
田に含有される錫が下地金属層中のコバルトへ拡散する
のを有効に阻止し得ず、半田剥がれが発生する。また、
その含有量が1.5重量%を越えると下地金属層の耐食性
が劣化するので好ましくない。When the sulfur content of the present invention is less than 0.001% by weight, tin contained in the solder cannot be effectively prevented from diffusing into cobalt in the underlying metal layer, and solder peeling occurs. Also,
If its content exceeds 1.5% by weight, the corrosion resistance of the underlying metal layer deteriorates, which is not preferable.
以下に本発明を添付図面に示す実施例に基づき詳細に説
明する。Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings.
第1図は本発明の電子部品をリード付半導体素子収納用
パッケージの例に採って示した一部破断平面図であり、
第2図は第1図の要部拡大断面図である。FIG. 1 is a partially cutaway plan view showing an electronic component of the present invention as an example of a package for housing a semiconductor element with leads,
FIG. 2 is an enlarged cross-sectional view of the main part of FIG.
図において、1はセラミック、ガラス等の電気絶縁材料
から成る絶縁基体であり、2は半導体集積回路素子10の
電極と外部リード端子12との電気的導通をはかるための
ワイヤ11が取着されるワイヤボンディング用メタライズ
金属層である。In the figure, 1 is an insulating substrate made of an electrically insulating material such as ceramic or glass, and 2 is attached a wire 11 for electrically connecting an electrode of the semiconductor integrated circuit element 10 and an external lead terminal 12 to each other. It is a metallized metal layer for wire bonding.
前記メタライズ金属層2はその一部が絶縁基体1の側面
にまで延長されており、絶縁基体1の側面においてロウ
材等を介して外部リード端子12が接合されている。3は
半導体集積回路素子10をマウントするためのダイアタッ
チ部のメタライズ金属層である。これらのメタライズ金
属層2,3及び外部リード端子12の直上にはコバルトと硫
黄の合金より成る金属層4,5,6が、更にその上には金の
導電層7,8,9が夫々層設されている。金の導電層8にはA
u−Si等のロウ材を介して半導体集積回路素子10が取着
されており、該半導体集積回路素子10の各電極はワイヤ
11を介して金の導電層7と電気的に接合され、外部リー
ド端子12に導出される。A part of the metallized metal layer 2 extends to the side surface of the insulating base 1, and the external lead terminal 12 is joined to the side surface of the insulating base 1 via a brazing material or the like. 3 is a metallized metal layer of a die attach portion for mounting the semiconductor integrated circuit element 10. Immediately above the metallized metal layers 2 and 3 and the external lead terminals 12, metal layers 4,5 and 6 made of an alloy of cobalt and sulfur, and on top of them, gold conductive layers 7, 8 and 9, respectively. It is set up. A for the gold conductive layer 8
The semiconductor integrated circuit element 10 is attached via a brazing material such as u-Si, and each electrode of the semiconductor integrated circuit element 10 is a wire.
It is electrically joined to the gold conductive layer 7 via 11 and is led to the external lead terminal 12.
前記メタライズ金属層2,3は絶縁基体1にタングステ
ン、モリブデンもしくはマンガン等の粉末に適当な有機
溶剤、溶媒を添加混合して得た金属ペーストを従来周知
の厚膜手法により印刷塗布し、しかる後、高温で焼成し
てメタライズすることにより形成される。The metallized metal layers 2 and 3 are formed by printing and coating a metal paste obtained by adding a suitable organic solvent to a powder of tungsten, molybdenum, manganese, or the like, and a solvent to the insulating substrate 1 by a well-known thick film method, and thereafter. It is formed by baking at high temperature and metallizing.
また外部リード端子12はコバール(Fe−Ni−Co)、42Al
loy等の金属から成り、コバルト−硫黄合金及び金の各
金属層4,5,6,7,8,9はめっき、真空蒸着、スパッタリン
グ等の手法により形成されている。The external lead terminals 12 are Kovar (Fe-Ni-Co), 42Al.
Each metal layer 4,5,6,7,8,9 made of a metal such as loy and made of a cobalt-sulfur alloy and gold is formed by a technique such as plating, vacuum deposition, and sputtering.
また、前記絶縁基体1の上面にはセラミック、ガラス等
の電気絶縁材料から成る蓋体13がガラス、樹脂等の封止
部材を介して取着されており、これにより半導体素子収
納用パッケージ内部の空所は外気から完全に気密に封止
され、最終製品である半導体装置となる。Further, a lid 13 made of an electrically insulating material such as ceramic or glass is attached to the upper surface of the insulating substrate 1 via a sealing member such as glass or resin. The void is completely airtightly sealed from the outside air, and becomes a semiconductor device as a final product.
かくして、本発明によれば、外部リード端子の表面で、
金の導電層の下地に金と固溶し難く、かつ錫が拡散する
ことがないコバルトと硫黄の合金から成る金属層を設け
たことにより、半田と外部リード端子との密着強度を大
として、外部リード端子と半田との間に外力印加による
剥離を発生することを皆無となし、しかも半導体集積回
路素子を取着する際、あるいは取着後の気密封止の際等
に熱が印加され、かつ高温多湿等の酸化条件下に曝され
てもロウ材との反応性(濡れ性)が悪い酸化物や水酸化
物を生成することもなく、半導体素子収納用パッケージ
を外部電気回路に強固に取着することができる。Thus, according to the invention, on the surface of the external lead terminal,
By providing a metal layer made of an alloy of cobalt and sulfur, which is hard to form a solid solution with gold and does not diffuse tin, on the base of the gold conductive layer, the adhesion strength between the solder and the external lead terminal is increased, There is no occurrence of peeling between the external lead terminals and the solder due to the application of an external force, and heat is applied when the semiconductor integrated circuit element is attached, or when hermetically sealing after attachment, In addition, even if exposed to oxidizing conditions such as high temperature and high humidity, it does not generate oxides or hydroxides that have poor reactivity (wettability) with the brazing material, making the package for storing semiconductor elements strong in external electrical circuits. Can be attached.
なお、本発明は上述の実施例に限定されるものではな
く、例えば半導体集積回路素子収納用リードレスパッケ
ージ(チップキャリア)や多層配線基板等の金の導電層
を有する電子部分にも適用可能なことは言うまでもな
い。The present invention is not limited to the above-described embodiments, and is applicable to, for example, a leadless package for storing a semiconductor integrated circuit element (chip carrier), an electronic portion having a gold conductive layer such as a multilayer wiring board, and the like. Needless to say.
(I)評価試料 評価試料として幅2mm、長さ20mm、厚さ0.25mmの42Alloy
から成る金属板の外表面に第1表に示す如く金の導電層
の下地としてコバルトと硫黄の合金から成る金属層を介
在させたもの(本発明品)及びコバルトの金属層を介在
させたものを各100本準備した。(I) Evaluation sample 42Alloy having a width of 2 mm, a length of 20 mm and a thickness of 0.25 mm as an evaluation sample
As shown in Table 1, on the outer surface of a metal plate made of a metal sheet having a metal layer made of an alloy of cobalt and sulfur as an underlayer (the present invention) and a metal layer of cobalt being made to intervene. 100 pieces of each were prepared.
(II)半田剥れ性テスト 上記評価試料を245℃±5℃に制御された溶融状態の錫6
0重量%、鉛40重量%の共晶半田中に浸漬して半田付け
した後、半導体集積回路素子の特性をチェックするため
のバーンインテストと同じ条件、即ち150℃に制御され
たオーブン中で250時間のエージング処理を行い、その
後、それぞれの試料を直角に折り曲げ、半田が剥離しな
い本数を数え、半田剥がれ良品率を求めた。(II) Solder peelability test The above-mentioned evaluation sample was used for molten tin 6 controlled at 245 ° C ± 5 ° C.
After immersing and soldering in eutectic solder of 0 wt% and 40 wt% lead, the same conditions as the burn-in test to check the characteristics of the semiconductor integrated circuit device, that is, 250 in an oven controlled at 150 ° C. After aging treatment for time, each sample was bent at a right angle, the number of solders that did not peel off was counted, and the solder peeling non-defective rate was calculated.
その結果を第1表に示す。The results are shown in Table 1.
第1表からも判るように従来品の金の導電層の下地とし
て硫黄を含有しないコバルトの金属層を形成した試料番
号1においては半田剥がれ良品率が僅が18%にしか過ぎ
ず、電子部品に適用する場合、大きな問題となる。ま
た、硫黄の含有量が1.5重量%を越えると下地金属層が
酸化により変色するため望ましくない。 As can be seen from Table 1, in the sample No. 1 in which the sulfur-free cobalt metal layer was formed as the base of the conventional gold conductive layer, the rate of non-soldering was only 18%, and the electronic component When applied to, it becomes a big problem. If the sulfur content exceeds 1.5% by weight, the underlying metal layer is discolored due to oxidation, which is not desirable.
これらに対し、本発明によれば0.001重量%以上1.5重量
%以下の硫黄を含有したコバルトと硫黄の合金から成る
金属層を形成したものでは、いずれも半田剥がれ良品率
が100%となることが判明した。On the other hand, according to the present invention, in the case where the metal layer made of the alloy of cobalt and sulfur containing 0.001% by weight or more and 1.5% by weight or less of sulfur is formed, the yield rate of solder peeling can be 100%. found.
以上の如く、本発明によれば、メタライズ金属層及び外
部リード端子表面にコバルトと硫黄の合金から成る金属
層を設けたことにより、半導体集積回路素子の特性をチ
ェックするバーンインテストを行ったとしても半田に含
有される錫がコバルトへ拡散するのを防止し、外部より
応力が加えられても絶縁基体に設けたメタライズ金属層
や外部リード端子の表面より半田が剥離することがな
く、しかも半導体集積回路素子を取着する際、あるいは
取着後の気密封止の際等に熱が印加され、かつ高温多湿
等の酸化条件下に曝されてもロウ材との反応性(濡れ
性)が劣化することもない。As described above, according to the present invention, even if the burn-in test for checking the characteristics of the semiconductor integrated circuit element is performed by providing the metallized metal layer and the metal layer made of an alloy of cobalt and sulfur on the surface of the external lead terminal. It prevents the tin contained in the solder from diffusing into cobalt, so that even if external stress is applied, the solder does not peel off from the surface of the metallized metal layer provided on the insulating substrate or the external lead terminals. Reactivity (wettability) with the brazing material is deteriorated even when heat is applied when the circuit element is attached, or after airtight sealing after attachment, and when exposed to oxidizing conditions such as high temperature and high humidity. There is nothing to do.
第1図は本発明の電子部品をリード付半導体素子収納用
パッケージを例に採って示した一部破断平面図であり、
第2図は第1図の要部拡大断面図である。 1……絶縁基体 2,3……メタライズ金属層 4,5,6……コバルト−硫黄合金金属層 7,8,9……金の導電層 10……半導体集積回路素子 11……ワイヤ 12……外部リード端子 13……蓋体FIG. 1 is a partially cutaway plan view showing an electronic component of the present invention as an example of a package for housing a semiconductor element with leads,
FIG. 2 is an enlarged cross-sectional view of the main part of FIG. 1 ... Insulating substrate 2,3 ... Metallized metal layer 4,5,6 ... Cobalt-sulfur alloy metal layer 7,8,9 ... Gold conductive layer 10 ... Semiconductor integrated circuit element 11 ... Wire 12 ... External lead terminal 13 Lid
Claims (1)
おいて、該金の導電層の下地として、コバルト(Co)9
8.5〜99.999重量%、硫黄(S)0.001〜1.5重量%の合
金から成る金属層を設けたことを特徴とする金の導電層
を有する電子部品。1. In an electronic component having a gold conductive layer on a metal surface, cobalt (Co) 9 is used as a base of the gold conductive layer.
An electronic component having a gold conductive layer, characterized in that a metal layer made of an alloy of 8.5 to 99.999% by weight and sulfur (S) 0.001 to 1.5% by weight is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61204719A JPH0787233B2 (en) | 1986-08-30 | 1986-08-30 | Electronic component having a gold conductive layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61204719A JPH0787233B2 (en) | 1986-08-30 | 1986-08-30 | Electronic component having a gold conductive layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6360549A JPS6360549A (en) | 1988-03-16 |
| JPH0787233B2 true JPH0787233B2 (en) | 1995-09-20 |
Family
ID=16495175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61204719A Expired - Lifetime JPH0787233B2 (en) | 1986-08-30 | 1986-08-30 | Electronic component having a gold conductive layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787233B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6391172B2 (en) | 1997-08-26 | 2002-05-21 | The Alta Group, Inc. | High purity cobalt sputter target and process of manufacturing the same |
| CN1218071C (en) | 2000-06-30 | 2005-09-07 | 霍尼韦尔国际公司 | Method and apparatus for processing metals, and the metals so produced |
-
1986
- 1986-08-30 JP JP61204719A patent/JPH0787233B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6360549A (en) | 1988-03-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |