JPH0787247B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device such as a power IC applied to a device such as an inverter, and more particularly to a monolithic technology for the same.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional power device having a three-phase bridge structure. N-channel insulated gate bipolar transistors (hereinafter abbreviated as IGBT) Q _{1 to} Q ₆ are arranged in a three-phase bridge configuration. N-side IGBT on the positive potential side of the power supply VS
N channel on the negative potential side in the collector C of Q ₁ , Q ₃ and Q _5.
It is commonly connected to the emitters E of the IGBTs Q ₂ , Q ₄ and Q ₆ . Output U, N from the connection point of N-channel IGBT Q ₁ , Q ₂
An output V is output as a three-phase output from the connection point of the channel IGBTQ ₃ and Q _{4 and} an output W from the connection point of the N channel IGBTQ ₅ and Q ₆ . In addition, the free wheeling diodes D _{1 to} D ₆ are connected in antiparallel to the corresponding N-channel IGBTQ _{1 to} Q ₆ , respectively.

FIG. 4 is a circuit diagram showing a structure for one phase of the three-phase bridge structure shown in FIG. The outputs of the drive circuits DR ₁ and DR ₂ are connected to the gates of the corresponding N channel IGBTQ ₁ and Q ₂ , respectively. N-channel IGBT corresponding to protection circuits P ₁ and P ₂
The collector voltage of each of Q ₁ and Q ₂ is detected, and the output of the corresponding drive circuits DR ₁ and DR ₂ is limited when an overcurrent flows in the N-channel IGBT Q ₁ and Q ₂ . The same structure is applied to the other two phases.

Such a high power N-channel IGBT is manufactured on a semiconductor substrate by a vertical structure. N for one phase shown in FIG.
In channel IGBTQ _1, Q _2, terminal C, Q ₂ terminal U of Q _1, terminals U, Q ₂ terminal E for Q ₁ is a point corresponding to the structure. When the N-channel IGBTs Q ₁ and Q ₂ are manufactured with the same vertical structure, _two discrete N-channel IGBT elements are used to share the terminal U, and a connection is provided between them. In addition, the freewheeling diodes D ₁ and D ₂ also use discrete elements.

Further, the emitter of the N-channel IGBTQ ₁ is connected to the output U, and the potential changes abruptly. To prevent malfunction due to this potential change, drive circuits DR ₁ and DR ₂ and protection circuit
The power supply for external circuits such as P ₁ and P _{2 is} also different for each of the N-channel IGBTs Q ₁ and Q ₂ , and therefore the configuration is separate for each group.

[Problems to be Solved by the Invention]

Since the conventional semiconductor device is configured as described above,
N-channel IGBTs Q ₁ and Q _{2 for} phase and freewheeling diode D ₁ ,
D ₂ had to be composed of discrete elements, and each IGBT had to have a separate external circuit power supply. Therefore, there are problems that assembly such as connection between each element becomes complicated, manufacturing time and cost increase, and the entire apparatus becomes large and heavy.

The present invention has been made in order to solve the above problems, and an IGBT for one phase and a free wheeling diode are formed on the same substrate to facilitate assembly, reduce manufacturing time and cost, and reduce the entire device. Aims to obtain a small and lightweight semiconductor device.

[Means for Solving the Problems]

The first semiconductor layer of the first conductivity type and the second semiconductor layer of the second conductivity type, which has a conductivity type opposite to the first conductivity type, and has one main surface and the other main surface, are both the main surfaces. A semiconductor substrate provided with an exposed surface, an electrode provided on one main surface of the semiconductor substrate and in contact with both the first and second semiconductor layers, and a first semiconductor substrate. A first conductive type channel region formed on the other main surface of the second semiconductor layer and using the first semiconductor layer as a collector.
Of the insulated gate bipolar transistor and the second conductivity type channel region disposed on the other main surface of the first and second semiconductor layers of the semiconductor substrate and formed with the second semiconductor layer as a collector. A second insulated gate bipolar transistor having: a drive circuit for driving the first and second insulated gate bipolar transistors formed on the semiconductor substrate; and a first insulated gate bipolar transistor formed on the semiconductor substrate. A high breakdown voltage isolation layer that electrically isolates the bipolar transistor, the second insulated gate bipolar transistor, and the drive circuit from each other, and another main layer of the second semiconductor layer in which the first insulated gate bipolar transistor is disposed. The electrode disposed on the surface and short-circuited via the second semiconductor layer is used as one electrode, and the first insulated gate bipolar transistor is provided. The first free wheeling diode connected in anti-parallel between the collector and the emitter of the transistor and the second insulated gate bipolar transistor are arranged on the other main surface of the first semiconductor layer. The electrode short-circuited via the first semiconductor layer is used as one electrode, and the collector of the second insulated gate bipolar transistor,
A second freewheeling diode connected in antiparallel between the emitters.

[Action]

In the semiconductor device according to the present invention, since the first and second insulated gate bipolar transistors have the first and second conductivity types, respectively, and the semiconductor substrate also has the first and second semiconductor layers, By using the first and second semiconductor layers of the semiconductor substrate as active regions, the first and second semiconductor layers are formed.
Insulated gate bipolar transistor, and the first and second free wheeling diodes can be formed on the same semiconductor substrate.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a circuit diagram of one phase of a three-phase inverter integrated into a circuit according to an embodiment of the present invention.

First, the configuration will be described. The control circuit CL has an input terminal S
And has output terminals ST and SB. In addition, the low voltage monitoring circuit UV connected to the power supply voltage V _CC , the emitter of the IGBTQ ₇ and the IGBT
Overcurrent detection circuit O connected to the collector of Q ₂ respectively
An abnormal signal output output terminal F that outputs an abnormal signal corresponding to the input signals from the overheat detection circuits OT ₁ and OT ₂ etc. arranged adjacent to C ₁ and OC ₂ and IGBT Q ₇ and Q ₂ , respectively, is provided. Have. It also has a power supply voltage V _CC connection terminal and a ground terminal.

The output terminal ST is connected to the base of the transistor T ₁ via the resistor R ₁ , and the output terminal SB is connected to the transistor T ₄ via the resistor R ₆ ,
Commonly connected to the base of T ₅ . The collector of the transistor T ₁ is commonly connected to the bases of the transistors T ₂ and T ₃ via the resistor R ₃ . The base and collector of the transistor T ₂ are connected via the resistor R ₂ . The collector of the transistor T ₂ is connected to the emitter E ₁ of the P-channel IGBTQ ₇ . The emitters of the transistors T ₂ and T _{3 which} are commonly connected are connected to the gate G ₁ of the P-channel IGBTQ ₇ via the resistor R ₇ . The emitter of the transistor T ₁ is commonly connected to the collectors of the transistors T ₃ and T ₅ . The base and collector of the transistor T ₄ are connected via the resistor R ₄ . The collector of the transistor T ₄ is connected to the power supply V _CC . The emitters of the transistors T ₄ and T ₅ are commonly connected to the gate G ₂ of the N-channel IGBTQ ₂ via the resistor R ₅ . The collector of the transistor T ₅ is connected to the emitter E ₂ of N-channel IGBTQ _2. Overcurrent detection circuit
OC ₁ and OC ₂ are connected to the emitter E ₁ of the P-channel IGBTQ ₇ and the collector of the N-channel IGBTQ ₂ , respectively, and their outputs are connected to the control circuit CL. Control circuit CL, overcurrent detection circuits OC ₁ and OC ₂ , low voltage monitoring circuit UV, transistor T ₁ ~
T ₅ and the resistor R ₁ to R ₇ constitute a drive circuit DR, including a protection circuit.

Freewheeling diode between the collector and emitter of P-channel IGBTQ ₇ and between the collector and emitter of N-channel IGBTQ _2.
D ₁ and D ₂ are connected in antiparallel. P-channel IGBT
The collector of Q _{7 and} the collector of N-channel IGBT Q ₂ are connected and output U is output. The emitter E ₁ of P-channel IGBTQ ₇ is connected to the terminal C, emitter E ₂ of N-channel IGBTQ ₂ is grounded. The P-channel IGBTQ ₇ , the N-channel IGBTQ ₂ and the free wheeling diodes D ₁ and D ₂ form an arm A for one phase of the power device. The other two-phase arms have the same structure, and the three arms are connected as shown in FIG.

Next, the operation will be described. When a signal from a microcomputer or a gate array is input to the input terminal S of the control circuit CL composed of a well-known PWM input switching regulator, P-channel IGBTQ ₇ and N-channel are respectively output from the output terminals ST and SB. A signal for driving the IGBT Q ₂ is output.

Output ST is "H" via the a level of resistance R ₁ increases the base potential of the transistor T ₁ is the transistor T ₁ is conducting further transistor T ₂ is nonconductive, the transistor T ₃ is conductive. A voltage obtained by dividing the voltage at the terminal C by the resistors R ₂ and R ₃ is applied to the gate G ₁ of the P-channel IGBTQ ₇ via the resistor R ₇ . This voltage is lower than the voltage at terminal C, so P-channel IG
BTQ ₇ becomes conductive. When the output ST becomes "L" level, the transistor T _1, T ₃ becomes non-conductive, transistor T ₂ is turned on. The gate G ₁ of the P-channel IGBTQ ₇ is almost supplied with the voltage of the terminal C, and the P-channel IGBTQ ₇ becomes non-conductive.

The base potential of the transistor T _4, T ₅ via a resistor R ₆ output SB becomes "H" level rises, the transistor T ₄ is rendered conductive, the transistor T ₅ is rendered non-conductive. N channel IGBTQ ₂
Power supply voltage V _CC is applied to the gate G ₂ of the N channel IGBT Q ₂ and the N channel IGBT Q ₂ becomes conductive. Output the SB becomes "L" level nonconducting transistor T ₄ is, T ₅ becomes conductive. N channel IG
The gate G ₂ of BTQ ₂ is given approximately ground potential, N-channel IGBTQ ₂ becomes non-conductive.

During such operation, P channel IGBTQ ₇ and N channel IGBTQ ₂
When both are turned on at the same time, the terminal C is directly connected to the ground level. Therefore, in order to avoid this and perform stable operation, the outputs ST and SB do not go to "H" level at the same time.
Further, during each "H" level period, the control circuit CL provides a dead time in which both are at "L" level.

Overcurrent detection circuits OC ₁ and OC ₂ are P-channel IGBTQ ₇ and N, respectively.
Detects overcurrent flowing in channel IGBTQ ₂ . Overheat detection circuits OT ₁ and OT ₂ are P-channel IG on the upper arm side, respectively.
BTQ ₇ , freewheeling diode D ₁ and lower arm N-channel IGBTQ ₂ and freewheeling diode D ₂ detect overheating. Further, the low voltage monitoring circuit UV detects a decrease in the power supply voltage V _CC .
The control circuit CL receives such a detection signal, and outputs an output signal regardless of the input signal S when any abnormality occurs.
The ST and SB are suppressed, and the driving of the P channel IGBTQ ₇ and N channel IGBTQ ₂ is stopped. Further, the abnormality signal output F is output to the outside in order to notify the abnormality state to the outside according to the combination of each detection signal.

FIG. 2 is a sectional view showing a structure in which the arm A shown in FIG. 1 is formed on a semiconductor substrate. The n ⁺ regions 1a and 1b and the p ⁺ region 5 are provided on the electrode 14 serving as the output U. P ⁺ regions 2a and 2b and n ⁺ regions 6 and 13 are provided thereon. The p ⁺ region 2a, n ⁺ region 6 is in contact with the n ⁺ region 1b, and the p ⁺ region 2b is the n ⁺ region 1a,
1b and p ⁺ region 5 are in contact, and n ⁺ region 13 is in contact with n ⁺ region 1a. On top of that, n ⁻ region 3, p ⁺ buffer region 8 and
An n ⁺ buffer area 7 is formed. The n ^- region 3 is in contact with the p ⁺ region 2a, and the p ⁺ buffer region 8 is the p ⁺ region 2a, 2b and the n ⁺ region 6
, And the n ⁺ buffer region 7 is in contact with the p ⁺ region 2b and the n ⁺ region 13. On the thinly formed n ⁺ buffer region 7 and p ⁺ buffer region 8, n ⁻ region 15 and p ⁻ region 16 are formed, respectively. The high breakdown voltage isolation layer 4a has an n ⁻ region 3 and ap ⁺ buffer region 8
And p ⁻ region 16 are separated from each other, and high breakdown voltage isolation layer 4b separates p ⁺ buffer region 8 and p ⁻ region 16 from n ⁺ buffer region 7 and n ⁻ region 15. The n ⁺ buffer region 7 and the P ⁺ buffer region 8 are for improving the latch-up resistance of each IGBT.

In the n ⁻ region 15, ap region 9 having a high concentration in the central portion and a low concentration in the peripheral portion is selectively provided, and the n ⁻ region 10 is further provided in the p region 9.
Are selectively provided. In the p ⁻ region 16, an n region 11 having a high concentration in the central portion and a low concentration in the peripheral portion is selectively provided, and further, a p ⁻ region 12 is selectively provided in the n region 11. The emitter electrode is in contact with the central part of the p region 9 and a part of the n ⁻ region 10.
E ₂ is in contact with the central portion of n region 11 and a part of p ⁻ region 12 to be provided with emitter electrode E ₁ . Gate electrodes G ₂ and G ₁ are provided at both ends of the p region 9 and both ends of the n region 11 with an insulating film interposed therebetween.

The collector of the P-channel IGBTQ ₇ is p ⁺ buffer region 8 and
It is formed by the p ⁻ region 16, the emitter is formed by the p ⁻ region 12, and the channel region is formed by the n region 11 just below the gate electrode G ₁ . N-channel IGBT Q ₂ collector
It is formed by the n ⁺ buffer region 7 and the n ⁻ region 15, the emitter is formed by the n ⁻ region 10, and the channel region is formed by the p region.
The region 9 is formed immediately below the gate electrode G ₂ . Also p
The collector injection region of the channel IGBTQ ₇ is defined by the n ⁺ regions 1b, 6 and the collector injection region of the N channel IGBTQ ₂ is defined by the p ⁺ regions 2b, 5
Formed by.

The anode of the free wheeling diode D ₁ is formed by the p ⁺ regions 5, 2b, the p ⁺ buffer region 8 and the p ⁻ region 16, and the cathode is n
Formed by region 11. The cathode of the free wheeling diode D ₂ has n ⁺ regions 1a and 13, n ⁺ buffer region 7 and n ⁻ region 15
And the anode is formed by the p-region 9.

Further, part or all of the drive circuit DR shown in FIG. 1 can be formed in the n ⁺ region 3, and the p ⁺ region 2a functions as a subtoslate thereof.

By connecting the P-channel IGBTQ ₇ and the N-channel IGBTQ ₂ in a totem-pole type in this way, the electrode 14 serving as the output U is made common and the P-channel IGBTQ ₇ and the N-channel IGBT are formed on the same substrate.
Q ₂ and freewheeling diodes D ₁ and D ₂ can be formed. Also, since the potentials of the emitters E ₁ and E ₂ of the P-channel IGBTQ ₇ and N-channel IGBTQ ₂ , which are the reference potentials of the control voltage applied to the gate electrodes G ₁ and G ₂ , are constant irrespective of the output U, The power supply V _CC of the drive circuit DR can be shared by the upper arm side and the lower arm side.
The configuration of the drive circuit DR is simplified, and it is also possible to provide a part or all of it in the n ⁻ region 3 on the same substrate as the P channel IGBTQ ₇ and the N channel IGBTQ ₂ .

If MOSFET or bipolar transistor is used instead of IGBT, P-channel MO
The resistance when the SFET is conducting and the saturation voltage of the PNP transistor become high, making it unusable for practical use. There is also a problem that it is difficult to make it monolithic in manufacturing. In the case of the IGBT, there is no such problem as described above, and the P-channel IGBTQ ₇ and the N-channel IGBTQ ₂ have almost the same characteristics such as current capacity.
Therefore, similar characteristics can be obtained with chip areas of approximately the same size, which is advantageous in manufacturing.

〔The invention's effect〕

As described above, according to the present invention, the semiconductor device is configured such that the collectors of the first and second insulated gate bipolar transistors of the first and second conductivity types are commonly connected, and the semiconductor substrate is also the first and second semiconductor substrates. Since it has two semiconductor layers, the first and second semiconductor layers of the semiconductor substrate are
By using the second insulated gate bipolar transistor and the active region such as the free wheeling diode, these elements can be formed on the same semiconductor substrate. Further, the power supplies for the circuits for driving the first and second insulated gate bipolar transistors can be made common, and the circuit configuration is simplified. Therefore, it is possible to obtain a semiconductor device which is easy to assemble, reduces manufacturing time and cost, and has a small size and light weight as a whole.

[Brief description of drawings]

1 is a circuit diagram of one phase of a three-phase inverter according to an embodiment of the present invention, FIG. 2 is a sectional view of a structure of an arm A shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional power device, and FIG. FIG. 4 is a circuit diagram of one phase of the power device shown in FIG. In the figure, Q ₇ is a P channel IGBT and Q ₂ is an N channel IGBT.
T, D ₁ and D ₂ are freewheeling diodes, 4a and 4b are high breakdown voltage isolation layers, 14
Is an electrode, 1a, 1b, 6, 13 are n ⁺ regions (first semiconductor layer), 2a, 2
b and 5 are p ⁺ regions (second semiconductor layer). In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of front page (56) Reference JP-A-60-62152 (JP, A) JP-A-58-212173 (JP, A) JP-A-61-180472 (JP, A) JP-A-61-285750 (JP , A) Actual development Sho 57-115260 (JP, U)

Claims (1)

[Claims] 1. A first semiconductor layer of a first conductivity type having a main surface and another main surface, and a second semiconductor layer of a second conductivity type which is a conductivity type opposite to the first conductivity type. Semiconductor substrates each having an exposed surface on both main surfaces, and electrodes arranged on one main surface of the semiconductor substrate and in contact with both the first and second semiconductor layers, A first insulated gate having a channel region of a first conductivity type, which is disposed on the other main surface of the first and second semiconductor layers of the semiconductor substrate and has the first semiconductor layer as a collector. Type bipolar transistor, and a second conductivity type channel region which is disposed on the other main surface of the first and second semiconductor layers of the semiconductor substrate and is formed with the second semiconductor layer as a collector. A second insulated gate bipolar transistor formed on the semiconductor substrate; And a drive circuit for driving the first and second insulated gate bipolar transistors, the first insulated gate bipolar transistor, the second insulated gate bipolar transistor, and the drive circuit formed on the semiconductor substrate. A high breakdown voltage isolation layer for electrically isolating each of them and a second semiconductor layer on which the first insulated gate bipolar transistor is provided are disposed on the other main surface.
A first free wheeling diode connected in anti-parallel between the collector and the emitter of the first insulated gate bipolar transistor, and the second insulated gate, wherein the electrode short-circuited via the semiconductor layer is used as one electrode. Type bipolar transistor is disposed on the other main surface of the first semiconductor layer on which the first bipolar transistor is disposed.
Of the second insulated gate bipolar transistor, and a second free wheeling diode connected in antiparallel between the collector and the emitter of the second insulated gate bipolar transistor.