JPH0787377B2 - Delta modulator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta modulator of an analog-digital converter which has reduced distortion.

2. Description of the Related Art A delta modulator is a type of analog-to-digital converter that focuses on the difference between each sample when sampling at regular time intervals, encodes this information, and corrects the error that occurs in subsequent samples. It will be corrected by.

Hereinafter, the conventional delta converter as described above will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional delta modulator. Generally, a delta modulator is composed of an analog signal input terminal 201, a subtractor 202, a comparator 203, a local demodulator 204, and a delta modulation signal output terminal 205 as shown in FIG. Information indicating whether the potential has increased or decreased compared with the potential sampled before the sampling period is output by a 1-bit code.

First, the analog signal input to the analog input terminal 201 is input to the subtractor 202. The subtractor 202 takes the difference from the output of the local demodulator 204 which outputs the potential sampled one sampling period before, and inputs it to the comparator 203. If the signal input to the comparator 203 is larger than a certain reference potential, it is determined that the analog input signal has increased as compared with the potential before one sampling. If it is smaller than the reference potential, it is determined that the analog input signal has decreased compared to the potential before one sampling. Then, the comparator 203 outputs “0” to the delta modulation signal output terminal 205 when it determines “1” when it determines that it increases, and this becomes the delta modulation signal.
On the other hand, the local demodulator 204 demodulates an analog signal based on the delta modulation signal output from the comparator 203 and outputs the demodulated analog signal to the subtractor 202.

FIG. 4 is a circuit diagram showing an example of the above-mentioned conventional delta modulator. The analog signal input from the analog signal input terminal 206 has a direct current component removed through a capacitor 207, and is output from a local demodulator 215 through a resistor 208 to a resistor 209.
Is added to the signal passed through and D of the D flip-flop 213 is added.
Input to the terminal. However, since the inverted output () of the D flip-flop 213 is used for the input of the local demodulator 215, the resistors 208 and 209 have the same effect as the subtractor.

Next, the D flip-flop 213 serves as a comparator that determines whether the analog input signal is increased or decreased in comparison with the potential sampled one sampling before according to the input potential. If the potential of the D terminal is higher than the threshold level, it is determined to increase, and "1" is output to the Q terminal and "φ" is output to the terminal.
If the potential of the D terminal is lower than the threshold level, it is determined to decrease and "φ" is output to the Q terminal and "1" is output to the terminal. The signal output from the Q terminal is a delta conversion signal and is output to the delta modulation signal output terminal 214.
On the other hand, the delta modulation signal output from the terminal, which is the inverted “1” or “φ”, is input to the local demodulator 215. The local demodulator 215 is composed of a resistor 211 and a capacitor 210,
The capacitor 210 is charged and discharged through the resistor 211 by inputting the potentials corresponding to “1” and “φ”. At this time, when the time constant τ of the resistor 211 and the capacitor 210 is much larger than the sampling period T, this local demodulator 215 becomes an integrating circuit, and the integrated result is the analog input signal sampled one sampling period before. It becomes an electric potential.

However, the conventional delta modulator described above has a problem that distortion occurs due to the characteristics of the D flip-flop.

FIG. 5 shows (a) clock signal when analog input signal is zero, (b) D terminal input signal of D flip-flop of ideal delta modulator, (c) D of ideal delta modulator.
Output signal of Q terminal of flip-flop, (d) D terminal input signal of D flip-flop in conventional delta modulator (point B in FIG. 4), (e) Q terminal of D flip-flop in conventional delta modulator Output signal (C in FIG. 4
FIG. 6 is a waveform diagram showing points).

When there is no analog input signal, the output delta modulation signal is ideally a signal that repeats "1" and "φ" at each rising edge of the clock signal supplied to the D flip-flop as shown in FIG. 5 (c). Become. When the input signal of the D terminal of the D flip-flop is higher than the threshold level V _TH at the rising edge of a certain clock, “1” is output from the Q terminal.
Is output, and "φ" is output from the terminal. When “φ” is output from the terminal, the local demodulator 215 discharges with a time constant determined by the resistor 211 and the capacitor 210 of the local demodulator 215, and the input signal at the D terminal of the D flip-flop begins to fall V _TH It becomes a lower potential. Then, at the next rising edge of the clock signal, the potential of the D terminal of the D flip-flop
Since the potential is lower than V _TH, “φ” is output from the Q terminal,
"1" is output from the terminal. When "1" is output from the terminal, the local demodulator 215 is charged, and the input signal of the D terminal of the D flip-flop 213 starts to rise and has a potential higher than V _TH . By such repetition, in ideal operation, "1" and "φ" are repeatedly output from the Q terminal of the D flip-flop.

However, in the actual D flip-flop in the conventional delta modulator, since there is a delay Δt from the rising of the clock to the output to the Q terminal or the terminal, there is “1” from the Q terminal of the D flip-flop which is the delta modulation signal. "," Φ "is not output alternately. As shown in FIG. 5 (d), when a certain clock rises, D
When the input signal at the D terminal of the flip-flop has a potential higher than the threshold level V _TH , there is a delay Δt, and therefore, there is a delay Δt from the terminal, and then “φ”.
Is output. Therefore, the potential of the input signal at the D terminal of the D flip-flop begins to drop with a delay of Δt. In this case, when the next clock rises, the input signal of D terminal is V _TH
A state in which the electric potential is still higher occurs. When the input signal of the D terminal is higher than V _TH, "φ" is output again from the terminal, and the potential of the D terminal continues to drop. At the rising edge of the next clock, the input signal at the D terminal becomes a potential lower than V _TH and "1" is output from the terminal, but at the rising edge of the next clock, "1" is output again from the terminal due to the delay Δt. It In other words, since there is a delay from the rise of the clock to the output of the terminal, the Q output which is a delta modulation signal does not output "1" and "φ" alternately,
A judgment error such as "1", "1", "φ", "φ" which is not an ideal operation occurs.

In the above example, the case where the analog input signal is zero has been described, but when there is an input signal, this determination error causes distortion. In particular, when the potential at the point A in the circuit diagram of the conventional delta modulator in FIG. 4 is close to the threshold level V _TH of the D flip-flop 213, distortion is likely to occur, and the power supply voltage is 5 V, V _TH 2.5 When a sine wave is input to the analog signal input terminal using a D flip-flop with V, output “1” level of 5V, and output “φ” level of 0V, the absolute value of the slope of the sine wave is the largest at point A. The point is
Since the potential is 2.5 V, distortion occurs at this point, and second harmonic distortion occurs in the delta modulation signal.

The present invention solves such conventional problems and provides a high-performance delta modulator in which distortion is reduced.

To achieve this object, the delta modulator of the present invention provides an analog signal so that the DC voltage level of the output signal of the offset circuit is lower than the DC voltage level of the output signal of the local demodulator. It is configured to control the DC offset.

Operation In the present invention, the absolute value of the slope when the potential of the comparator input signal rises differs from the absolute value of the slope when the potential of the comparator input signal is different by performing the above DC offset control. That is, when the potential of the input signal of the comparator rises, the slope is small and the input signal of the comparator becomes a low potential with respect to the reference potential of the comparator several times in succession. Therefore, even if a judgment error due to delay occurs, the delta modulation signal originally outputs "φ" several times in succession, so that the relative error due to one judgment error becomes small, and the distortion generation becomes small. Further, when the potential of the input signal of the comparator is decreasing, the absolute value of the slope becomes large, and the probability of becoming lower than the comparator reference potential during the sampling period T and the delay Δt (T−Δt) increases. It is possible to realize a high-performance delta modulator by making it difficult to make a judgment error and reducing the occurrence of distortion.

Embodiment Hereinafter, a delta modulator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a delta modulator according to an embodiment of the present invention. Since the delta modulator of this embodiment shown in FIG. 1 has basically the same configuration as the conventional delta modulator, the same components are designated by the same reference numerals and detailed description thereof will be omitted. 207 in FIG.
Is a capacitor for removing the DC component of the analog input signal, and 101 is a resistor for controlling the DC voltage level of the analog input signal to be lower than the DC voltage level of the output signal of the local demodulator 215.

Like the conventional delta modulator shown in FIG. 4, the delta modulator of this embodiment also adds the output of the local demodulator 215 and the analog input signal. However, since the resistor 101 exists, the resistor 209 , The current flows to the ground point through the resistor 208 and the resistor 101, and the absolute value of the slope of the time change when the output potential of the local demodulator 215 increases / decreases due to charging / discharging of the capacitor 210 of the local demodulator 215 is different. come. Therefore, the input potential of the D terminal of the D flip-flop (hereinafter referred to as DFF) 213 has a smaller slope when rising and an larger absolute value of the slope when falling, so that distortion generation due to delay of the DFF 213 can be reduced.

Referring to FIG. 2 in detail below, FIG.
It is a waveform diagram which shows an example of the sampling clock signal of DFF213, (b) the input signal to DFF213, and (c) the delta modulation signal output. As can be seen from FIG. 2 (b), by controlling the DC offset, the absolute value of the slope when the potential of the input signal of the DFF 213 rises and the absolute value of the slope when it falls are different. When the potential of the input signal of DFF213 is rising, the slope is small and the input signal of DFF213 is DF continuously several times.
The potential becomes lower than the reference potential of F213. Therefore, even if a judgment error due to delay occurs, the delta modulation signal originally outputs "φ" several times in succession, so that the relative error due to one judgment error becomes small, and the distortion generation becomes small.
When the potential of the input signal of DFF213 is decreasing, the absolute value of the slope is large, and the probability of becoming lower than the reference potential of DFF213 increases during the sampling period T and the delay Δt (T−Δt). , It is hard to make a judgment error. Therefore, the occurrence of distortion can be reduced, and a high-performance delta modulator can be realized.

As described above, the offset value of the analog input signal can be controlled with a slight improvement to provide a high-performance delta modulator with reduced distortion.

In this embodiment, the resistor is used to control the offset immediately after the capacitor for removing the DC component of the analog input signal, but the same effect can be obtained by using the resistor in the D terminal input portion of the DFF213.

EFFECTS OF THE INVENTION As described above, the delta modulator of the present invention can reduce the distortion caused by the delay characteristic of the element by the offset circuit that controls the DC offset of the analog input signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a delta modulator in one embodiment of the present invention, FIG. 2 is (a) a sampling clock signal when the analog input signal is zero, and (b) D of a delta modulator in this embodiment. The waveform diagram of the D terminal input signal of the flip-flop, (c) the same Q terminal output signal, FIG. 3 is a block diagram showing a conventional delta modulator, FIG. 4 is a circuit diagram of the conventional delta modulator, and FIG. The figure shows (a) when the analog input signal is zero.
Sampling clock signal, (b) D of an ideal delta modulator
D terminal input signal of flip-flop, (c) Q terminal output signal of D flip-flop of ideal delta modulator,
(D) A waveform diagram of the D terminal input signal of the D flip-flop of the delta modulator in the conventional example, and (e) the Q terminal output signal of the same. 101 ... Offset circuit resistor, 206 ... Analog signal input terminal, 212 ... Sampling clock input terminal, 213 ... D flip-flop, 214 ... Delta modulation signal output terminal, 215
...... Local demodulator, 201 …… Analog signal input terminal, 202 ・ ・ ・
… Subtractor, 203 …… Comparator, 204 …… Local demodulator, 205…
... Delta modulation signal output terminal, T ... sampling clock cycle, V _TH ... D flip-flop threshold level, Δt ... D flip-flop delay time.

Claims (1)

[Claims] 1. An offset circuit for controlling a DC offset of an analog signal, a subtractor for taking a difference between an output of the offset circuit and a local demodulation signal, and a comparison for sampling an output of the subtractor and converting it into a delta modulation signal. And a local demodulator for demodulating the output of the comparator into an analog signal, the analog signal so that the DC voltage level of the output signal of the offset circuit is lower than the DC voltage level of the output signal of the local demodulator. A delta modulator characterized by controlling the DC offset of.