JPH0787435B2 - Multiplex channel receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexed channel device for data transmission of a plurality of lines or data transmission in which a plurality of channels are multiplexed on one line. For example, in the ISDN primary interface, as many as 24 or 30 channels are multiplexed in one line and these operate simultaneously to perform data processing.

In this case, a huge amount of hardware is required to support simultaneous processing.

[0003]

2. Description of the Related Art FIG. 7 is a conventional system configuration diagram. The plurality of lines L are connected to the receiver / driver RD through the respective modems M, and the serial-parallel converter SP corresponding to the reception data RXD in response to the reception clock RXC.
Is taken into. Then, the serial-parallel converter S
The data stored in P is the serial-parallel converter SP
It is converted into parallel data by and transmitted to the microprocessor MPU, memory RAM, ROM and the like. As shown, in the conventional configuration, a serial-parallel converter SP is provided for each RD. As described above, a serial-parallel converter is required as a receiving device for a multiplexed channel, but as this serial-parallel converter, a device called "line control LSI" has been widely used conventionally. A signal from the line interface is supplied to the line control LSI by the receiver / driver RD to the serial-parallel converters # 0 to #n for each channel.

[0004]

As described above, conventionally, when the line control LSI is used to control the simultaneous operation of a plurality of lines or a plurality of channels in one line, it is necessary to control each channel as shown in the drawing. Requires a serial-to-parallel converter. Therefore, such a configuration causes an increase in the amount of hardware, resulting in an increase in cost.

An object of the present invention is to reduce the amount of hardware by sharing one multi-channel serial-parallel converter, thereby reducing the cost.

[0006]

FIG. 1 is a system configuration diagram to which the present invention is applied. As shown in the figure, in the present invention, one serial-parallel converter is shared by each channel. As described above, in order to share the serial-parallel converter between multiple channels, the multiplex channel receiver of the present invention controls the operation from the outside and saves / restores the internal information from the outside. Means and a memory for storing the save / restore data are provided.

[0007]

When the data is received, the serial-parallel converter SP normally performs an operation of converting the input serial data into parallel data in response to a predetermined external clock. The serial-to-parallel converter is usually composed of a shift register, but the internal information of this shift register (that is, the data in the shift register and the number of bits of the data) is temporarily saved in an external memory according to an instruction from the outside.
I wish I could be back.

If such data saving / restoring is temporarily executed, the original data in the shift register constituting the converter is used as a step for sharing the serial-parallel converter with a plurality of channels. Internal information SAVE
→ LOAD of new internal information → Receive operation (ordinary serial-parallel converter processing, that is, serial-to-parallel conversion, and if the assembly into parallel data is completed, send that data to the receive buffer) -> SAVE of internal information-> By repeating the operation described below, multiple channels can be operated simultaneously even if only one serial-parallel converter is provided.

[0009]

FIG. 2 is a block diagram of an embodiment of the present invention. RX
-FIFOs # 0, # 1, and # 2 are reception FIs for each channel
FO (first-in first-out buffer), RG is a data presence / absence display register, RP is a read pulse generation circuit, S is a serial-parallel converter of the present invention, and RM is a save RAM. The serial-parallel converter SP comprises a reception shift register RXS and a reception counter RXT.

Normally, the line control LSI is used for transmission / reception (Tx
/ Rx) each FIFO, each register for transmission / reception,
And functional blocks such as a transmission / reception CRC generator / checker. In the present invention, each of these functional blocks of the line control LSI is operated intermittently. In the basic operation of the present invention, as an operation for a predetermined channel, a predetermined transmission / reception clock is externally supplied to the serial-parallel converter, and serial data is transmitted / received for a predetermined number of bits in a normal operation. For another channel operation, the data holding the current state of each functional block is temporarily saved in the external storage.

FIG. 3 is a signal timing chart of the present invention,
FIG. 4 is a basic flow chart of the present invention using FIFO # 0 as an example. As shown in FIGS. 3 and 4, serial data for each channel is transferred by a clock for serial data, and FI is generated by a write pulse RX pulse to the FIFO.
Captured in FO. Then, the read pulse RP is sent from the read pulse generation circuit to the FIFO to read from the FIFO.

The operation will be specifically described below. For each FIFO for transmission / reception (Tx / Rx), a value of a pointer that indicates how much data is stored in a plurality of FIFOs, and RA for saving data in the FIFO
Evacuate to M. For each shift register for transmission / reception, the value of the pointer indicating up to what bit of data in each shift register and the data in the shift register are saved in the save RAM. Also for the CRC generator checker, the CRC value calculated so far is saved in the save RAM.

Next, after the previous save data of another channel is restored from the save RAM for the operation of another channel, a transmit / receive clock is externally supplied to transmit / receive.
After performing the reception operation for several bits, the operation shifts to another channel operation. Here, there is a difference between the actual transmission / reception speed of the line and the transmission / reception speed of the serial-parallel converter according to the present invention. I am trying to adjust it. That is, the received data from the line is sampled and then held in the serial data storage unit (FIFO) at the same speed as the communication speed, and the serial-parallel converter of the present invention operates at a speed higher than the communication speed from the serial data storage unit. Take out Serial-parallel conversion operation.

An example of an interface in which a plurality of channels are multiplexed on one line as found in ISDN will be described below. In ISDN, a plurality of channels are time-divisionally transmitted on one transmission path physically. The method of separating the data from here to each channel depends on the interface contract (frame format),
For example, after repeating one or several frame sync bits by matching a predetermined pattern,
It is possible to count based on each frame synchronization bit and extract as data of each channel.

The serial data separated as described above is stored in the FIFO for each channel. Attention should be paid here at the timing of FIG. 3 so as not to collide with the data reading of the FIFO from the serial-parallel converter. That is, reading / writing of the FIFO does not occur simultaneously, writing is done at the same speed as the bit rate of the channel, and reading is done at a speed several times faster than this. Note that reading is performed only when there is data remaining in the FIFO.

Next, the operation of the serial-parallel converter will be described. In FIG. 2, this configuration can also be configured by a microprocessor (MPU), for example. The microprocessor can know in which FIFO the data exists by the data presence / absence display register RG of each transmission FIFO. Where FIFO
Depending on the presence or absence of data, there is also a function of notifying how much data remains. The microprocessor gives a read pulse (which can be read faster than the write pulse) to the FIFO in which the data remains and reads the serial data, and the data is given as the data of the serial-parallel converter, and the read pulse is It is given as a serial clock.

Inside the serial-parallel converter, data is sampled by the clock and assembled into parallel data by the shift register. Here, if it is assembled as 8-bit parallel data, it becomes a reception character. If the number of FIFO read pulses is not enough for assembling 8-bit parallel data, the number of effective bits remaining in the shift register is 3 bits. It can be known by the counter.

The microprocessor SAVEs the contents of the shift register and the contents of the 3-bit counter to the RAM for saving for the next channel operation, and restores the previously saved data of the next channel to the shift register and the 3-bit counter. , Data of several bits are read from the FIFO and serial-parallel conversion is performed. In the present invention, these operations are repeated.

Although only the shift register unit is described above for simplification of explanation, the same applies to other parts, such as the CRC calculation register and the sync pattern detection circuit for synchronizing the SYN flag, and the current contents and status are shown. Evacuation /
It can be operated by returning. FIG. 5 is a detailed diagram of the data presence / absence display register shown in FIG. A register is provided for each FIFO input, and the register is selected and output by the register selection pulse.

FIG. 6 is a detailed diagram of the read pulse generation circuit shown in FIG. A register is provided for each FIFO, and the output from the pulse generation counter is input to AND gates # 0 to # 2, and a read pulse is generated when the output matches the output of the register.

[0021]

As described above, according to the present invention,
In data processing of multiplexed channels, the serial-to-parallel converter can be shared by each channel to save / restore data, so that it is possible to reduce hardware and cost.

[Brief description of drawings]

FIG. 1 is a system configuration diagram to which the present invention is applied.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a signal timing chart of the present invention.

FIG. 4 is a flowchart of an embodiment of the present invention.

5 is a detailed view of the display register of FIG.

FIG. 6 is a detailed diagram of the read pulse generation circuit of FIG.

FIG. 7 is a conventional system configuration diagram.

[Explanation of symbols]

 SP ... Serial-parallel converter RD ... Receiver driver FIFO ... First-in first-out buffer RG ... Display register RP ... Read pulse creation circuit RM ... Save memory L ... Line RXC ... Receive clock RXD ... Received data

Claims (2)

[Claims] 1. In a multiplexed channel device for data transmission of a plurality of lines or data transmission in which a plurality of channels are multiplexed by one line, serial data storage means for temporarily storing data from the line is multiplexed. A single serial-parallel conversion means for receiving serial data and converting it into parallel data and a saving means for temporarily saving serial data being received by the serial-parallel conversion means are provided, and the serial-parallel conversion means makes parallel A multiplexed channel receiving apparatus characterized in that, when converting into data, serial data is saved in the saving means while serial-parallel conversion of the next storage means is performed by time division. 2. An apparatus for converting multiplexed reception data by a single serial-parallel conversion means, comprising a counting means for counting an effective bit length in a shift register having a predetermined data length.