JPH0787438B2 - Receive memory circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a receiving memory circuit,
In particular, the present invention relates to a reception memory circuit for suppressing jitter caused by deletion of overhead bits, stuff bits, etc. performed in a demultiplexing unit of a stuff synchronous multiplex converter.

[0002]

2. Description of the Related Art Conventionally, in this type of receiving memory circuit, bits other than information bits are removed from an input signal to reproduce a signal consisting of only information bits. At this time,
The reception memory circuit also smooths the jitter that occurs when bits other than the information bits are removed.

Here, in addition to information bits, overhead bits and stuff bits are inserted into the input signal in accordance with a predetermined frame format. The insertion positions of signals other than these information bits are clarified by the frame synchronization circuit and the destuff circuit at the preceding stage.

FIG. 2 is a block diagram showing the structure of a conventional receiving memory circuit. In the figure, an input signal 101 is connected to k (k bits) memory cells 10-1 to 10-k, and one bit is sequentially written to each of the memory cells 10-1 to 10-k.

The memory cells 10-1 to 10-k are elastic stores capable of writing and reading independently.
The write control is performed by the write address counter 12.

The write address counter 12 sequentially writes the information bits in the input signal 101 to the memory cells 10-1 to 10-k according to the write control signal 102. That is, the write address counter 12 stops the write control according to the write control signal 102 at the bit positions such as the overhead bit and the stuff bit, and the memory cell 10
Only the information bits in the input signal 101 are written to -1 to 10-k.

Reading from the memory cells 10-1 to 10-k is performed with the clock reproduced by the voltage controlled oscillator (VCO) 15, that is, with the same clock as the bit rate of the information signal.

The read address counter 16 operates with the clock from the voltage controlled oscillator 15, and its output is input to the selector 11. Although the outputs of all the memory cells 10-1 to 10-k are connected to the selector 11, the memory cell 1 is output by a signal from the read address counter 16.
The contents of 0-1 to 10-k are sequentially output as the output signal 103.

The oscillation frequency control of the voltage controlled oscillator 15 is P
The oscillation frequency is controlled by the output of the phase comparison circuit 13 from which the high-frequency jitter component is removed by the low-pass filter 14.

The phase comparison circuit 13 generates a voltage proportional to the phase difference between the write timing from the write address counter 12 and the read timing from the read address counter 16. The phase comparison circuit 13 can be easily realized by an exclusive OR circuit or the like.

Therefore, since the read address counter 16 operates at the oscillation frequency of the voltage controlled oscillator 15 controlled by the output of the phase comparison circuit 13, the memory cell 10-
1 to 10-k write phase and memory cells 10-1 to 1
The read phase from 0-k is always kept in a constant phase relationship.

As a result, the output signal 103 output from the selector 11 is only the information bits in the input signal 101, and the jitter caused by removing other bits such as overhead bits and stuff bits is also reduced.

[0013]

In the above-mentioned conventional receiving memory circuit, since the signal to be written in the memory needs to be a serial bit string, the speed required for the circuit element becomes high when a high speed signal is targeted. It becomes difficult to realize a large-scale LSI using a CMOS process or the like.

Therefore, an object of the present invention is to solve the above-mentioned problems and to make it possible to use a large-scale LSI using a CMOS process or the like as an element constituting a memory circuit, thereby making the circuit compact and reducing the power consumption. It is an object of the present invention to provide a receiving memory circuit that can be realized.

[0015]

SUMMARY OF THE INVENTION A receiving memory circuit according to the present invention is a receiving memory circuit for extracting an information bit from an input signal based on a write control signal indicating an information bit to be extracted, and a pair of the input signals. n (n is a positive integer) serial-parallel conversion means, m (m is a multiple of n) memory cells for storing the input signal, and the output of the conversion means based on the write control signal Distribution means for distributing to the m memory cells.

[0016]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the input signal 101 is serial-parallel converted into 1 to n (n is a positive integer) by the serial-parallel conversion circuit 1 to be n parallel data. The signals converted into n parallel data by the serial-parallel conversion circuit 1 are output to the selector circuit 2.

The selector circuit 2 can arbitrarily combine one-to-one connection of n parallel data and n output signals, and the control of this combination is performed by a control signal from the write address counter 5. That is, the selector circuit 2 is controlled by the control signal from the write address counter 5, and distributes n pieces of parallel data to m pieces (m is a multiple of n) of memory cells 3-1 to 3-m.

The output of the selector circuit 2 is the memory cell 3-1.
It is connected to the input of an m-bit memory consisting of ~ 3-m. That is, the first output of the selector circuit 2 is the memory cells 3-1, 3- (n + 1), 3- (2n + 1), ...
..., 3- (m-n + 1), respectively.

The second output of the selector circuit 2 is the memory cells 3-2, 3- (n + 2), 3- (2n + 2),
..., 3- (mn + 2), respectively. Similarly, the nth output of the selector circuit 2 is the memory cell 3
-N, 3-2n, 3-3n, ..., 3-m, respectively. That is, each output terminal of the selector circuit 2 is m /
It is connected to n memory cells.

The positions of the bits other than the information bits in the input signal 101, that is, the positions of the bits that are not written in the memory are input to the write address counter 5 as the write control signal 102. The write control signal 102 is in units of n bits for serial / parallel conversion, and is composed of the position of the information bit and the number of bits indicating which of the n bits is the information bit.

The write address counter 5 is responsive to the write control signal 102 to write data in the memory cells 3-1 to 3-1.
Send write signal to 3-m. At the same time, the write address counter 5 controls the selector circuit 2 to write the information bits in the input signal 101 to the memory cells 3-1 to 3-1 to which the writing is performed.
It outputs to the output terminal of the selector circuit 2 connected to 3-m.

By performing this control, on the write side of the memory cells 3-1 to 3-m, every time n bits of the input signal 101 are input, only the information bits of the n bits are stored in the memory cells 3-1 to 3-. It is written in m in order.

The reading of the information bits from the memory cells 3-1 to 3-m is performed at the clock reproduced by the voltage controlled oscillator (VCO) 8, that is, at the same clock as the bit rate of the information signal.

The read address counter 9 operates with the clock from the voltage controlled oscillator 8, and its output is input to the selector circuit 4. Although the outputs of all the memory cells 3-1 to 3-m are connected to the selector circuit 4, the contents of the memory cells 3-1 to 3-m are read from the selector circuit 4 by the signal from the read address counter 9. Output signal 1 in order
Output as 03.

The oscillation frequency control of the voltage controlled oscillator 8 is PL
The phase comparison circuit 6 has an oscillation frequency of L and the high-frequency jitter component is removed by the low-pass filter 7.
Controlled by the output of.

The phase comparison circuit 6 has a phase difference between the write timing from the write address counter 5 for a specific memory cell (for example, the memory cell 3-1) in the memory and the read timing from the read address counter 9 for the memory cell. Generates a voltage proportional to. The phase comparison circuit 6 can be easily realized by an exclusive OR circuit or the like.

Therefore, the read address counter 9 has the voltage controlled oscillator 8 controlled by the output of the phase comparison circuit 6.
Memory cells 3-1 to 3-3-
The write phase to m and the read phase from the memory cells 3-1 to 3-m are always kept in a constant phase relationship.

As a result, the output signal 103 output from the selector circuit 4 is only the information bits in the input signal 101, and the jitter caused by removing other bits such as overhead bits and stuff bits is also reduced.

Thus, before writing only the information bits in the input signal 101 to the memory cells 3-1 to 3-m, the input signal 101 is serial-parallel converted to 1: n by the serial-parallel conversion circuit 1. The subsequent processing can be reduced to 1 / n.

Therefore, a large-scale LSI using a CMOS process or the like can be used for the elements constituting the memory circuit, and the circuit can be downsized and the power consumption can be reduced.

[0032]

As described above, according to the present invention, the input signal including the information bit to be taken out is serial-parallel converted to 1 to n (n is a positive integer), and the serial-parallel converted signal is converted into
By distributing to m memory cells (m is a multiple of n) based on a write control signal indicating an information bit to be taken out, a large-scale LSI using a CMOS process or the like can be used as an element forming a memory circuit. You can
There is an effect that the circuit can be downsized and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional reception memory circuit.

[Explanation of symbols]

 1 Serial-parallel conversion circuit 2, 4 Selector circuit 3-1 to 3-m Memory cell 5 Write address counter 9 Read address counter

Claims (2)

[Claims] 1. A receiving memory circuit for extracting the information bits from an input signal based on a write control signal indicating an information bit to be extracted, wherein the input signal is serial-parallel converted to 1: n (n is a positive integer). Converting means, m memory cells (m is a multiple of n) for storing the input signal, and distributing means for distributing the output of the converting means to the m memory cells based on the write control signal. A receiving memory circuit including :. 2. The receiving device according to claim 1, wherein the distributing means has n output terminals, and each of the output terminals is connected to m / n memory cells. Memory circuit.