JPH0787473B2 - Demodulator for differential phase modulation communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is directed to differential phase modulation (Differential Phase-Shif).
t Keying, hereinafter referred to as DSPK) communication system demodulator.

[Conventional technology]

A conventional demodulator using the DSPK communication system has a configuration shown in FIG. This is shown in "Modern Digital Communication Method" published by Ohmsha, co-authored by Hiroshi Miyagawa and Takuya Koizumi. In the figure, 1 is a demodulator input terminal, 2 is a delay device, 3 is a delay output terminal, 4 is a multiplier, 5 is an output terminal of the multiplier, and 6 is a bit determiner.

FIG. 6 shows the signal waveforms of the respective parts in FIG. 5 with the reference numerals of the respective parts.

Next, the operation will be described. The input signal waveform of the demodulator having the information sent by the DPSK communication system (FIG. 6) is delayed by the delay device 2 and becomes a delayed waveform (FIG. 6). This delay waveform is calculated by the multiplier 4 as the input signal waveform shown in FIG. 6 and becomes the input waveform of the bit decision unit 6 shown in FIG. This input waveform is subjected to bit determination by the bit determining device 6.
The delay time in the delay device 2 in the conventional DPSK communication system is demodulated as a bit period T. Further, in the bit judging device 6, the input waveform of the judging device 6 shown in FIG. 6 is integrated based on the clock of the bit period T, and the judgment is made by passing through the slicer. For example, if the integration result is negative, it means that the phase difference between the bits is 180 °, and if it is positive, the phase difference between the bits is 0 °. In the DPSK communication system, for example, when the phase difference between bits is 180 °, it is positioned as “1” of the data code, and when the phase difference is 0 °, it is associated with “0” to perform modulation. In this case, it is determined that the digital code "1" is transmitted when the integration result in the bit determiner 6 becomes negative, and the digital code "0" is transmitted when the integration result becomes positive.

[Problems to be Solved by the Invention]

In the conventional demodulator as described above, when the SN ratio of the received signal is poor, the probability of correctly recognizing the signal is also poor.

Therefore, an object of the present invention is to obtain a demodulator that accurately detects information even for a received signal with a poorer SN ratio, in order to improve the above problems.

[Means for Solving the Problems]

The demodulator of the present invention relates to a demodulator that performs bit determination after multiplying an input signal having information transmitted by the DPSK communication system and a delayed signal of this input signal. A plurality of combination circuits of are provided in parallel, and are configured to be input to the bit determination circuit to perform bit determination through an adder that adds each output of the multiplier,
The delay time of each delay device is set in order to emphasize the input carrier wave component of the demodulator included in the output signal of the adder.

Further, another type of demodulator of the present invention inputs another same number of combination circuits each having a predetermined delay time to a plurality of combination circuits of delay devices and multipliers. It is characterized in that it is provided in parallel with the signal and each multiplication output of the other combination circuit is input to an adder common to all of the combination circuits via respective sign inverters.

[Work]

Since the demodulator according to the present invention uses a plurality of combination circuits having different delay amounts and adds the outputs thereof to emphasize the signal component of the input signal, the SN ratio of the received signal can be increased.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 2a and 2b are delay circuits, 4a and 4b are multipliers, 8 is an adder, and 6 is a bit discriminator. Reference numeral 1 is an input terminal of the demodulator, 7a and 7b are output terminals of the multipliers 4a and 4b, and 9 is an output terminal of the adder 8. FIG. 2 shows the signal waveforms of the respective parts in FIG. 1 by the reference numerals of the respective parts.

Next, the operation of the demodulator will be described with reference to the embodiment shown in FIG. 1 in the case where the DPSK communication method in which one cycle of the carrier wave represents one bit of the modulated wave is transmitted. Demodulator Received Waveform FIG. 2 shows that after being delayed by the delay units 2a and 2b respectively, the multipliers 4a and 4b are delayed.
At the demodulator received waveform itself. Now, if the bit period T of the modulated wave by the DPSK communication system is selected as 4τ, 2τ becomes equal to the carrier wave period. When the delay time in the delay device 2a is set to 2τ and the delay time in the delay device 2b is determined to 4τ, the input waveforms 7a and 7b of the adder 8 shown in FIGS. The input waveforms 2a and 2b in FIG. 2 are added by the adder 8 to form the input waveform 2 in FIG. This input waveform of FIG. 2 is subjected to bit judgment by the judging device 6. The bit determination can be performed, for example, by integrating the input waveform shown in FIG. 2 on the time axis with a clock synchronized with the bit. As can be seen here, the carrier component representing the information of the input signal of the demodulator is emphasized by being added by the adder 8.

FIG. 3 shows another embodiment of the present invention. The circuit configuration of this figure is the same as that of the circuit of FIG. 1 but with a pair of delay devices 2c and 2d.
Also, a combination circuit including the multipliers 4c and 4d is provided, and sign inverters 10a and 10b for inverting the outputs of the combination circuits are provided.
Here, the delay time in the delay device 2c is τ, and the delay time in the delay device 2d is 3τ. Reception waveform of demodulator 4
When the waveform of the result of multiplication with is added to the sign inverters 10a and 10b to invert the sign, the result is obtained as the input waveform of the adder 8 in FIG.
In addition to b, Fig. 4c and 7d are obtained. These input waveforms 7a, 7b, 7c, 7d shown in FIG. 4 are added by the adder 8 to obtain the input waveform of the judging device 6 shown in FIG. This input waveform is shown in FIG.
Is the input waveform of the decision unit in the embodiment of FIG.
Compared to, the SN ratio can be further improved.

In the embodiment of the present invention shown in FIGS. 1 and 3, the operation of the demodulator of the DPSK communication system which represents one bit in two cycles of the carrier wave has been described. Further, even when the carrier wave period per bit increases or decreases, a demodulator having the same effect as the demodulator described here can be realized by adjusting the number of delay devices and multipliers.

Although the delay time in the delay device has been described as an integral multiple of 1/2 cycle of the carrier wave in the above-described embodiment, the range of the delay time τ ₀ is expressed by the bit cycle T, and the same holds true for 0 <τ ₀ <T. The effect is obtained.

〔The invention's effect〕

As described above, according to the present invention, since the carrier wave component of the input waveform of the demodulator is emphasized and the SN ratio of the input waveform of the determiner is increased, the recognition rate of the transmitted signal becomes high. This is particularly effective when the transmission frequency is low and the SN ratio of the received signal is poor.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a demodulator for a differential phase modulation communication system according to an embodiment of the present invention, FIG. 2 is a time chart showing signal waveforms of respective parts in FIG. 1, and FIG. 4 is a block circuit diagram of another embodiment, FIG. 4 is a time chart of signal waveforms of respective parts in FIG. 3, FIG. 5 is a block circuit diagram of a conventional demodulator, and FIG. 6 is time of signal waveforms of respective parts in FIG. It is a chart figure. 2a to 2d ... delay device, 4a to 4d ... multiplier, 6 ... decision device,
10a to 10b ... Sign invertor, 8 ... Adder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akio Morimori 8-1-1 Tsukaguchihonmachi, Amagasaki-shi, Hyogo Sanryo Electric Co., Ltd. Industrial Systems Research Institute (56) Reference Japanese Patent Laid-Open No. 2-149048 A) JP-A-63-153942 (JP, A)

Claims (2)

[Claims] 1. A difference for performing bit determination after multiplying an input signal having information transmitted by a differential phase modulation communication system in which a bit period of a modulation wave is an integer multiple of carrier wave synchronization and a delayed signal of the input signal. In a dynamic phase modulation communication system demodulator, a first combination circuit of a delay device and a multiplier is provided in parallel with respect to an input signal, and bit determination is performed through an adder that adds each output of the multiplier. Therefore, the demodulator for differential phase modulation communication system is characterized in that the delay time of the delay circuit of the first combination circuit is set to an integer multiple of the cycle of the carrier wave. 2. A second combination circuit of a delay device and a multiplier is further provided in parallel with a first combination circuit of the delay device and the multiplier, the second combination circuit including a delay device and a multiplier, and the second combination circuit is provided. Each multiplication output signal of is input to an adder common to all of the first and second combinational circuits via respective sign inverters, and the delay time of the delayer of the second combinational circuit is set to the cycle of the carrier wave. The demodulator for differential phase modulation communication system according to claim 1, wherein the value is an integral multiple of 1/2.