JPH0789127B2 - Voltage measurement circuit - Google Patents
Voltage measurement circuitInfo
- Publication number
- JPH0789127B2 JPH0789127B2 JP27810288A JP27810288A JPH0789127B2 JP H0789127 B2 JPH0789127 B2 JP H0789127B2 JP 27810288 A JP27810288 A JP 27810288A JP 27810288 A JP27810288 A JP 27810288A JP H0789127 B2 JPH0789127 B2 JP H0789127B2
- Authority
- JP
- Japan
- Prior art keywords
- current limiting
- input terminal
- voltage
- operational amplifier
- limiting resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は、電圧測定回路に関するものであり、詳しく
は、高電圧測定時におけるコモンモードノイズの除去に
関するものである。Description: TECHNICAL FIELD The present invention relates to a voltage measurement circuit, and more particularly to removal of common mode noise during high voltage measurement.
＜従来の技術＞ 一般に、商用電源電圧などの比較的高い電圧を測定する
のにあたっては、機器の絶縁劣化などの故障によって大
電流が流れることを防止するために、電圧測定回路に電
流制限抵抗を接続することが行われている。<Prior Art> Generally, when measuring a relatively high voltage such as a commercial power supply voltage, a current limiting resistor is provided in a voltage measuring circuit in order to prevent a large current from flowing due to a failure such as insulation deterioration of equipment. Connecting is done.
第２図は、従来のこのような回路の一例を示す回路図で
ある。図において、測定電圧EMの一方の入力端子T1は第
１の電流制限抵抗R1を介して第１の演算増幅器A1の非反
転入力端子に接続され、測定電圧EMの他方の入力端子T2
は第２の電流制限抵抗R2を介して共通電位点に接続され
ている。ECはコモンモード電圧であり、測定電圧EMの他
方の入力端子T2と大地間に接続されている。Ｃは共通電
位点と大地間の浮遊容量である。FIG. 2 is a circuit diagram showing an example of such a conventional circuit. In the figure, an input terminal T 1 of the measurement voltage E M is connected to a first non-inverting input terminal of the operational amplifier A 1 via a first current limiting resistor R 1, the other input of the measuring voltage E M Terminal T 2
Is connected to the common potential point via the second current limiting resistor R 2 . E C is a common mode voltage, which is connected between the other input terminal T 2 of the measured voltage E M and the ground. C is a stray capacitance between the common potential point and the ground.
このような構成において、電流制限抵抗R1,R2は、第１
の演算増幅器A1に大電流が流入することを防止する。In such a configuration, the current limiting resistors R 1 and R 2 are
A large current is prevented from flowing into the operational amplifier A 1 of.
＜発明が解決しようとする課題＞ しかし、このような従来の構成によれば、正常状態にお
いて、コモンモード電圧ECから入力端子T2→電流制限抵
抗R2→浮遊容量Ｃの経路を通って大地にコモンモード電
流ICが流れる。この結果、電流制限抵抗R2において、 VN＝R2・IC で表わされる電圧降下VNが発生し、第１の演算増幅器A1
の出力電圧にノーマルモードノイズとして悪影響を及ぼ
し、ノイズ特性を劣化させることになる。<Problems to be Solved by the Invention> However, according to such a conventional configuration, in a normal state, the common mode voltage E C passes through the path of the input terminal T 2 → current limiting resistance R 2 → stray capacitance C. Common mode current I C flows to the ground. As a result, a voltage drop V N represented by V N = R 2 · I C occurs in the current limiting resistor R 2 , and the first operational amplifier A 1
This adversely affects the output voltage of the normal mode noise and deteriorates the noise characteristics.
本発明は、このような点に着目したものであり、その目
的は、比較的簡単な構成で、コモンモード電流ICに起因
するノーマルモードノイズが除去できる電圧測定回路を
提供することにある。The present invention focuses on such a point, and an object thereof is to provide a voltage measurement circuit which has a relatively simple configuration and which can remove normal mode noise caused by the common mode current I C.
＜課題を解決するための手段＞ 本発明の電圧測定回路は、 測定電圧の一方の入力端子は第１の電流制限抵抗を介し
て第１の演算増幅器の非反転入力端子に接続され、 測定電圧の他方の入力端子は第２の電流制限抵抗を介し
て共通電位点に接続され、 第２の演算増幅器の非反転入力端子は第２の電流制限抵
抗の共通電位点側に接続され、 第２の演算増幅器の出力端子は第３の電流制限抵抗を介
して第２の電流制限抵抗の測定電圧の他方の入力端子側
に接続され、 第２の演算増幅器の反転入力端子は第４の電流制限抵抗
を介して第２の電流制限抵抗の測定電圧の他方も入力端
子間に接続されたことを特徴とする。<Means for Solving the Problems> In the voltage measuring circuit of the present invention, one input terminal of the measurement voltage is connected to the non-inverting input terminal of the first operational amplifier via the first current limiting resistor, The other input terminal of is connected to the common potential point via the second current limiting resistor, and the non-inverting input terminal of the second operational amplifier is connected to the common potential point side of the second current limiting resistor. The output terminal of the operational amplifier is connected to the other input terminal side of the measured voltage of the second current limiting resistor via the third current limiting resistor, and the inverting input terminal of the second operational amplifier is connected to the fourth current limiting resistor. The other of the measured voltages of the second current limiting resistor is also connected between the input terminals via the resistor.
＜作用＞ 本発明における第２の電流制限抵抗の両端の電位は、第
２の演算増幅器のフィードバック効果により等しい値に
保たれることになり、第１の演算増幅器の出力電圧に対
するノーマルモードノイズの影響を防止できる。<Operation> The potentials across the second current limiting resistor in the present invention are kept at an equal value due to the feedback effect of the second operational amplifier, and the normal mode noise of the output voltage of the first operational amplifier is reduced. The impact can be prevented.
＜実施例＞ 以下、図面を用いて本発明の実施例を詳細に説明する。<Example> Hereinafter, an example of the present invention is described in detail using a drawing.
第１図は本発明の一実施例を示す回路図であり、第２図
と同一部分には同一符号を付けている。図において、A2
は第２の演算増幅器であり、その非反転入力端子は第２
の電流制限抵抗R2の共通電位点側に接続され、出力端子
は第３の電流制限抵抗R3を介して第２の電流制限抵抗R2
の測定電圧EMの他方の入力端子T2側に接続され、反転入
力端子は第４の電流制限抵抗R4を介して第２の電流制限
抵抗R2の測定電圧EMの他方の入力端子T2側に接続されて
いる。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. In the figure, A 2
Is a second operational amplifier whose non-inverting input terminal is the second
Is connected to the common potential point side of the current limiting resistor R 2 of, and the output terminal is connected to the second current limiting resistor R 2 via the third current limiting resistor R 3.
Connected to the other input terminal T 2 side of the measured voltage E M of the inverting input terminal via the fourth current limiting resistor R 4 and the other input terminal of the measured voltage E M of the second current limiting resistor R 2 Connected to the T 2 side.
このように構成された回路の動作を説明する。The operation of the circuit thus configured will be described.
第２図の演算増幅器A2のループゲインをＧ、第２の演算
増幅器A2の出力電圧をE0、第２の電流制限抵抗R2の共通
電位点側の電位をvB＝０、第２の電流制限抵抗R2の測定
電圧EMの他方の入力端子T2側の電位をvAとすると、 になり、 E0＝Ｇ・VA になる。従って、 になる。ここで、Ｇは無限大とすると、vA＝０になり、
コモンモード電圧ECの影響はなくなる。The loop gain of the operational amplifier A 2 in FIG. 2 is G, the output voltage of the second operational amplifier A 2 is E 0 , the potential on the common potential point side of the second current limiting resistor R 2 is v B = 0, If the potential on the other input terminal T 2 side of the measured voltage E M of the current limiting resistor R 2 of 2 is v A , And E 0 = G · V A. Therefore, become. Here, if G is infinite, v A = 0,
The influence of the common mode voltage E C disappears.
このように構成することにより、第２の電流制限抵抗R2
の両端の電位は第２の演算増幅器A2のフィードバック効
果により等しい電位に保たれることになり、従来のよう
にコモンモード電流ICが流れることによってノーマルノ
イズ電圧が発生することはなく、第１の演算増幅器A1の
ノイズ特性を大幅に改善できる。With this configuration, the second current limiting resistor R 2
The potentials at both ends of the are maintained at the same potential due to the feedback effect of the second operational amplifier A 2 , and the normal noise voltage is not generated by the common mode current I C flowing as in the conventional case. The noise characteristic of the operational amplifier A 1 can be greatly improved.
＜発明の効果＞ 以上説明したように、本発明によれば、比較的簡単な構
成で、コモンモード電流に起因するノーマルモードノイ
ズが除去できる電圧測定回路が実現でき、実用上の効果
は大きい。<Effects of the Invention> As described above, according to the present invention, it is possible to realize a voltage measurement circuit capable of removing normal mode noise caused by a common mode current with a relatively simple configuration, and a great practical effect.
第１図は本発明の一実施例を示す回路図、第２図は従来
の回路の一例を示す回路図である。 T1,T2……入力端子、A1,A2……演算増幅器、R1〜R4……
電流制限抵抗。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional circuit. T 1 , T 2 ...... Input terminal, A 1 , A 2 ...... Operational amplifier, R 1 to R 4 ……
Current limiting resistor.
Claims (1)
限抵抗を介して第１の演算増幅器の非反転入力端子に接
続され、 測定電圧の他方の入力端子は第２の電流制限抵抗を介し
て共通電位点に接続され、 第２の演算増幅器の非反転入力端子は第２の電流制限抵
抗の共通電位点側に接続され、 第２の演算増幅器の出力端子は第３の電流制限抵抗を介
して第２の電流制限抵抗の測定電圧の他方の入力端子側
に接続され、 第２の演算増幅器の反転入力端子は第４の電流制限抵抗
を介して第２の電流制限抵抗の測定電圧の他方も入力端
子間に接続されたことを特徴とする電圧測定回路。1. An input terminal for measuring voltage is connected to a non-inverting input terminal of a first operational amplifier via a first current limiting resistor, and another input terminal for measuring voltage is a second current limiting resistor. Is connected to the common potential point via the non-inverting input terminal of the second operational amplifier is connected to the common potential point side of the second current limiting resistor, and the output terminal of the second operational amplifier is the third current limiting terminal. The second inverting input terminal of the second operational amplifier, which is connected to the other input terminal side of the measurement voltage of the second current limiting resistance via the resistor, measures the second current limiting resistance via the fourth current limiting resistance. A voltage measurement circuit characterized in that the other of the voltages is also connected between the input terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27810288A JPH0789127B2 (en) | 1988-11-02 | 1988-11-02 | Voltage measurement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27810288A JPH0789127B2 (en) | 1988-11-02 | 1988-11-02 | Voltage measurement circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02124471A JPH02124471A (en) | 1990-05-11 |
| JPH0789127B2 true JPH0789127B2 (en) | 1995-09-27 |
Family
ID=17592659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27810288A Expired - Lifetime JPH0789127B2 (en) | 1988-11-02 | 1988-11-02 | Voltage measurement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0789127B2 (en) |
-
1988
- 1988-11-02 JP JP27810288A patent/JPH0789127B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02124471A (en) | 1990-05-11 |
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