JPH0789143B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a scan path composed of a plurality of registers.

[Conventional technology]

Conventionally, a semiconductor integrated circuit device of this type has a scan path shown in FIG. FIG. 4 shows registers 11,12,
.. 1n are connected in series so that the shift inputs and outputs of all registers are in series so that they enter the scan path, shift data input is IN, shift data output is OUT, and shift control is SFT. Normally, you do not set or read data to or from all the registers.
In case of, the sum of the number of bits of register 11 and the number of bits of register 12 is required as the number of shift clocks.
When reading 12 data, the number of shift clocks is the total number of bits of each of the registers 12, ..., 1n.

Generally speaking, the maximum number of shift clocks, which is the sum of the number of bits of the maximum registers 11 to 1n, is always required when data is read and written once.

[Problems to be Solved by the Invention]

In the above-described semiconductor integrated circuit device having the scan path, even if there is a register that does not set or read data because all the registers are in series, the necessary register information is not transferred unless the data is transferred by the shift clock. Since it cannot be read or written, the number of shift clocks is increased. Generally, the scan path is often introduced to test the semiconductor integrated circuit device, and the wasteful increase in the number of shift clocks has the drawback of increasing the test time and increasing the test pattern amount. Was there.

[Means for Solving the Problems]

A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a scan path in which a plurality of registers are connected in series, and at least some of the plurality of registers are provided with an input signal to the register. A path for directly outputting without passing and a means for selecting a signal output through the register and a signal directly outputting through the path are provided, and the selecting means selects the signal directly output through the path. A means for stopping the supply of the shift clock to the register is provided when the selection signal is applied.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. Register 11
The input of is the shift input IN, and its output is connected to the selection circuit 21. The other input of the selection circuit 21 is the shift input IN, and the output of the selection circuit 21 is serially connected to the registers 12 to 1n and output to the shift output OUT. The shift control 1 (SFT1) is a control line for whether or not the register 11 is incorporated in the scan path, and the AND circuit 41 with the shift control (SFT) controls the shift of the register 11. The shift control 1 (SFT1) also serves as selection information for the selection circuit 21.

If the register for setting data is 12, the register 11 is not used. Therefore, if the selection circuit 21 is set so that the shift input IN is input to the register 12 by the shift control 1 (SFT1), the number of shift clocks is Only the number of bits will suffice.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

The scan path bypass by the shift control 1 (SFT1) is configured in the register 11 of FIG. 1 except that the scan path bypass by the shift control 2 (SFT2) is configured in the register 12 in FIG. It is the same.

In this example, when reading the contents of register 11 or register
If the register 12 is not used when setting data to 13 to 1n, the shift clock number can be reduced by the number of bits of the register 12 by bypassing the register 12 by the shift control 2 (SFT2).

As can be understood from this example, the same applies even if any of the registers 11, 12, ..., 1n is provided with a bypass for the scan path.

FIG. 3 is a circuit diagram of still another embodiment of the present invention.

FIG. 3 shows an example of a circuit of a type in which a plurality of registers can be bypassed, and the number of shift clocks can be reduced by the maximum total number of bits of the bypassed registers.

〔The invention's effect〕

As described above, in the present invention, the logical product circuit (41, 41) of the shift (SFT) and the shift control (SFT1, 2, ...) Is added to the unnecessary register of the plurality of registers forming the scan path. 42, ...) and the clock is not always supplied. Therefore, it is possible to set data in any register with the minimum number of clocks, which reduces wasteful test time, reduces test cost, and reduces the amount of test patterns. Since the clock is not supplied to, there is an effect that an increase in power consumption can be prevented.

[Brief description of drawings]

1, 2 and 3 are circuit diagrams of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit device. IN: shift input data, OUT: shift output data, S
FT ... Shift control, SFT1 ... Shift control 1, SFT2 ... Shift control 2, 11-1n ... Register, 41-42 ... AND circuit, 21,22 ... Selection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a scan path in which a plurality of registers are connected in series, at least some of the plurality of registers do not pass an input signal to the registers through the registers. A selection for providing a direct output path and a means for selecting a signal output through a register and a signal directly output through the path, and the selection means selecting the signal directly output through the path A semiconductor integrated circuit, characterized in that supply of a shift clock to the register is stopped when a signal is applied.