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JPH0789553B2 - Method for manufacturing bump electrode type semiconductor device - Google Patents
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JPH0789553B2 - Method for manufacturing bump electrode type semiconductor device - Google Patents

Method for manufacturing bump electrode type semiconductor device

Info

Publication number
JPH0789553B2
JPH0789553B2 JP60051705A JP5170585A JPH0789553B2 JP H0789553 B2 JPH0789553 B2 JP H0789553B2 JP 60051705 A JP60051705 A JP 60051705A JP 5170585 A JP5170585 A JP 5170585A JP H0789553 B2 JPH0789553 B2 JP H0789553B2
Authority
JP
Japan
Prior art keywords
substrate
bump electrode
bump
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60051705A
Other languages
Japanese (ja)
Other versions
JPS61210656A (en
Inventor
正一 井上
進 君島
勉 上本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60051705A priority Critical patent/JPH0789553B2/en
Publication of JPS61210656A publication Critical patent/JPS61210656A/en
Publication of JPH0789553B2 publication Critical patent/JPH0789553B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07231Techniques
    • H10W72/07236Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体基板にオーミック接続する複数の金属
電極が形成され、更にその上に低融点金属からなるバン
プ電極が形成される半導体装置の製造方法に関する。
Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to the manufacture of a semiconductor device in which a plurality of metal electrodes for ohmic connection are formed on a semiconductor substrate, and bump electrodes made of a low melting point metal are formed on the metal electrodes. Regarding the method.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

CCDセンサは入射光学像を二次元的に多数配列された光
検知素子で受け、これを時系列の電気信号に変換して取
出す機能を備えた集積化センサとしてよく知られてい
る。従来は二次元の物理量を取出すセンサは、このよう
な光センサに限られていた。最近、メカトロニクス技術
の発達にともなって例えば、圧力を二次元的に検知して
機械に圧覚や触覚の機能を持たせる要求が増えている。
この様な圧力センサの一例として、半導体のピエゾ抵抗
素子が利用される。例えば、Si基板に拡散抵抗素子を二
次元的に配列形成すれば、これに外部から応力が加わっ
た時その時の抵抗値が変化して信号を得ることができ
る。このような圧力センサをCCDと一体化すれば、応力
分布を検知してその電気信号処理まで行う集積化センサ
が得られる。この場合、圧力センサ基板とCCD基板を一
体化するには、対応する電極を突き合わせて接続する、
いわゆるバンプ電極構造が用いられる。
The CCD sensor is well known as an integrated sensor having a function of receiving an incident optical image by a plurality of two-dimensionally arrayed photodetecting elements and converting it into a time-series electric signal to take it out. Conventionally, a sensor for extracting a two-dimensional physical quantity has been limited to such an optical sensor. Recently, with the development of mechatronics technology, for example, there is an increasing demand for two-dimensionally detecting pressure to give a machine a function of pressure sense or tactile sense.
A semiconductor piezoresistive element is used as an example of such a pressure sensor. For example, if diffusion resistance elements are two-dimensionally arranged and formed on a Si substrate, when external stress is applied thereto, the resistance value at that time changes and a signal can be obtained. If such a pressure sensor is integrated with the CCD, an integrated sensor that detects the stress distribution and processes the electric signal can be obtained. In this case, to integrate the pressure sensor board and the CCD board, the corresponding electrodes are butted and connected.
A so-called bump electrode structure is used.

第2図はこの様な用途に供される従来のバンプ電極型CC
Dの製造工程例である。(a)に示すように、CCD基板11
の表面には複数の信号入力部12(12a,12b,…)を有し、
それぞれにバンプ電極を形成すべきコンタクトホール電
極13(13a,13b,…)が形成されている。14はSiO2膜等の
絶縁膜である。CCD基板11にはまた、図では省略した
が、多数の転送ゲート電極が配列形成されており、表面
の凹凸を平坦化するために通常採用されているポリイミ
ド膜15が形成されている。コンタクトホール電極13は例
えばAl膜である。その後(b)に示すように、全面にTi
膜161、Cu膜162を順次蒸着した積層金属膜16を形成す
る。Ti膜161はバリアメタルであり、Cu膜162はメッキ様
電極である。次に(c)に示すように、バンプ電極を立
てる位置にフォトレジスト17をパターン形成し、選択メ
ッキ法によりCu層18(18a,18b,…)、続いてIn層19(19
a,b,…)を形成する。この後(d)に示すように、フォ
トレジスト17を除去し、次いでIn層19をマスクとしてCu
膜162,Ti膜161を順次エッチング除去してInバンプ電極
を形成する。
Fig. 2 shows the conventional bump electrode type CC used for such applications.
It is an example of a manufacturing process of D. As shown in (a), the CCD substrate 11
Has a plurality of signal input sections 12 (12a, 12b, ...) On its surface,
A contact hole electrode 13 (13a, 13b, ...) For forming a bump electrode is formed on each of them. Reference numeral 14 is an insulating film such as a SiO 2 film. Although not shown in the drawing, a large number of transfer gate electrodes are arrayed and formed on the CCD substrate 11, and a polyimide film 15 which is usually adopted to flatten the surface unevenness is formed. The contact hole electrode 13 is, for example, an Al film. Then, as shown in (b), Ti
A laminated metal film 16 is formed by sequentially depositing a film 16 1 and a Cu film 16 2 . The Ti film 16 1 is a barrier metal and the Cu film 16 2 is a plating-like electrode. Next, as shown in (c), a photoresist 17 is patterned at a position where the bump electrode is to be formed, and a Cu layer 18 (18a, 18b, ...) Is formed by selective plating, followed by an In layer 19 (19).
a, b, ...) are formed. After this, as shown in (d), the photoresist 17 is removed, and then the In layer 19 is used as a mask for Cu.
The film 16 2 and the Ti film 16 1 are sequentially removed by etching to form an In bump electrode.

この様な従来法においては、第2図(d)に示すよう
に、選択メッキ法により形成されるCu層18及びIn層19は
基板の中心部に比べて周辺部で高くなる、というメッキ
厚のバラツキが生じる。これは、メッキ電流を一定値に
保持しても、電気メッキ特有の現象として周辺部で電流
密度が大きくなる結果である。このようなメッキ厚のバ
ラツキがあるため、例えばこのCCD基板を圧力センサ基
板と対応する端子電極を突き合わせて一体化した時に基
板中心部のIn電極が接続されない、という欠点があっ
た。
In such a conventional method, as shown in FIG. 2D, the Cu layer 18 and the In layer 19 formed by the selective plating method are higher in the peripheral portion than in the central portion of the substrate. Variation occurs. This is a result of the current density increasing in the peripheral portion as a phenomenon peculiar to electroplating even if the plating current is held at a constant value. Due to such variation in plating thickness, there is a drawback that the In electrode at the center of the substrate is not connected when the CCD substrate and the corresponding terminal electrode corresponding to the pressure sensor substrate are abutted and integrated, for example.

〔発明の目的〕[Object of the Invention]

本発明は上記した点に鑑みなされたもので、複数のバン
プ電極の高さを均一化して対応する基板の端子電極との
突き合わせ接続を確実に行ない得るようにしたバンプ電
極型半導体装置の製造方法を提供することを目的とす
る。
The present invention has been made in view of the above point, and a method for manufacturing a bump electrode type semiconductor device, which makes it possible to make the butt connection with the terminal electrodes of the corresponding substrate uniform by making the heights of the plurality of bump electrodes uniform. The purpose is to provide.

〔発明の概要〕[Outline of Invention]

本発明のバンプ電極型半導体装置の製造方法は、半導体
基板に複数のバンプ電極形成予定領域でオーミック接触
する下地金属膜を形成する工程と、前記下地金属膜上に
選択メッキ法により低融点金属からなる複数のバンプ電
極を形成する工程と、前記バンプ電極の形成された面に
平坦基板を所定の圧力・温度で貼り合わせバンプ電極表
面を融解させた後この平坦基板を分離し、表面が先細り
のバンプ電極を形成する工程とを備えたことを特徴とす
る。
A method of manufacturing a bump electrode type semiconductor device according to the present invention comprises a step of forming a base metal film in ohmic contact with a plurality of regions for forming bump electrodes on a semiconductor substrate, and a low melting point metal on the base metal film by a selective plating method. A step of forming a plurality of bump electrodes, and a flat substrate is attached to the surface on which the bump electrodes are formed at a predetermined pressure and temperature to melt the bump electrode surface, and then the flat substrate is separated to make the surface tapered. And a step of forming bump electrodes.

〔発明の効果〕〔The invention's effect〕

本発明によれば、電気メッキ法で避けられないメッキ厚
のばらつきによるバンプ電極の高さの不均一が解消され
る。従ってこのバンプ電極が形成された例えばCCD基板
を、他の半導体素子基板と対応する端子電極をつき合わ
せて接続して一体化する場合に信頼性の高い接続を行う
ことができる。
According to the present invention, the unevenness of the bump electrode height due to the variation of the plating thickness, which is unavoidable in the electroplating method, is eliminated. Therefore, for example, when a CCD substrate on which the bump electrodes are formed is integrated by associating and connecting another semiconductor element substrate with corresponding terminal electrodes, highly reliable connection can be performed.

さらに、本発明では、表面が先細りのバンプ電極を形成
しているので、以下のような効果が得られる。
Further, in the present invention, since the bump electrode having a tapered surface is formed, the following effects can be obtained.

すなわち、バンプ電極が形成された半導体基板(第1の
半導素子体基板)と、端子電極が形成された他の半導体
素子基板(第2の半導体素子基板)とを接続する際、上
記バンプ電極の表面が先細りであるので、第1の半導体
素子基板と第2の半導体素子基板とを弱い力で接続でき
る。
That is, when connecting a semiconductor substrate having bump electrodes formed thereon (first semiconductor element substrate) and another semiconductor element substrate having terminal electrodes formed thereon (second semiconductor element substrate), the bump electrodes Since the surface of the element is tapered, the first semiconductor element substrate and the second semiconductor element substrate can be connected with a weak force.

したがって、第1の半導体素子基板、第2の半導体素子
基板に機械的に弱い素子構造等があっても、信頼性を損
なわずに、上記2つの半導体素子基板を一体化できる。
Therefore, even if the first semiconductor element substrate and the second semiconductor element substrate have mechanically weak element structures and the like, the two semiconductor element substrates can be integrated without impairing reliability.

このとき、バンプ電極の高さにたとえばらつきがあって
も、このばらつきの範囲がバンプ電極表面の細い部分の
高さ以内であれば、上記ばらつきは、第1、第2の半導
体素子基板を弱い力で接続する際に消滅してしまうの
で、信頼性の高い接続を行なうことができる。
At this time, even if there are variations in the height of the bump electrode, if the range of this variation is within the height of the thin portion of the surface of the bump electrode, the above variation makes the first and second semiconductor element substrates weak. Since it disappears when connecting by force, a highly reliable connection can be performed.

〔発明の実施例〕Example of Invention

以下本発明の一実施例を説明する。 An embodiment of the present invention will be described below.

第1図(a)のバンプ電極型CCDの製造工程は、先に説
明した第2図(a)〜(d)と同じである。即ちCCD基
板21の表面には信号入力部22(22a,22b,…)が形成さ
れ、この上に信号入力部22に開口を持つ絶縁膜23,ポリ
イミド膜24が形成され、各信号入力部22にはAl膜からな
るコンタクト電極が形成されている。この後全面にTi膜
261,Cu膜262を順次蒸着した下地金属膜26が形成され
る。Ti膜261はバリアメタルであり、Cu膜262はメッキ用
電極膜である。この後フォトレジストパターンをマスク
する選択メッキ法によりCu層27(27a,27b,…)、次いで
In層28(28a,28b,…)が形成される。Cu層27は例えば、
基板を硫酸銅浴のCuメッキ液中に浸し、室温にて下地金
属膜のCu膜262を電極として、最初逆メッキを数秒間行
って清浄化した後、正常なCuメッキを所定電流値で数十
分間行って形成する。これにより、数μm厚のCu層27が
形成される。またIn層28はこのCu層27が形成された基板
を例えば、ホウフッ化浴のInメッキ液に浸し、所定の電
流値で数十分間電気メッキを行うことにより数μmの厚
さに形成される。次にフォトレジストを除去し、Cu層27
にIn層28が積層されたバンプ電極をマスクとしてその直
下の下地金属膜を残してそれ以外の下地金属膜を弱酸系
エッチャントにより順次エッチング除去して行く。
The manufacturing process of the bump electrode type CCD of FIG. 1A is the same as that of FIGS. 2A to 2D described above. That is, a signal input portion 22 (22a, 22b, ...) Is formed on the surface of the CCD substrate 21, and an insulating film 23 having an opening in the signal input portion 22 and a polyimide film 24 are formed thereon, and each signal input portion 22 is formed. A contact electrode made of an Al film is formed on the. After this, Ti film is formed on the entire surface
A base metal film 26 is formed by sequentially depositing 26 1 and Cu film 26 2 . The Ti film 26 1 is a barrier metal and the Cu film 26 2 is a plating electrode film. Then, a Cu layer 27 (27a, 27b, ...) Is formed by a selective plating method that masks the photoresist pattern, and then
In layers 28 (28a, 28b, ...) Are formed. The Cu layer 27 is, for example,
Immersing the substrate in Cu plating solution of copper sulfate bath, a Cu film 26 2 of the base metal film as an electrode at room temperature, after cleaning by performing a few seconds the first reverse plating at a predetermined current value normal Cu plating It is formed after several tens of minutes. As a result, a Cu layer 27 having a thickness of several μm is formed. The In layer 28 is formed to have a thickness of several μm by immersing the substrate on which the Cu layer 27 is formed in, for example, an In plating solution in a borofluoride bath and performing electroplating at a predetermined current value for several tens of minutes. It The photoresist is then removed and the Cu layer 27
Using the bump electrode having the In layer 28 laminated thereon as a mask, the underlying metal film immediately below is left, and the other underlying metal films are sequentially removed by etching with a weak acid-based etchant.

このようにしてInバンプ電極を形成した後、図示してい
ないが、平行度の高い圧接装置を用いてCCD基板21を真
空チャックし、CCD基板21に対向して平坦基板として例
えばSi基板を真空チャックする。そして第1図(a)に
示すように、CCD基板21とSi基板29をフォーミングガス
雰囲気中で例えば140℃に加熱し、所定の圧力で数分間
圧接した後、例えば160℃程度に温度をあげて数分間保
持する。こうしてInパンプ電極表面を融解した後、CCD
基板21とSi基板29を分離する。これにより第1図(b)
に示すように、高さの揃ったInバンプ電極が形成され
る。
After forming the In bump electrodes in this way, although not shown, the CCD substrate 21 is vacuum-chucked by using a pressure welding device having a high degree of parallelism, and a flat substrate such as a Si substrate is vacuumed facing the CCD substrate 21. Chuck. Then, as shown in FIG. 1 (a), the CCD substrate 21 and the Si substrate 29 are heated to, for example, 140 ° C. in a forming gas atmosphere, pressed at a predetermined pressure for several minutes, and then heated to, for example, about 160 ° C. Hold for a few minutes. After melting the surface of the In-pump electrode in this way, the CCD
The substrate 21 and the Si substrate 29 are separated. As a result, FIG. 1 (b)
As shown in, the In bump electrodes with uniform height are formed.

以上のようにこの実施例によれば、Inバンプ電極形成後
その電極面に平坦基板を加熱圧接することにより、メッ
キ厚のばらつきがあってもバンプ電極の高さを均一なも
のとすることができる。この様なバンプ電極の高さを均
一にしたCCD基板を例えば圧力センサ基板と対応する端
子電極を突き合わせて一体化すれば、多数の端子電極の
接続が確実に行われ、電気信号処理までできる圧力セン
サを歩留りよく得ることができる。
As described above, according to this embodiment, by heating and pressing the flat substrate on the electrode surface after forming the In bump electrode, the height of the bump electrode can be made uniform even if the plating thickness varies. it can. If a CCD substrate with such bump electrode heights that are uniform in height is integrated by, for example, abutting the corresponding terminal electrodes on the pressure sensor substrate, a large number of terminal electrodes can be reliably connected and even pressure signal processing can be performed. The sensor can be obtained with high yield.

本発明は上記した実施例に限られるものではなく、その
趣旨を逸脱しない範囲で種々変形実施することができ
る。例えばバンプ電極面を圧接加熱する平坦基板はどの
ようなものであってもよい。
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. For example, any kind of flat substrate may be used for heating the bump electrode surface under pressure.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)(b)は本発明の一実施例のバンプ電極型
CCDの製造工程を説明するための図、第2図(a)〜
(d)は従来のバンプ電極形CCDの製造工程を説明する
ための図である。 21……CCD基板、22(22a,22b,…)……信号入力部、23
……絶縁膜、24……ポリイミド膜、25(25a,25b,…)…
…コンタクトホール電極、26……下地金属膜、261……T
i膜、262……Cu膜、27(27a,27b,…)……Cu層、28(28
a,28b,…)……In層(バンプ電極)、29……Si基板(平
坦基板)。
1 (a) and 1 (b) are bump electrode types according to one embodiment of the present invention.
FIG. 2A to FIG. 2A for explaining the CCD manufacturing process
(D) is a figure for demonstrating the manufacturing process of the conventional bump electrode type CCD. 21 …… CCD board, 22 (22a, 22b, ...) …… Signal input section, 23
…… Insulating film, 24 …… Polyimide film, 25 (25a, 25b,…)…
… Contact hole electrode, 26 …… Base metal film, 26 1 …… T
i film, 26 2・ ・ ・ Cu film, 27 (27a, 27b,…) …… Cu layer, 28 (28
a, 28b,…) …… In layer (bump electrode), 29 …… Si substrate (flat substrate).

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に複数のバンプ電極形成予定領
域でオーミック接触する下地金属膜を形成する工程と、
前記下地金属膜上に選択メッキ法により低融点金属から
なる複数のバンプ電極を形成する工程と、前記バンプ電
極の形成された面に平坦基板を所定の圧力・温度で貼り
合わせバンプ電極表面を融解させた後この平坦基板を分
離し、表面が先細りのバンプ電極を形成する工程とを備
えたことを特徴とするバンプ電極型半導体装置の製造方
法。
1. A step of forming a base metal film in ohmic contact with a plurality of regions for forming bump electrodes on a semiconductor substrate,
A step of forming a plurality of bump electrodes made of a low melting point metal on the underlying metal film by a selective plating method, and a flat substrate is attached to the surface on which the bump electrodes are formed at a predetermined pressure and temperature to melt the bump electrode surface. After that, the flat substrate is separated, and a step of forming bump electrodes having a tapered surface is provided, and a method of manufacturing a bump electrode type semiconductor device.
【請求項2】半導体基板はCCD基板である特許請求の範
囲第1項記載のバンプ電極型半導体装置の製造方法。
2. The method for manufacturing a bump electrode type semiconductor device according to claim 1, wherein the semiconductor substrate is a CCD substrate.
【請求項3】平坦基板はSi基板である特許請求の範囲第
1項記載のバンプ電極型半導体装置の製造方法。
3. The method of manufacturing a bump electrode type semiconductor device according to claim 1, wherein the flat substrate is a Si substrate.
JP60051705A 1985-03-15 1985-03-15 Method for manufacturing bump electrode type semiconductor device Expired - Lifetime JPH0789553B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60051705A JPH0789553B2 (en) 1985-03-15 1985-03-15 Method for manufacturing bump electrode type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60051705A JPH0789553B2 (en) 1985-03-15 1985-03-15 Method for manufacturing bump electrode type semiconductor device

Publications (2)

Publication Number Publication Date
JPS61210656A JPS61210656A (en) 1986-09-18
JPH0789553B2 true JPH0789553B2 (en) 1995-09-27

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JP60051705A Expired - Lifetime JPH0789553B2 (en) 1985-03-15 1985-03-15 Method for manufacturing bump electrode type semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0179473B1 (en) * 1995-04-29 1999-03-20 황인길 Planation of semiconductor package using a solder ball as input/output terminal

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5422457U (en) * 1977-07-15 1979-02-14

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Publication number Publication date
JPS61210656A (en) 1986-09-18

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