JPH0789564B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a reverse biased PN has been used as an element isolation method used in a monolithic semiconductor integrated circuit.
There are ones by joining and ones by an insulator. PN
For example, the fifth method is one in which the elements are separated by using the junction.
As shown in the figure, an N ⁻ type silicon single crystal layer 2 is epitaxially grown on a P ⁻ type silicon substrate 1. Then
A P ⁺ type diffusion layer 3 reaching the silicon substrate 1 from the main surface of the silicon single crystal layer 2 is formed by selective diffusion of a high concentration P type impurity. In this way, surrounded by a resulting P ⁺ -type diffusion layer 3 and the silicon substrate 1 N ^- -type silicon layer 4, P-N
By reverse biasing the junction, it is electrically isolated from other regions. This method can be performed at low cost, but has a problem that the area required for element isolation becomes large on the substrate surface.

In order to solve this problem, as shown in FIG. 6, a P ⁺ high concentration layer 5 is formed on a P type silicon substrate 1 by an ion implantation method, and then an epitaxial layer 6 is formed on the surface thereof in the same manner as described above. There is one in which the P ⁺ type layer 7 is sequentially formed.
According to this method, diffusion from the epitaxial layer surface by the diffusion layer 7 from the P ⁺ high-concentration layer 5 can be performed in a shorter time than that described above, and the diffusion spread in the lateral direction along the surface of the silicon substrate 1 can be performed. Can be shortened to reduce the area required for element isolation. However, such element isolation by the P-N junction has a restriction on the circuit configuration for applying a reverse bias potential, and the leakage current of the P-N junction becomes a defect and appears in the characteristics. Further, as shown in FIG. 6, even if the separation is performed by diffusion in multiple directions, the region necessary for the separation cannot be made sufficiently small, which is not suitable for a high breakdown voltage element.

On the other hand, in the case of element isolation by an insulator, for example, as shown in FIG. 7, an N ⁻ layer 12 is epitaxially grown on a P ⁻ type substrate 11, and this N ⁻ layer 12 is formed.
A groove 13 reaching the P ⁻ type substrate 11 from the main surface of is formed.
Next, after forming the thermal oxide film 14 on the inner wall surface of the groove 13,
The trench 13 is filled with a polycrystalline silicon member 15 which is not doped with impurities, and element isolation is performed in the direction along the surface of the P ⁻ type substrate 11. In this method, since the element isolation is not performed by the diffusion layer, the area required for element isolation can be reduced, and the bias voltage is also unnecessary.
However, the element region 16 surrounded by the groove 13 needs to be separated from the P ⁻ type substrate 11 by the P—N junction. Therefore, there is a restriction on the circuit configuration for applying the reverse bias potential, and P
There is a problem that leakage current of the N junction is generated.

As another example of element isolation by an insulator, as shown in FIG. 8A, first, a groove 21 is formed by selectively etching a predetermined region of the N-type silicon substrate 20. After that, a thermal oxide film 22 is formed on the surface. Then, a polycrystalline silicon layer 23 not doped with impurities is deposited on the thermal oxide film 22. Next, as shown in FIG. 3B, the back surface side of the N-type silicon substrate 20 is polished and removed until it reaches the groove 21. N-type layer 2 thus obtained
4 is an island region in which the insulator 21 is separated by the groove 21 filled with the polycrystalline silicon layer 23. This method has a large isolation breakdown voltage and does not require a bias voltage, and is particularly effective for a semiconductor device that uses only one surface region of a silicon substrate. However, there is a problem that one main surface of the semiconductor chip is insulated, the back surface cannot be used as a current path, and the cost becomes high.

[0006]

SUMMARY OF THE INVENTION According to the present invention, it is possible to surely separate insulators between elements and to reduce the area required for element separation to improve the degree of integration and to increase the power consumption of the elements. Achieved semiconductor device can be easily obtained,
It is an object of the present invention to provide a method for manufacturing a semiconductor device.

[0007]

The present invention is a first and second silicon substrate having a mirror-polished main surface, at least one of which is embedded in a predetermined surface region of the main surface. First step of preparing a silicon substrate having an insulating film formed thereon, the surface of the insulating film being flush with the main surface and being mirror-polished; and mirror-polishing of the first and second silicon substrates. The main surfaces of the
By bringing them into close contact with each other under a clean atmosphere, a second step of forming a bonded body having an insulating film inside, and a third step of applying heat treatment to the bonded body to improve the bonding strength,
By forming an element isolation region reaching the insulating film inside the bonded body from the surface of the first or second silicon substrate forming the bonded body, the element isolation region and the insulating film are surrounded. A method of manufacturing a semiconductor device, comprising: a fourth step of forming a first element region and a second element region outside the element isolation region.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, one main surface of a single conductivity type silicon single crystal substrate 30 having a high concentration of impurities is covered with a deposited layer of a thin silicon oxide film 31 and a silicon nitride film 32 by thermal oxidation. Then, the silicon nitride film 32 is partially etched and then subjected to high-temperature thermal oxidation to obtain a structure shown in FIG. That is, the silicon oxide film 31 does not grow under the silicon nitride film 32, but only the silicon oxide film 33 at the etched portion of the silicon nitride film 32 grows. Next, after removing the silicon nitride film 32 and the thin silicon oxide film 31, a resist film 34 for photo-etching is applied to cover the surface flat as shown in FIG. 1 (B). Then RIE
The resist film 34 and the silicon oxide film 33 are etched by (Reactive Ion Etching) at the same etching rate until the silicon single crystal substrate 30 is reached, and the structure shown in FIG. 1C is obtained. That is, the silicon oxide film 33 is embedded in the flat silicon single crystal surface.
Next, the silicon single crystal substrate 30 and the silicon oxide film 3
A silicon single crystal mirror substrate 34 having the same conductivity type or the opposite conductivity type as that of the silicon single crystal substrate 30 and a flat surface is adhered to the mirror substrate surface composed of 3 in a sufficiently clean atmosphere to form a strong bonded body 35 in FIG. Obtained as shown in (D). This bonded body 3
For No. 5, the joint becomes stronger when heat-treated at a temperature of 200 ° C. or higher. An insulating film is embedded inside the single silicon single crystal structure 35 (bonded body) thus bonded.

The structure composed of the silicon single crystal structure 35 having a flat surface and the insulating film can be obtained by the following means. That is, as shown in FIG. 2A, after the silicon single crystal substrate 30 is etched, O ₂ or another impurity 36 is implanted at a high concentration in this etched region. After that, when the high temperature thermal oxidation is performed, the etching rate of the etched portion 37 is higher than that of other portions, and the silicon oxide film 38 grows as shown in FIG. 2 (B). Then, as in the case of FIG. 1 (B), a resist for photo-etching is applied, and etching by RIE is performed to form silicon as an insulating film in the flat silicon single crystal surface as in FIG. 1 (C). Oxide film 38
Will be embedded. Further, as another means, for example, after the step of FIG. 1A, the silicon oxide film 31 is removed by diluted hydrofluoric acid or the like, and then high temperature thermal oxidation is performed again. Considering that the thermal oxide film 39 having a thickness of 0.55X ₀ is grown on the silicon single crystal substrate 30 with respect to the thickness X ₀ of the thermal oxide film 39, the silicon oxide film 33 of FIG. When the thickness of the reoxidation film 39 is determined, the cross-sectional shape after the reoxidation is as shown in FIG. 2 (C). After that, if the silicon oxide film 31 and the silicon nitride film 32 are removed, a flat structure can be obtained by the same means as in FIG. 1 (C). In addition to this, various means using selective epitaxial growth of a silicon single crystal, a silicon oxide film, or vapor deposition of non-doped polysilicon can be considered.

Next, another silicon single crystal substrate 34 having a flat surface is brought into close contact with each other in a clean atmosphere and bonded, and further heat-treated at a high temperature, and as shown in FIG. Silicon crystal structure 3 with embedded insulating film
5 is obtained.

According to the silicon crystal structure 35 thus constructed, the following effects can be obtained. That is, as shown in FIG. 3A, the silicon oxide film 40 reaching the silicon oxide film 33 from the main surface of the other silicon crystal body 34.
Or forming a silicon oxide film 40 reaching the silicon oxide film 33 from the main surface of the other silicon crystal body 34, as shown in FIG. The structure covered with the element region 41 can be easily obtained. As a result, the region surrounded by the silicon oxide film 33 and the silicon oxide film 40 can be completely electrically separated from the other regions of the silicon crystal structure 35. In other words, an IC having many functions such as control interface protection can be formed, and the current of the output transistor handling a large amount of power can be taken out from the back surface of the substrate (silicon single crystal substrate 30). That is, it is possible to achieve high power and multi-functionalization of the element by eliminating restrictions due to potential relations or parasitic effects on various circuit configurations and by effectively utilizing the back surface of the substrate as an electrode. Further, the required area of the element-isolated region 41 on the substrate surface (other silicon crystal body 34) is small, and high integration of elements can be achieved. If there is no problem in constructing the integrated circuit, as shown in FIG.
The element region 41 may be formed by a combination with the separation layer 42 by N junction.

In FIG. 4A, an NPN transistor 45 and N-channel and P-channel transistors 42 and 43 are formed as a control circuit in the element region 41 thus obtained, and the drain electrode of the output power MOSFET is formed. It is taken out by the back surface electrode 44.

Further, as shown in FIG. 4 (B), by arranging the insulating film embedded in the silicon single crystal substrate 30 under the element 46 requiring high breakdown voltage in the control circuit, high breakdown voltage is obtained. The element can be formed separately from the output element. Besides this, due to the structure of the element region 41,
A two-dimensional device integration along the main surface of a conventional silicon crystal body is integrated inwardly of the silicon crystal body to form a three-dimensional IC.
Can be realized.

[0014]

As described above, according to the present invention, the isolation of the insulator between the elements can be surely performed, and the area required for the isolation between the elements can be reduced to improve the degree of integration and increase the size of the element. It is possible to easily manufacture a semiconductor device that achieves power conversion.

[Brief description of drawings]

FIG. 1A to FIG. 1D are explanatory diagrams sequentially showing a main process in one embodiment of the present invention.

2 (A), (B), and (C) of FIG. 2 are explanatory views showing another example of a main process in the present invention, respectively.

3 (A) to 3 (C) are explanatory views showing the structure at the stage of forming an element region in the method of the present invention.

FIGS. 4A and 4B are explanatory views showing an example of a semiconductor device manufactured by the method of the present invention.

FIG. 5 is an explanatory view showing a method of forming element regions electrically isolated from each other in the manufacture of a conventional semiconductor device.

FIG. 6 is an explanatory diagram showing a method of forming element regions electrically isolated from each other in manufacturing a conventional semiconductor device.

FIG. 7 is an explanatory diagram showing a method of forming element regions electrically isolated from each other in the manufacture of a conventional semiconductor device.

FIG. 8 is an explanatory diagram showing a method of forming element regions electrically isolated from each other in the manufacture of a conventional semiconductor device.

[Explanation of symbols]

30 ... Silicon single crystal substrate, 31 ... Silicon oxide film, 3
2 ... Silicon nitride film, 33 ... Silicon oxide film (insulating film), 34 ... Resist film, 35 ... Silicon crystal structure (junction), 41 ... Element region.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-53-17286 (JP, A) JP-A-56-155547 (JP, A) JP-A-58-175844 (JP, A) JP-B-45- 112058 (JP, B1)

Claims (3)

[Claims] 1. A first and a second silicon substrate having mirror-polished main surfaces, at least one of which has an insulating film embedded in a predetermined surface region of the main surface, The first step of preparing a silicon substrate in which the surface of the insulating film is flush with the main surface and is mirror-polished, and the mirror-polished main surfaces of the first and second silicon substrates are opposed to each other. A second step of forming a bonded body having an insulating film inside by bringing them into close contact with each other in a clean atmosphere, and a third step of subjecting the bonded body to heat treatment to improve bonding strength, By forming an element isolation region reaching the insulating film inside the joined body from the surface of the first or second silicon substrate forming the joined body, a first surrounded by the element isolation region and the insulating film is formed. One element area and the element And a fourth step of forming a second element region outside the separated region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein one of the first and second silicon substrates forming the bonded body in which the element isolation region is not formed is exposed. A method comprising a fifth step of forming a metal electrode on a surface. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first element region is an element region for forming a control circuit element, and the second element region is a high breakdown voltage output. A method of forming an element region for forming an element.