JPH0789570B2 - 1-transistor type DRAM device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-transistor DRAM device, and more particularly to a high-density and highly reliable one-transistor DRAM device.

2. Description of the Related Art In recent years, the density of semiconductor memory devices has increased, and DRAMs have been particularly highly integrated and have a large capacity. The development of such DRAM largely depends on the development of a technology for increasing the density of memory cells, which occupy more than half of the chip size. At present, various three-dimensional structure DRAM cells have been proposed for the purpose of further increasing the density. Conventionally, this type of three-dimensional structure DRAM cell has, for example, a structure as shown in FIG. 2 (1984 ED M Digest of Technical Papers, P244-247, (IEDM)). Diges
t of Technical Papers)). Fig. 2 shows an example of a memory cell structure using a trench, which is an FCC (Folded Capacitor Ce
ll), and the trench 2 is formed in the semiconductor substrate 1.
Is formed in the depth direction, and the trench 2 is used to form a signal storage capacitor for two memory cells.
It is used for cell separation. In FIG. 2, each memory cell includes a drain 3 which constitutes a bit line,
A gate oxide film 4 of a MOS transistor which constitutes a transfer gate for signal reading, a gate electrode 5 which constitutes a word line and is formed of, for example, polysilicon, a source diffusion portion 6 which also serves as a charge storage electrode of a capacitor of a memory cell, An insulating thin film 7 forming a capacitor of a memory cell and a plate electrode 8 using, for example, polysilicon to form a cell plate are formed, and two memory cells are separated by a thick film 9 for separating cells. Reference numeral 10 is an interlayer insulating film that insulates the gate electrode 11 for the memory cells (not shown) adjacent in the word line direction. In this structure, the trench 2 is formed in the depth direction of the semiconductor substrate 1. Therefore, by setting the trench depth to a predetermined value, the storage capacitance is set to a value required as a capacitor of the memory cell (source diffusion portion of the memory cell). It is said that 50 fF or more is required to prevent an α-ray soft error caused by α particles passing through the depletion layer formed in the pn junction region under 6). Further, as described above, the trench 2 is used not only as a signal storage capacitor but also for cell separation. Therefore, by making the inter-cell separation thick film 9 thick, the inter-cell leakage current can be easily generated. It can be held low enough.

As another conventional three-dimensional structure DRAM cell, there is a stacked structure as shown in FIG. 3 (for example, June 3, 1985).
Nikkei Electronics P.209 ~ 230). In FIG. 3, reference numeral 16 denotes a semiconductor substrate, and a memory cell formed on this semiconductor substrate 16 constitutes a drain 17 forming a bit line and a signal reading transfer gate.
The gate oxide film 18 of the MOS transistor and the gate electrode formed of, for example, polysilicon, which constitutes the word line.
19, the source diffusion portion 20 of the memory cell, and the source diffusion portion 20
The charge storage electrode 21 that directly contacts the
Two memory cells (one of which is not shown) are formed between cells by an insulating film 22 formed thereon to form a capacitor of a memory cell and a plate electrode 23 formed of, for example, polysilicon to form a cell plate. They are separated by a separating thick film 24. Capacitor is plate electrode of cell plate
23 and charge storage electrode 21 forming the source portion of the memory cell
Formed during. Reference numeral 25 is an interlayer insulating film that insulates the gate oxide film 18, the gate electrode 19 and the capacitor of the MOS transistor, and the gate electrode 26 for the memory cells (not shown) adjacent in the word line direction. Since the capacitor can use the portion on the word line and the side surface of the charge storage electrode 21 as a capacitor, a large storage capacitance can be obtained. Further, the α-ray soft error is caused by α particles passing through the depletion layer formed in the pn junction region under the source portion of the memory cell as described above. The pn junction region between the semiconductor substrate 16 and the semiconductor substrate 16 is much smaller than the conventional planar type or the memory cell of the FCC structure using the trench of FIG.

Problems to be Solved by the Invention In such a conventional configuration, there are the following problems in each of the FCC structure using the trench and the stacked structure.

First, in the memory cell having the FCC structure using the trench, a required value can be secured for the storage capacity by selecting the trench 2 at a predetermined depth. However, since the trench 2 is buried in the deep portion of the semiconductor substrate 1, the depletion layer in the semiconductor substrate 1 at the lower end of the source diffusion portion 6 becomes large, and the α-ray soft error rate is larger than that of the planar cell having the same capacitance. More than an order of magnitude worse. Therefore, in order to reduce the α-ray soft error rate, it is necessary to increase the area of the capacitor cell area on the plane, which is disadvantageous for high integration.

On the other hand, by implanting ions into the side surface or the bottom surface of the trench 2, an n ⁺ p ⁺ junction is formed, so-called HI −.
Although it is possible to suppress the extension of the depletion layer by using the C cell structure, as a result of high-concentration implantation, an increase in leak current due to damage occurrence, complication of process steps, etc. occur, which is a practical problem. Further, it is necessary to form a thin insulating thin film 7 along the surface of the trench 2, and depending on the orientation of the surface of the trench 2 with respect to the crystal axis, the insulating thin film 7 (for example, Si
The oxidation rate of O ₂ ) is different, and it is difficult to grow an insulating thin film having a uniform thickness. As a result, the dielectric breakdown voltage varies and decreases, which is a practical problem. In order to increase the dielectric constant and the dielectric strength of the insulating thin film 7 that forms the capacitor of the memory cell, the insulating thin film 7 is made of Si ₃ N.
_It is necessary to use a multilayer structure composed of ₄ and SiO _2, and the single crystal sillcon of the semiconductor substrate 1 forming the inner wall of the trench 2 is affected by the stress of Si ₃ N ₄ , and the silicon of the semiconductor substrate 1 becomes defective. Are formed, the leak current increases, which is a practical problem. Obviously, these problems will become more serious obstacles when further increasing the degree of integration and capacity.

On the other hand, the stacked structure has an advantage that the region of the pn junction that becomes the source diffusion part 20 of the memory cell is small, and is therefore resistant to soft errors, and the thick wall for cell separation 24 is larger than that of the planar cell. Therefore, the leak current between cells can be easily suppressed. However, due to its structure, there is a limit to the increase in the memory cell capacity using the part on the word line and the side surface of the electrode 21, and it is inevitable that the memory cell capacity will become insufficient with the miniaturization and high integration of the cell. Is.

The present invention solves the above-mentioned problems, realizes an increase in storage capacity, enables high integration and large capacity, significantly reduces the α-ray soft error rate and leakage current, and configures a capacitor. It is an object of the present invention to provide a one-transistor type DRAM device having a memory cell structure in which an insulating film is easily formed.

Means for Solving the Problems In order to solve the above problems, the present invention provides a trench formed in a predetermined region of a semiconductor substrate of one conductivity type and a first interlayer insulation formed on an inner wall of the trench. An element isolation insulating thick film formed on the semiconductor substrate in the peripheral portion of the trench, and a conductive material opposite to the semiconductor substrate formed in the vicinity of the semiconductor substrate surface adjacent to the element isolation insulating thick film. Type signal reading MOS transistor source region, a gate insulating film of the MOS transistor formed on the semiconductor substrate adjacent to the aus region, and adjacent to the gate insulating film, with respect to the gate insulating film A drain region for a bit line having a conductivity type opposite to that of the semiconductor substrate, which is formed in the vicinity of the surface of the semiconductor substrate on the side opposite to the source region, and a trench of the isolation insulating film. A first electrode for a word line provided on the peripheral portion and the gate on an insulating film, a second interlayer insulating film formed so as to cover the first electrode, and an insulating thick film for element isolation, A cell plate second electrode layer formed of polysilicon on the first interlayer insulating film and the second interlayer insulating film, and a third interlayer provided between the second electrode layer and the source region. An insulating film, a dielectric insulating film of the memory cell capacitor formed on the second electrode layer, and a charge storage first formed on the dielectric insulating film of the memory cell capacitor and electrically contacting the source region. It has three electrode layers.

Action With the above configuration, the storage capacitance is composed of the trench portion and the portion on the other plane, and the side surface of the third electrode layer for charge storage serves as a memory capacitor in the trench portion. Therefore, the storage capacitance is made extremely large. By reducing the area of the source region as much as possible, it is possible to reduce the pn junction region between the source region of the memory cell and the semiconductor substrate, thereby reducing the leak current and the α-ray soft error rate. be able to. Furthermore, since the dielectric insulating film is formed on the second electrode layer made of polysilicon, the dielectric insulating film can be easily formed to have a uniform thickness without depending on the orientation of the oxidation rate of polysilicon. In addition, since the second electrode for the cell plate is below the third electrode for accumulating the charge which constitutes the source portion of the memory cell,
By forming the second electrode for the cell plate as thin as possible, the area of the memory capacitor inside the trench can be made large, and a memory cell having a large storage capacity can be obtained.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 (a) is a partial plan view of an essential part of a memory cell portion of a one-transistor type DRAM device according to an embodiment of the present invention, and FIG. 1 (b) is a sectional view taken along the line AA '. In FIG. 1, 31 is a semiconductor substrate of one conductivity type. A trench 32 is formed in a predetermined region of the semiconductor substrate 31, a first interlayer insulating film 38 is formed on the inner wall of the trench 32, and the periphery of the trench 32. Insulation thick film for element isolation (thick film for cell separation) on the semiconductor substrate 31
34 are formed. Memory cell signal read MOS
The transistor is formed on the surface of the semiconductor substrate 31 adjacent to the element isolation insulating thick film 34, the source region 35 of the opposite conductivity type to the semiconductor substrate 31, and on the semiconductor substrate 31 adjacent to the source region 35. The formed gate insulating film 36 and the semiconductor substrate 31 adjacent to the gate insulating film 36 and formed in the vicinity of the surface of the semiconductor substrate 31 on the side opposite to the source region 35 with respect to the gate insulating film 36 are It is composed of a drain region 37 for a bit line of the opposite conductivity type and a first electrode 38 for a word line formed on the gate insulating film 36. 38 ′
Is the first for memory cells adjacent in the word line direction
It is an electrode. The capacitor of the memory cell is formed on the second interlayer insulating film 39 formed so as to cover the first electrodes 38, 38 ', on the element isolation insulating thick film 34, and on the first interlayer insulating film 33. A cell plate second electrode layer 40 formed of polysilicon, a capacitor dielectric insulating film 41 formed on the second electrode layer 40, and a source region 35 formed on the dielectric insulating film 41. It is composed of a third charge storage third electrode layer 42 made of polysilicon which is in electrical contact. Further, a third interlayer insulating film 43 is formed between the second electrode layer 40 and the source region 35.

The operation of the above configuration will be described.

The storage capacitance is composed of a portion embedded in the trench 32 and a portion on a plane other than that. Further, in the portion of the trench 32, since the entire side surface of the third electrode layer 42 for charge storage serves as a cell capacitor, the capacitance is increased. Is greatly increased. Compared to the FCC structure with the same cell area and the same trench depth, the cell capacity is more than doubled. According to the calculation by the present inventor, when the cell area is 8 μm ² (corresponding to 4 Mbit DRAM), the trench depth is 5
By taking μm, the cell capacity can be about 85 fF,
When the cell area is 5 μm ² (equivalent to 16 Mbit DRAM), the trench depth is set to 5 μm, and
fF can be taken. It is possible to sufficiently satisfy the minimum required storage capacitance of about 50 fF for one memory cell.

Further, by reducing the area of the source region 35 as much as possible in terms of design or process technology, the pn junction region between the source region 35 of the memory cell and the semiconductor substrate 31 can be reduced, so that the memory cell The leakage current can be made extremely small. Further, since the pn junction region is small, the depletion layer associated therewith is also very small, which can drastically reduce the α ray soft error. Furthermore, when forming a thin dielectric insulating film 41 to be a capacitor on the second electrode layer 40 made of polysilicon, it is necessary to grow an insulating film having a uniform thickness without depending on the azimuth of the oxidation rate of polysilicon. Therefore, it is possible to suppress the variation and reduction of the withstand voltage as compared with the case of forming the trench in the single crystal trench.

Further, even when a multilayer structure made of Si ₃ N ₄ and SiO ₂ is used as the dielectric insulating film 41 forming the capacitor of the memory cell, the second electrode layer 40 for the plate forming the capacitor of the memory cell and the charge storage Since the third electrode layer 42 is formed of polysilicon, the influence of the stress of Si ₃ N ₄ can be absorbed without affecting the substrate, which is extremely advantageous for stable formation of the multilayer insulating film.

In addition, in particular, since the plate second electrode layer 40 is below the charge storage third electrode layer 42 forming the source portion of the memory cell, the plate second electrode layer 40 is as thin as possible in design and process. By forming it, the area of the capacitor of the memory cell inside the trench 32 can be increased, and a cell with a large capacitance can be obtained.
In this case, even if the plate second electrode layer 40 is thinly formed,
It does not affect the operation speed of the memory cell. The plate second electrode layer 40 can be formed not only on the lower portion of the charge storage third electrode layer 42 but also on the upper portion thereof. In this case, the capacity of the cell capacitor is significantly increased, and the memory cell is suitable for higher density and higher integration.

EFFECTS OF THE INVENTION As described above, according to the present invention, not only the storage capacitance can be made extremely large, but also the soft error rate and the leak current can be drastically reduced, and the insulating thin film can be easily formed in the process steps. be able to. Therefore, it is possible to obtain the effect that the higher integration and the larger capacity of the one-transistor type DRAM device can be realized very easily.

[Brief description of drawings]

FIG. 1 (a) is a plan view of an essential part of a semiconductor memory cell portion showing an embodiment of the present invention, and FIG. 1 (b) is an A- line in FIG. 1 (a).
FIG. 2 is a sectional view of an essential part of a conventional FCC structure memory cell using a trench, and FIG. 3 is a sectional view of an essential part of a conventional stacked structure memory cell. 31 ... Semiconductor substrate, 32 ... Trench, 33 ... First interlayer insulating film, 34 ... Element isolation insulating thick film, 35 ... Source region,
36 ... Gate insulating film, 37 ... Drain region, 38,38 '...
... first electrode, 39 ... second interlayer insulating film, 40 ... second electrode layer, 41 ... dielectric insulating film, 42 ... third electrode layer, 43 ... third interlayer insulating film.

Claims (1)

[Claims] 1. A trench formed in a predetermined region of a semiconductor substrate of one conductivity type, a first interlayer insulating film formed on an inner wall of the trench, and a trench formed on the semiconductor substrate in a peripheral portion thereof. An element isolation insulating thick film, and a signal reading MOS having a conductivity type opposite to that of the semiconductor, formed near the surface of the semiconductor substrate adjacent to the element isolation insulating thick film
Adjacent to the source region of the transistor, the gate insulating film of the MOS transistor formed on the semiconductor substrate adjacent to the source region, and adjacent to the gate insulating film, and opposite to the source region with respect to the gate insulating film. A drain region for a bit line having a conductivity type opposite to that of the semiconductor substrate formed in the vicinity of the surface of the semiconductor substrate on the side, and a word provided on the trench peripheral portion of the element isolation insulating thick film and on the gate insulating film. A line first electrode, a second interlayer insulating film formed to cover the first electrode, an element isolation insulating thick film, the first interlayer insulating film, and the second interlayer insulating film. A cell plate second electrode layer made of polysilicon, a third interlayer insulating film provided between the second electrode layer and the source region, and a film formed on the second electrode layer. A dielectric insulating film of Riseru capacitor, one transistor type DRAM device having said formed in the memory cell capacitor of the dielectric on the insulating third electrode layer for charge storage to electrically contact the source region.